CN117116939B - Insulated gate bipolar transistor chip and gate resistance adjusting method thereof - Google Patents
Insulated gate bipolar transistor chip and gate resistance adjusting method thereof Download PDFInfo
- Publication number
- CN117116939B CN117116939B CN202311384541.4A CN202311384541A CN117116939B CN 117116939 B CN117116939 B CN 117116939B CN 202311384541 A CN202311384541 A CN 202311384541A CN 117116939 B CN117116939 B CN 117116939B
- Authority
- CN
- China
- Prior art keywords
- conductive
- conductive structure
- resistance
- layer
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 150
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000010586 diagram Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 5
- 238000000608 laser ablation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses an insulated gate bipolar transistor chip and a gate resistance adjustment method thereof, wherein the insulated gate bipolar transistor chip comprises: a substrate; the insulated gate bipolar transistor cell area is positioned in the substrate, and insulated gate bipolar transistor cell arranged in an array manner is formed in the cell area; the bonding area is positioned on the surface of the substrate and is electrically connected to the grid electrode of each transistor cell in the cell area through the first conductive structure; wherein, the resistance of the first conductive structure is adjustable. The adjustment of the grid resistance is directly realized by adjusting the resistance value of the first conductive structure, so that the method is convenient and flexible.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an insulated gate bipolar transistor chip and a method for adjusting gate resistance thereof.
Background
In the field of high-power current control, the separation device IGBT (insulated gate bipolar transistor) still receives great attention so far and is one of the most widely applied high-power devices because of the advantages of low on-voltage drop, high voltage resistance, high process maturity and the like. The gate resistance Rg is a key factor of the IGBT switching control gate driving circuit, and has an important influence on switching frequency, switching loss, switching reliability, and the like.
The IGBT has very wide application occasions, and different application occasions have different requirements on the grid resistance Rg, but the process platform of the same type of IGBT is generally approximately fixed, and the corresponding parameters such as voltage resistance, conduction voltage drop and the like cannot meet various requirements.
How to provide a structure with an adjustable gate resistance Rg to match various requirements is a problem to be solved.
Disclosure of Invention
The invention provides an insulated gate bipolar transistor chip and a gate resistance adjusting method thereof, which realize the adjustment of the gate resistance.
The application provides an insulated gate bipolar transistor chip, comprising: a substrate; the insulated gate bipolar transistor cell area is positioned in the substrate, and insulated gate bipolar transistor cell arranged in an array manner is formed in the cell area; the bonding area is positioned on the surface of the substrate and is electrically connected to the grid electrode of each transistor cell in the cell area through the first conductive structure; wherein, the resistance of the first conductive structure is adjustable.
Preferably, the first conductive structure comprises at least two stacked conductive layers in longitudinal electrical contact, and the conductive layer on the top layer has a variable size.
Preferably, the semiconductor device further comprises a second conductive structure electrically connected to the gate of each cell; one end of the first conductive structure is electrically connected with the pressure welding area, and the other end of the first conductive structure is electrically connected to the second conductive structure.
Preferably, the second conductive structure is disposed around the edge of the cellular region; and a space is arranged between the first conductive structure and the pressure welding area, and the first conductive structure is positioned in the space.
Preferably, the first conductive structure is strip-shaped and is bent and arranged in the space.
Preferably, the first conductive structure includes: a first conductive layer, and a second conductive layer covering the surface of the first conductive layer.
Preferably, the first conductive layer is a doped semiconductor layer located in the substrate, and the second conductive layer is a metal layer; and/or the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer.
Preferably, the substrate comprises: a semiconductor substrate in which a cellular region is formed; the isolation layer is positioned at the periphery of the cellular region; the pressure welding area and the first conductive structure are positioned on the surface of the isolation layer.
Preferably, the first conductive structure includes a plurality of conductive units connected in parallel between the bonding pad and the first conductive structure.
Preferably, each of the conductive units includes at least two stacked conductive layers electrically contacted in a longitudinal direction, and the conductive layer located at the top layer has a variable size.
The application also provides a gate resistance adjustment method of the insulated gate bipolar transistor chip, which comprises the following steps: providing an insulated gate bipolar transistor chip according to any one of the above; determining a target resistance of the first conductive structure; and adjusting the resistance value of the first conductive structure to the target resistance.
Optionally, the first said first conductive structure comprises at least two stacked and longitudinally electrically contacted conductive layers; and adjusting the size of the conductive layer positioned on the top layer to adjust the resistance value of the first conductive structure to the target resistance.
According to the insulated gate bipolar transistor chip and the grid resistance adjusting method thereof, the first conductive structure with adjustable resistance is arranged between the pressure welding area and the grid, and the adjustment of the grid resistance Rg is directly realized by adjusting the resistance value of the first conductive structure, so that convenience and flexibility are realized, and the defects of plate changing and overlarge occupied chip area are avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an IGBT chip of one implementation;
fig. 2 is a schematic structural diagram of an IGBT chip of another implementation;
fig. 3 is a schematic structural diagram of an IGBT chip according to an embodiment of the present disclosure;
fig. 4a is a partial schematic diagram of an IGBT chip according to an embodiment of the present application;
fig. 4b is a schematic partial view of an IGBT chip according to an embodiment of the present disclosure after adjusting the gate resistance;
fig. 5a is a schematic cross-sectional view of an IGBT chip according to an embodiment of the disclosure;
fig. 5b is a schematic cross-sectional view of an IGBT chip according to an embodiment of the disclosure after adjusting the gate resistance;
fig. 6 is a schematic diagram of a partial structure of an IGBT chip according to an embodiment of the present application.
Detailed Description
As described in the background, it is necessary to develop a method for adjusting the gate resistance Rg conveniently, and to develop a matched gate resistance Rg for each requirement.
The IGBT chip generally includes a cell region and a gate metal pad connected to a gate connection bus of the cell region for providing a gate control voltage, and the gate resistance Rg can be adjusted by adjusting a connection resistance of the gate metal pad between the gate connection buses.
In some embodiments, please refer to fig. 1, which is a schematic top view of an IGBT chip. The IGBT chip 1 comprises a cell area 2, and a terminal area 3 is formed at the periphery of the cell area 2; the first gate metal connection line 5 is used as a gate connection bus and is electrically connected to the conductive layer below through the first gate contact hole 4; a second gate metal connection line 7 electrically connected to the lower conductive layer through the second gate metal contact hole 6; the metal bonding area 9 is electrically connected to the lower conductive layer through the metal contact hole 8 of the gate bonding area; the high-resistance polysilicon 10 is located between the metal bonding area 9 and the second gate metal connection line 7. The high resistance polysilicon 10 may be provided to obtain a desired gate resistance Rg. By changing the size of the high-resistance polysilicon 10, the gate resistance Rg can be adjusted. The method has the problems that the grid resistance Rg needs to be changed every time, and the adjustment mode is not flexible enough.
In other embodiments, referring to fig. 2, a high-resistance island metal bonding area 71 is disposed between the metal bonding area 9 and the second gate metal connection line, and a certain number of high-resistance island metal bonding areas 71 and the gate metal bonding area 9 are selectively connected by using a wire bonding 11.
The application provides a first conductive structure with adjustable resistance between a pressure welding area and a grid electrode, and the adjustment of the grid electrode resistance Rg is directly realized by adjusting the resistance value of the first conductive structure, so that the adjustment is convenient and flexible, and the defects of plate modification and overlarge occupied chip area are avoided.
The present invention will now be more fully described by way of examples with reference to the accompanying drawings.
Fig. 3 is a schematic structural diagram of an igbt chip according to an embodiment of the present application.
The insulated gate bipolar transistor chip 31 includes: a substrate, a cell region 32 within the substrate, and a bond pad region 35. The bonding pad 35 is located on the substrate surface and is electrically connected to the gate of each transistor cell in the cell area 32 through a first conductive structure 36, wherein the resistance of the first conductive structure 36 is adjustable.
The base includes a semiconductor substrate, and the cell region 32 is formed on a central region of the semiconductor substrate; an isolation layer is formed on the surface of the semiconductor substrate located at the periphery of the cell region 32; the bonding pad 35 and the first conductive structure 36 are located on the surface of the isolation layer.
Insulated gate bipolar transistor cells arranged in an array are formed in the cell region 32; the bipolar transistor comprises three electrodes, a collector (not shown) on the back side of the substrate, and a gate and an emitter on the front side of the substrate, respectively.
In order to meet the characteristic of the IBGT chip of reverse high voltage resistance, a high voltage resistant terminal area 33 is also surrounded around the chip area at the periphery of the cell area 32.
The bonding pad 35 is located on the substrate surface, particularly inside the termination region 33, adjacent to the cell region 32. The bonding pad 35 is configured to be electrically connected to the gate of each transistor cell in the cell region 32 through a first conductive structure 36; wherein, the resistance of the first conductive structure 36 is adjustable. By adjusting the resistance of the first conductive structure 36, the adjustment of the gate resistance of the IGBT chip can be achieved.
In this embodiment, a second conductive structure 34 is also formed in the cell region 32 and electrically connected to the gates of the individual cells. The second conductive structure 34 is elongated and surrounds the array of cells. The cell region 32 is also formed with gate connection lines connecting the gates of the individual cells in rows or columns, and with emitter and connection lines connecting the emitters of the individual cells in rows or columns. The second conductive structure 34 is used as a gate connection bus and connected with a gate connection line on the surface of the cell area 32, so as to realize electrical connection with the gates of the cells.
The first conductive structure 36 has one end electrically connected to the bonding pad 35 and the other end electrically connected to the second conductive structure 34, thereby electrically connecting the gates of the respective cells.
In some embodiments, the first conductive structure 36 includes at least two stacked conductive layers in longitudinal electrical contact, and the conductive layer at the top layer is of variable size. By adjusting the size of the conductive layer of the top layer, the resistance of the first conductive structure 36 can be adjusted. The dimensions may be understood as dimensions of one or more dimensions such as length, width, etc. of the top conductive layer, and may also be understood as areas, volumes, etc. of the top conductive layer; preferably, the dimension is a length. The dimensions of the conductive layer of the top layer can be changed, i.e. the resistance itself can be changed.
Specifically, the first conductive structure 36 includes: a first conductive layer, and a second conductive layer covering the surface of the first conductive layer. The second conductive layer is a conductive layer of the top layer and is positioned on the surface layer of the chip, and is easy to operate to change the size, so that the adjustment of the resistance of the first conductive structure is realized. The first conductive layer is electrically connected with the second conductive layer.
Preferably, the first conductive layer is a doped semiconductor layer located on the surface of the substrate, and specifically may be a doped polysilicon layer. The second conductive layer is a metal layer.
Similarly, the second conductive structure 34 and the first conductive structure 36 have the same composition and include a doped polysilicon layer and a metal layer on the doped polysilicon layer. The second conductive structure 34 and the first conductive structure 36 may be formed simultaneously using the same process. Specifically, the doped polysilicon layer may be formed simultaneously with the gate electrode (also doped polysilicon) of the cell in the cell region, and the metal layer is located on the top metal layer and may be formed simultaneously with other metal structures of the top metal layer.
Please refer to fig. 4a, which is a partially enlarged view of the region of fig. 3 where the bonding pad 35 is located.
Fig. 4a and 4b are schematic top views. An interlayer dielectric layer is further formed between the first conductive layer and the second conductive layer of the first conductive structure 36, and electrical connection is achieved between the first conductive layer and the second conductive layer through a conductive via 41 penetrating through the interlayer dielectric layer. The conductive via 41 is located below the second conductive layer, and the location of the conductive via is shown in a top view for ease of understanding as an illustration.
The second conductive structure 34 is disposed around the edge of the cellular region 32; there is a space between the first conductive structure 36 and the bonding pad 35, and the first conductive structure is located in the space. In order to increase the resistance adjustable range of the first conductive structure 36 as much as possible, it is necessary to increase the length of the first conductive structure 36 as much as possible within the pitch. Specifically, the first conductive structure 36 is elongated, and is bent and disposed in the space. The adjustment of the resistance value of the first conductive structure 36 is achieved by adjusting the length of the conductive layer on the top layer of the first conductive structure 36. The greater the length of the first conductive structure 36, the greater the adjustable range of resistance. The narrower the width of the first conductive structure 36, the greater the resistance adjustment accuracy, that is, the narrower the width of the first conductive structure 36, the smaller the resistance change of the corresponding first conductive structure 36, and the finer the resistance control can be achieved.
The bonding pad 35, the first conductive structure 36, and the second conductive structure 34 may have the same structure, each including a first conductive layer and a second conductive layer electrically connected one above the other, and the electrical connection of the upper and lower conductive layers is achieved by the conductive vias 43, 41, and 42, respectively. In some embodiments, the first conductive layer is high-resistance polysilicon, the second conductive layer is a metal layer, and the conductive via is a metal contact hole.
The second conductive layer has a resistance less than, preferably much less than, the resistance of the first conductive layer. Thus, when a control voltage is applied to the gate electrode, a current flows through the first conductive structure 36, mainly through the second conductive layer with smaller resistance, and at this time, the resistance of the first conductive structure 36 mainly depends on the resistance of the second conductive layer; when the dimensions of the second conductive layer are changed such that the second conductive layer is no longer connected above a portion of the first conductive layer, current can only flow through the first conductive layer when current flows, and the portion of the resistance will be determined by the resistance of the first conductive layer in that region, and thus, the change data of the dimensions of the second conductive layer determine the change of the resistance value.
When the chip is initially or leaves the factory, the second conductive layer can completely cover the first conductive layer, so that the resistance of the whole first conductive structure is basically determined by the second conductive layer, and then the area of the second conductive layer is reduced and the resistance is improved according to the tissue size required by an application scene. The second conductive layer is made of metal, and the size of the second conductive layer can be changed by laser ablation.
Fig. 4b is a schematic diagram of the first conductive structure 36 after the top conductive layer is sized based on fig. 4 a.
After removing the top conductive layer of a partial region of the first conductive structure 36, only the square first conductive layer 51 remains in the first conductive structure 36 of that region. In fact, the surface of the first conductive layer 51 is also covered by an interlayer dielectric layer, which is not shown in fig. 4b, in order to clearly show the variations of the first conductive junction 36.
Fig. 5a is a schematic cross-sectional view along the length direction of the first conductive structure 36 in fig. 4 a.
The base semiconductor substrate 61 is a first type doped silicon substrate, for example, an N-type or P-type doped substrate; an isolation layer 64 is formed on the surface of the semiconductor substrate 61, a first conductive layer 51 is formed on the surface of the isolation layer (e.g., field oxide layer), an interlayer dielectric layer 52 is formed on the surface of the first conductive layer 51, and a second conductive layer 53 is formed on the surface of the interlayer dielectric layer 52, and the first conductive layer 51 and the second conductive layer 53 are electrically connected through a conductive via 41. In this embodiment, the first conductive layer 51 is a high-resistance polysilicon layer, and the second conductive layer 53 is a metal layer. The metal layer material can be copper, aluminum, tungsten and the like.
The resistivity of the first conductive layer 51 is 10 3 Magnitude, and the resistance of the second conductive layer 53 is 10 -6 In order of magnitude, the second conductive layer 53 is the primary current path when conducting electricity.
Referring to fig. 5b, the second conductive layer 53 on the top layer is sized to adjust the resistance of the first conductive structure 36.
The second conductive layer 53 may be removed or melted away by laser ablation to a partial size of the top layer. Since the first conductive layer 51, i.e. the high-resistance polysilicon, under the first conductive structure 36 is connected in parallel with the second conductive layer 53, after the laser beam blows/melts away the second conductive layer 53 in a part of the section, the section of high-resistance polysilicon mainly takes charge of the gate signal circulation task, because the high-resistance polysilicon has relatively high resistivity, the resistance of the first conductive structure 36 increases, and thus the gate driving circuit resistance Rg of the IGBT chip increases.
The Rg size is flexibly controlled by controlling the length of the laser fuse wire so as to adapt to different application scenes.
The adjustment of the gate resistance of the IGBT chip can be achieved only by adjusting the size of the top conductive layer of the first conductive structure 36, and the first conductive structure 36 and the second conductive structure 34 can be formed simultaneously, without adding an additional photolithography mask structure and an additional process, and the size of Rg can be directly controlled. The first conductive structure 36 has a smaller size, and the arrangement area of the first conductive structure 36 can be provided only by properly reducing the size of the bonding pad, which has little influence on the chip area.
Fig. 6 is a schematic structural diagram of an igbt chip according to another embodiment of the invention.
In this embodiment, the first conductive structure 36 includes a plurality of conductive units 361, and the plurality of conductive units 361 are connected in parallel between the bonding pad 35 and the second conductive structure 34.
Each of the conductive units 361 includes at least two stacked conductive layers that are in longitudinal electrical contact, and the conductive layers on the top layer may be variable in size. The dimensions of the respective conductive units 361 may be the same or different, and may be designed as needed, without limitation.
In the single conductive unit 361, at least two conductive layers connected in parallel up and down are included, and the resistance value of the single conductive unit 361 can be adjusted by changing the size of the top conductive layer.
In the whole first conductive structure 36, since the plurality of conductive units 361 are connected in parallel, the resistance of the single conductive unit is changed, so that the resistance of the whole first conductive structure 36 is changed, and compared with the case that the single first conductive structure 36 is connected in series between the bonding pad 35 and the second conductive structure 34 in parallel, the parallel connection mode has a larger adjustment range of resistance and greater flexibility.
In the above embodiment, in the insulated gate bipolar transistor chip provided, the first conductive structure with adjustable resistance is arranged between the bonding area and the gate, and the adjustment of the gate resistance Rg is directly realized by adjusting the resistance value of the first conductive structure, so that the modification design is not required for different gate resistances.
Further, the first conductive structure comprises a plurality of stacked conductive layers, and the adjustment of the resistance of the first conductive structure can be conveniently realized by changing the size of the top conductive layer, so that the operation is convenient.
Based on the above embodiment, there is also provided a method for adjusting gate resistance of an insulated gate bipolar transistor chip, including the steps of:
step 1: an insulated gate bipolar transistor chip as in any one of the above embodiments is provided.
The insulated gate bipolar transistor chip, as in any one of the preceding embodiments, at least includes: a substrate; the insulated gate bipolar transistor cell area is positioned in the substrate, and insulated gate bipolar transistor cell arranged in an array manner is formed in the cell area; the bonding area is positioned on the surface of the substrate and is electrically connected to the grid electrode of each transistor cell in the cell area through the first conductive structure; wherein, the resistance of the first conductive structure is adjustable. The adjustment of the gate resistance value of the IGBT chip can be realized by adjusting the resistance value of the first conductive structure.
In some embodiments, the first conductive structure comprises at least two stacked conductive layers in longitudinal electrical contact, and the conductive layer at the top layer is of variable size. The resistance of the first conductive structure can be adjusted by adjusting the size of the conductive layer of the top layer.
When the insulated gate bipolar transistor chip is initially or leaves the factory, the resistance value of the first conductive structure is the minimum value, and the top conductive layer of the first conductive structure can completely cover the conductive layer below.
Specifically, the specific structure of the insulated gate bipolar transistor may be described in detail in connection with the embodiments of fig. 3 to 6, which will not be described herein.
Step 2: determining a target gate resistance;
based on the actual requirements of the application scene, the specific resistance value of the target gate resistance required by the insulated gate bipolar transistor to be adjusted can be determined, and the specific resistance value is taken as an adjustment target to adjust the gate resistance.
Referring to fig. 3, since the gate resistance of the insulated gate bipolar transistor mainly includes the resistance on the current path between the bonding pad 35 and the transistor gate in the cell region 32, the resistance of the other structures except the first conductive structure 36 on the premise of determining the chip manufacturing process and the size is fixed. Therefore, the gate resistance of the igbt can be adjusted to the target gate resistance by adjusting the resistance of the first conductive structure 36 to meet the application requirements.
Step 3: and adjusting the resistance value of the first conductive structure so that the grid resistance of the insulated gate bipolar transistor chip reaches the target grid resistance.
In the embodiment of the present invention, since the first conductive structure 36 (please refer to fig. 3) is a multi-layered stacked conductive layer, the resistance of the first conductive structure 36 can be adjusted to the target gate resistance by adjusting the size of the conductive layer located on the top layer.
Referring to fig. 5a and 5b, in some embodiments, the second conductive layer 53 of the top layer is metal, and the second conductive layer 53 of a portion of the top layer is removed by laser bombardment of the metal by laser ablation or the like. Since the first conductive layer 51 under the first conductive structure 36 is connected in parallel with the second conductive layer 53, after removing the second conductive layer 53 in a part of the section, the first conductive layer 51 (e.g. high-resistance polysilicon layer) will mainly take charge of the gate signal circulation task in this section, because the high-resistance polysilicon has relatively high resistivity, which results in an increase in the resistance of the first conductive structure 36, thereby increasing the gate driving circuit resistance value of the IGBT chip, i.e. the gate resistance Rg.
Referring to fig. 5a, before the second conductive layer 53 is resized, the current path between the gate and the bonding pad is: the bonding pad 35, the second conductive layer 53 in the first conductive structure 36, the second conductive structure 34, the transistor gate in the cell region 32; referring to fig. 5b, after the second conductive layer 53 is resized, the circuit path becomes: bond pad 35, second conductive layer 53, first conductive layer 51, transistor gates within cell region 32. The size of the second conductive layer 53 to be removed may be determined according to the difference between the target gate resistance and the current gate resistance of the chip. The Rg size can be flexibly controlled by controlling the length of the laser fuse so as to adapt to different application scenes.
Referring to fig. 6, in this embodiment, the first conductive structure 36 includes a plurality of parallel conductive units 361, and the resistance of the first conductive structure 36 is a parallel resistance value of the plurality of conductive units 361, and the size of the top conductive layer of one or more conductive units 361 can be adjusted according to the need, so as to adjust the resistance value of the first conductive structure 36.
According to the method for adjusting the grid resistance, the size of the top conductive layer of the first conductive structure can be reasonably adjusted according to different application scene requirements, so that the proper grid resistance can be obtained, the chip layout is not required to be changed, and the operation is convenient and flexible.
The foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, so that all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
Claims (9)
1. An insulated gate bipolar transistor chip, comprising:
a substrate;
the insulated gate bipolar transistor cell area is positioned in the substrate, and insulated gate bipolar transistor cell arranged in an array manner is formed in the cell area;
the bonding area is positioned on the surface of the substrate and is electrically connected to the grid electrode of each transistor cell in the cell area through the first conductive structure;
wherein, the resistance of the first conductive structure is adjustable;
the first conductive structure includes: the semiconductor device comprises a substrate, a first conductive layer and a second conductive layer covering the surface of the first conductive layer, wherein the first conductive layer is a doped semiconductor layer positioned in the substrate, and the first conductive layer is high-resistance polycrystalline silicon; the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer; the second conductive layer completely covers the first conductive layer.
2. The insulated gate bipolar transistor chip of claim 1, wherein the first conductive structure comprises at least two stacked conductive layers in longitudinal electrical contact, and the conductive layer at the top layer is of variable size.
3. The insulated gate bipolar transistor chip of claim 1 further comprising a second conductive structure electrically connected to the gate of the respective transistor cell; one end of the first conductive structure is electrically connected with the pressure welding area, and the other end of the first conductive structure is electrically connected to the second conductive structure.
4. The insulated gate bipolar transistor chip of claim 3 wherein said second conductive structure is disposed around an edge of said cell region; a space is reserved between the first conductive structure and the pressure welding area, and the first conductive structure is positioned in the space; the first conductive structure is strip-shaped and is bent and arranged in the space.
5. The insulated gate bipolar transistor chip of claim 4, wherein the second conductive layer is a metal layer.
6. The insulated gate bipolar transistor chip of claim 1, wherein the substrate comprises: a semiconductor substrate in which the cell region is formed; the isolation layer is positioned at the periphery of the cellular region; the pressure welding area and the first conductive structure are positioned on the surface of the isolation layer.
7. The insulated gate bipolar transistor chip of claim 1, wherein the first conductive structure comprises a number of conductive elements connected in parallel between the bond pad and the first conductive structure.
8. The insulated gate bipolar transistor chip of claim 7, wherein each of the conductive units comprises at least two stacked conductive layers in longitudinal electrical contact, and the conductive layer at the top layer has a variable size.
9. A method for adjusting gate resistance of an insulated gate bipolar transistor chip, comprising:
providing an insulated gate bipolar transistor chip according to any of claims 1 to 8;
determining a target resistance of the first conductive structure;
and adjusting the resistance value of the first conductive structure to the target resistance by using laser burning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311384541.4A CN117116939B (en) | 2023-10-25 | 2023-10-25 | Insulated gate bipolar transistor chip and gate resistance adjusting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311384541.4A CN117116939B (en) | 2023-10-25 | 2023-10-25 | Insulated gate bipolar transistor chip and gate resistance adjusting method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117116939A CN117116939A (en) | 2023-11-24 |
| CN117116939B true CN117116939B (en) | 2024-02-06 |
Family
ID=88795200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311384541.4A Active CN117116939B (en) | 2023-10-25 | 2023-10-25 | Insulated gate bipolar transistor chip and gate resistance adjusting method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117116939B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949533A (en) * | 2005-10-14 | 2007-04-18 | 三菱电机株式会社 | Semiconductor device |
| CN101312192A (en) * | 2007-05-25 | 2008-11-26 | 三菱电机株式会社 | Semiconductor device |
| CN101777556A (en) * | 2010-01-15 | 2010-07-14 | 无锡新洁能功率半导体有限公司 | Trench large-power MOS part and manufacturing method thereof |
| CN101877359A (en) * | 2009-04-29 | 2010-11-03 | 商海涵 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103050442A (en) * | 2012-12-20 | 2013-04-17 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN110197827A (en) * | 2018-02-26 | 2019-09-03 | 英飞凌科技奥地利有限公司 | Transistor with grid resistor |
-
2023
- 2023-10-25 CN CN202311384541.4A patent/CN117116939B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949533A (en) * | 2005-10-14 | 2007-04-18 | 三菱电机株式会社 | Semiconductor device |
| CN101312192A (en) * | 2007-05-25 | 2008-11-26 | 三菱电机株式会社 | Semiconductor device |
| CN101877359A (en) * | 2009-04-29 | 2010-11-03 | 商海涵 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN101777556A (en) * | 2010-01-15 | 2010-07-14 | 无锡新洁能功率半导体有限公司 | Trench large-power MOS part and manufacturing method thereof |
| CN103050442A (en) * | 2012-12-20 | 2013-04-17 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN110197827A (en) * | 2018-02-26 | 2019-09-03 | 英飞凌科技奥地利有限公司 | Transistor with grid resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117116939A (en) | 2023-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6587320B1 (en) | Apparatus for current ballasting ESD sensitive devices | |
| KR100199273B1 (en) | Insulated gate semiconductor device and manufacturing method thereof | |
| CN1574335B (en) | Semiconductor power device having a diamond shaped metal interconnect scheme | |
| EP0685886B1 (en) | MOS composite type semiconductor device | |
| US4963972A (en) | Gate turn-off thyristor with switching control field effect transistor | |
| EP0154998A2 (en) | Improved structure of power supply wirings in semiconductor integrated circuit | |
| US9607945B2 (en) | Semiconductor device comprising power elements in juxtaposition order | |
| US11626399B2 (en) | Semiconductor device | |
| US4412239A (en) | Polysilicon interconnects with pin poly diodes | |
| US20050274966A1 (en) | Fuse and write method for fuse | |
| CN103165677A (en) | Semiconductor device | |
| US4161740A (en) | High frequency power transistor having reduced interconnection inductance and thermal resistance | |
| US10163890B2 (en) | Semiconductor device | |
| JP4797445B2 (en) | Insulated gate bipolar transistor | |
| US4607273A (en) | Power semiconductor device | |
| EP0064231A2 (en) | Compression-type semiconductor device | |
| US11049856B2 (en) | Semiconductor device | |
| CN117116939B (en) | Insulated gate bipolar transistor chip and gate resistance adjusting method thereof | |
| EP0397727B1 (en) | Electronic appliance | |
| JP6894544B2 (en) | Manufacturing method of semiconductor devices | |
| JPS6364907B2 (en) | ||
| JP3390040B2 (en) | Integrated circuit | |
| WO1990010311A1 (en) | Mos field effect transistor controlled thyristor | |
| US20140021637A1 (en) | Semiconductor device | |
| US7368825B2 (en) | Power semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |