CN112822545A - Image display method, device and system and video controller - Google Patents
Image display method, device and system and video controller Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 230000008569 process Effects 0.000 claims description 23
- 230000009467 reduction Effects 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 5
- 230000008014 freezing Effects 0.000 claims description 5
- 238000007710 freezing Methods 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 230000006870 function Effects 0.000 description 22
- 230000015654 memory Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000000872 buffer Substances 0.000 description 3
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- 238000010168 coupling process Methods 0.000 description 3
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- 230000003287 optical effect Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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Abstract
Embodiments of the present invention relate to an image display method, an image display apparatus, an image display system, and a video controller. The image display method comprises the following steps: acquiring a target video source; performing first-direction scaling processing on the target video source according to a first scaling coefficient to obtain a first scaled video source; sending the first zoomed video source to a programmable logic device, carrying out second-direction zooming processing on the first zoomed video source by the programmable logic device according to a second zooming coefficient, wherein the second direction zooming processing is vertical to the first direction, so as to obtain a second zoomed video source, and outputting the second zoomed video source to a target display screen for displaying; wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction. The image display method provided by the embodiment of the invention realizes a low-cost narrow and long display screen with load.
Description
Technical Field
The present invention relates to the field of display control technologies of display screens, and in particular, to an image display method, an image display apparatus, an image display system, and a video controller.
Background
Currently, in the LED display industry, there are many application scenarios for long and narrow display screens, such as the application of a billboard beside a football field and the billboard in a shopping mall, wherein the long and narrow display screen refers to a display screen whose length-to-width ratio is greater than three. In order to realize the function that the video equipment can realize the video processor and the sending card in order to load the narrow and long display screen, namely, the video processor zooms the video source to the narrow and long shape, and the sending card sends the processed video source to the display screen for display.
As shown in fig. 1, currently, the loading of the narrow and long display screens is realized by splicing a plurality of common loaded video devices, and each video device loads a part of the narrow and long display screens, which increases the user cost.
Therefore, how to realize the loading of the narrow and long display screen at low cost becomes a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides an image display method, an image display device, an image display system and a video controller, which aim to realize a low-cost narrow and long display screen with load.
Specifically, in a first aspect, an embodiment of the present invention provides an image display method, including: acquiring a target video source; performing first-direction scaling processing on the target video source according to a first scaling coefficient to obtain a first scaled video source; sending the first zoomed video source to a programmable logic device, carrying out second-direction zooming processing on the first zoomed video source by the programmable logic device according to a second zooming coefficient, wherein the second direction zooming processing is vertical to the first direction, so as to obtain a second zoomed video source, and outputting the second zoomed video source to a target display screen for displaying; wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction.
In the prior art, the load of the narrow and long display screen is realized by splicing a plurality of common load-carrying video devices, so that the user cost is increased, and because each video device carries one part of the narrow and long display screen, the user needs to calculate the load-carrying area of each video device and needs to manually operate, so that the use of the user is inconvenient. According to the embodiment of the invention, the target video source is subjected to zooming twice, so that the narrow and long display screen is loaded by one video device, the cost can be reduced, the complicated manual operation work is avoided, and the user experience is improved.
In an embodiment of the present invention, the acquiring the target video source includes: receiving at least one input video source; and selecting the target video source from the at least one input video source according to a video source switching instruction.
In an embodiment of the present invention, the performing a first direction scaling process on the target video source according to a first scaling factor to obtain a first scaled video source includes: and carrying out first-direction reduction processing on the target video source according to the first scaling coefficient to obtain the first scaled video source.
In an embodiment of the present invention, the obtaining, by the programmable logic device, a second scaled video source by performing, according to a second scaling coefficient, scaling processing in a second direction perpendicular to the first direction on the first scaled video source includes: and carrying out second direction amplification processing on the first zoomed video source by the programmable logic device according to the second zoom coefficient to obtain a second zoomed video source.
In an embodiment of the present invention, the outputting, by the programmable logic device, the second scaled video source to a target display screen for display includes: and performing fade-in processing on the second zoomed video source by the programmable logic device and outputting and displaying.
In an embodiment of the present invention, before the performing the first-direction scaling process on the target video source according to the first scaling factor to obtain the first scaled video source, the method further includes: and performing de-interlacing processing on the target video source.
In a second aspect, an embodiment of the present invention provides an image display device, including: the video source acquisition module is used for acquiring a target video source; the zooming processing module is used for carrying out first-direction zooming processing on the target video source according to a first zooming coefficient to obtain a first zoomed video source; the video source sending module is used for sending the first zoomed video source to a programmable logic device, so that the programmable logic device performs zooming processing on the first zoomed video source in a second direction perpendicular to the first direction according to a second zooming coefficient to obtain a second zoomed video source, and outputs the second zoomed video source to a target display screen for display; wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction.
In a third aspect, an embodiment of the present invention provides a video controller, including: a microcontroller; the programmable logic device is connected with the microcontroller; and the video processing chip is connected with the microcontroller and the programmable logic device and is used for executing the image display method.
In one embodiment of the invention, the programmable logic device is configured to: receiving and responding to a freezing instruction sent by the microcontroller, acquiring the first zoomed video source input by the video processing chip, performing second-direction zooming processing on the first zoomed video source to obtain a second zoomed video source, caching the second zoomed video source and continuously reading the cached second zoomed video source for output and display; the video processing chip is used for: receiving and responding to a video source switching instruction sent by the microcontroller, selecting a second target video source from at least one path of video sources, and performing first-direction reduction processing on the second target video source according to the first scaling coefficient to obtain a third scaled video source; and sending the third scaled video source to the programmable logic device; the programmable logic device is further to: and gradually reducing the transparency of the second zoomed video source and improving the transparency of the fourth zoomed video source to output the second zoomed video source and the fourth zoomed video source in an aliasing manner until the transparency of the second zoomed video source is zero and the transparency of the fourth zoomed video source is one.
In a fourth aspect, an embodiment of the present invention provides an image display system, including: the system comprises a video controller and a target display screen connected with the video controller, wherein the video controller is used for executing the image display method.
In a fifth aspect, an embodiment of the present invention provides an image display system, including: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor, and the instructions cause the processor to perform operations for performing an image display method as in any one of the preceding.
In a sixth aspect, an embodiment of the present invention provides a computer-readable medium, where the computer-readable medium stores computer-readable instructions, where the computer-readable instructions include instructions for executing an image display method according to any one of the foregoing methods.
As can be seen from the above, the embodiments of the present invention can achieve one or more of the following advantages: according to the embodiment of the invention, the target video source is subjected to zooming twice, so that the narrow and long display screen is loaded by one video device, the cost can be reduced, the complicated manual operation work is avoided, and the user experience is improved.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a diagram of a prior art narrow and long display screen carried by multiple video devices;
fig. 2 is a schematic structural diagram of a video controller according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of internal modules involved in a first embodiment of a video controller according to the present invention;
FIG. 4 is a flowchart illustrating an image displaying method according to a second embodiment of the present invention;
fig. 5 is a block diagram of an image display device according to a third embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an image display system according to a fourth embodiment of the present invention;
fig. 7 is a schematic structural diagram of an image display system according to a fifth embodiment of the present invention;
fig. 8 is a schematic structural diagram of a computer-readable medium according to a sixth embodiment of the present invention.
[ description of reference ]
10: a video controller; 11: a microcontroller; 12: a programmable logic device; 13: a video processing chip;
S11-S15: the image display method step;
20: an image display device; 21: a video source receiving module; 22: a scaling processing module; 23: a video source sending module;
30: an image display system; 31: a video controller; 32: a target display screen;
40: an image display system; 41: a processor; 42: a memory;
50: a computer readable medium.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described in connection with embodiments with reference to the drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the division of the embodiments of the present invention is only for convenience of description and should not be construed as a limitation, and features of various embodiments may be combined and referred to each other without contradiction.
Before describing the embodiments of the present application, another loaded narrow-long display scheme is introduced. In particular, a video processing device is used to carry a long and narrow display screen, and the device typically uses an FPGA to implement the video source zoom function as well as the functions of the transmitter card portion. However, since all input video sources need to access the data after passing through the video decoding chips to the FPGA, and the image data signals output by each group of video decoding chips are at least 28 signals, each group of video sources needs 28 IO pins of the FPGA, and since the sending card function needs to buffer the data, DDR or SDRAM needs to be mounted, so that the demand on the pins of the PFGA is very large; in addition, because the FPGA needs to complete all scaling functions, and the FPGA needs to be buffered when completing vertical scaling, BRAM resources in the FPGA are also consumed greatly, and the resources are the most strained resources for the FPGA, so if the FPGA is used to realize all functions, an FPGA with higher cost must be selected for the type selection of the FPGA, and on a part of products which are sensitive to cost, the scheme cannot be realized, and the difficulty of scaling function algorithms is higher, and the development period is longer.
That is to say, one video device with a narrow and long display screen is used, and the functions of zooming the video source and sending the card part are mainly realized through the FPGA in the device, so that the requirement on the pin of the PFGA is very large, BRAM resources in the FPGA are also consumed very much, the FPGA with higher cost must be selected for the type selection of the FPGA, the FPGA is not suitable for the part with more sensitive cost, the difficulty of the zooming function algorithm is also high, and the development cycle is longer.
Based on this, the method of the embodiment of the present application is proposed.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 2, a first embodiment of the present invention provides a video controller. As shown in fig. 2, the video controller 10 includes, for example, a microcontroller 11, a programmable logic device 12, and a video processing chip 13. The microcontroller 11 is respectively connected with the programmable logic device 12 and the video processing chip 13, and the video processing chip 13 is also connected with the programmable logic device 12.
The microcontroller 11 is configured to send the first scaling factor to the video processing chip 13 and send the second scaling factor to the programmable logic device 12. The video processing chip 13 is configured to obtain a target video source, perform a first-direction scaling process on the target video source according to a first scaling coefficient to obtain a first scaled video source, and send the first scaled video source to the programmable logic device 12. The programmable logic device 12 is configured to perform, according to a second scaling coefficient, second direction scaling processing perpendicular to the first direction on the first scaled video source to obtain a second scaled video source, and output the second scaled video source to a target display screen for display, where a length of the target display screen in the second direction is at least three times as long as that of the target display screen in the first direction.
Specifically, the aforementioned first direction is, for example, a vertical direction, corresponding to a height direction of the video source, the aforementioned second direction is, for example, a horizontal direction, corresponding to a width direction of the video source, the aforementioned first scaling factor is a height scaling factor of the video source, which is, for example, a target height/initial height, and the first scaling factor is, for example, smaller than 1. The video processing chip 13 performs the first direction scaling process on the target video source according to the first scaling factor to obtain the first scaled video source, for example, including: and carrying out first-direction reduction processing on the target video source to obtain a first video source after scaling. The second scaling factor is a width scaling factor of the video source, which is, for example, a target width/initial width, and is, for example, greater than 1. The obtaining, by the programmable logic device 12, a second scaled video source by performing a second direction scaling process perpendicular to the first direction on the first scaled video source according to a second scaling coefficient includes: and carrying out second direction amplification processing on the first zoomed video source according to the second zoom coefficient to obtain a second zoomed video source.
The length of the mentioned target display screen in the second direction is at least three times of the length of the target display screen in the first direction, namely the width of the target display screen is at least 3 times of the height, so that the target display screen is in a narrow and long shape as a whole, and the target display screen is also called as a narrow and long display screen. The width and height ratio of the existing conventional display screen is usually 19:9, 4:3 and the like, while the target display screen mentioned in the present embodiment is an outdoor display screen, such as a display screen of a football field billboard or a market billboard, and is usually in a narrow and long shape with the width and height ratio larger than 3: 1. For example, the resolution of the target display screen is 3840 × 330.
Further, the video processing chip 13 acquiring the target video source includes, for example, receiving at least one input video source; and selecting the target video source from the at least one input video source according to a video source switching instruction sent by the microcontroller 11. Inside the video processing chip 13 is provided a Multiplexer (MUX) which can select a target video source output among a plurality of input video sources according to a video source switching instruction sent from the microcontroller 11. The input video source mentioned is, for example, a video source in the format of HDMI video source, DVI video source, USB video source, or the like. The mentioned video source switching instruction is obtained by the microcontroller 11 by responding to a command issued by a user through a human-computer interaction device, for example.
Further, when the target video source is an interlaced type video source, the video processing chip 13 is further configured to perform de-interlacing processing on the target video source after receiving the target video source. It can be understood here that the video source received by the video processing chip 13 is a non-interlaced type video source by default, that is, it is not necessary to perform de-interlacing processing on the video source, when the received video source is an interlaced type video source, the microcontroller 11 will inform the video processing chip 13 that the received video source is an interlaced type video source and it is necessary to perform de-interlacing processing, and the video processing chip 13 starts to perform de-interlacing processing on the video source, so as to accelerate the processing speed of the video source.
Further, before the programmable logic device 12 outputs the second scaled video source to the target display screen for display, the programmable logic device 12 is further configured to perform fade-in processing on the second scaled video source. The fade-in process mentioned is for example to gradually increase the transparency of the second scaled video source until the transparency is 1. Abnormal phenomena such as a black screen often can appear in a plurality of video source switching processes, and when an input video source is switched to be displayed in an output mode, fade-in and fade-out processing is carried out on the video source to be output, so that better user experience can be brought to a client.
Further, the video controller 10 further includes, for example, a memory (not shown) connected to the programmable logic device 12, such as SDRAM or DDR. The process by which the video controller 10 implements the fade-in and fade-out special effects includes, for example: firstly, the programmable logic device 12 receives and responds to a freezing instruction sent by the microcontroller 11, acquires the first zoomed video source input by the video processing chip 13, performs second-direction zooming processing on the first zoomed video source to obtain a second zoomed video source, buffers the second zoomed video source into the memory, and continuously reads the buffered second zoomed video source for output and display. Then, the video processing chip 13 receives and responds to a video source switching instruction sent by the microcontroller 11, selects a second target video source from at least one video source, performs a first-direction reduction processing on the second target video source according to the first scaling coefficient to obtain a third scaled video source, and sends the third scaled video source to the programmable logic device 12. Finally, the programmable logic device 12 performs a second direction amplification process on the third scaled video source according to the second scaling coefficient to obtain a fourth scaled video source, and gradually reduces the transparency of the second scaled video source and increases the transparency of the fourth scaled video source to output the second scaled video source and the fourth scaled video source in an aliasing manner until the transparency of the second scaled video source is zero and the transparency of the fourth scaled video source is one. The programmable logic device 12 gradually changes the respective transparencies of the second scaled video source and the fourth scaled video source, and then outputs the two video sources in an aliasing manner until the transparency of the second scaled video source is 0 and the transparency of the fourth scaled video source is 1, thereby implementing the fade-in process of the fourth scaled video source and the fade-out process of the second scaled video source.
The Microcontroller 11 is, for example, an MCU (Microcontroller Unit), which is also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer; or, other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors. The Programmable logic device 12 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device. The video processing chip 13 is a chip having a video image processing capability.
To facilitate understanding of the present embodiment, a specific implementation of the video controller provided in the present embodiment is described below with reference to fig. 3.
As shown in fig. 3, in the present embodiment, a scheme of a video processing IC, that is, a video processing chip + FPGA + MCU is adopted, the video processing IC completes switching among various video sources, de-interlacing processing, and scaling processing in a vertical direction, and the FPGA only needs to receive 1 channel of processed video sources, and thus scaling and fade-in and fade-out functions in a horizontal direction are implemented. In the prior art, as the FPGA is required to complete all functions, the resource requirement on the FPGA is excessive, and the method mainly includes that data of all input video sources after passing through the video decoding chips is required to be accessed into the FPGA, and the data output by each group of video decoding chips is at least 28 signals, so that each group of video sources needs 28 IO pins of the FPGA, and because the data needs to be cached due to the function of a sending card, DDR or SDRAM needs to be mounted, so that the requirement on the pins is large; in addition, because the FPGA completes all scaling functions, and the FPGA needs line buffering to implement vertical scaling, BRAM resources in the FPGA are consumed greatly, and the resources are the most strained resources for the FPGA, and in addition, the FPGA needs to consume DDR or SDRAM as frame buffering and BRAM and other resources when implementing the de-interlacing function, so if the FPGA is used to implement all functions, the FPGA with higher cost must be selected for the selection of the FPGA, and on a part of products with more sensitive cost, the scheme cannot be implemented, and the difficulty of function algorithms such as de-interlacing and scaling is also higher, and the development period is longer.
Compared with the prior art, the FPGA related to the embodiment of the invention only needs to receive the 1-path processed video source, namely the FPGA only needs to consume 28 pins. In addition, the FPGA implements scaling in the horizontal direction, not all scaling. For the video processing IC, the output pixel width of the video processing IC cannot exceed 2048 pixel width of the VESA standard generally, because the video processing IC cannot perform scaling to a narrow and long size, for example, to 3840 width, the scaling in the horizontal direction is realized by using the FPGA, and the FPGA does not need to consume extra line buffers when realizing scaling in the horizontal direction, so that the FPGA resource consumption is low, and the FPGA is convenient to select. Because the special effect function of fade-in fade-out can not be realized when the video source of the video processing IC is switched, the special effect of fade-in fade-out can be realized by utilizing other resources of the FPGA.
For example, in practical applications, it is necessary to implement dual-portal tape-loading 130 ten thousand pixels, but the shape of the display screen is 3840 × 330, and the size of the input video source is 1080P (1920 × 1080), so in order to meet such a requirement, the input video source 1080P needs to be scaled to 3840 × 330, in this embodiment, the video processing IC implements scaling in the vertical direction, that is, the vertical direction scales 1080 down to 330, the horizontal direction needs to scale 1920 up to 3840, the video processing IC in the general 1080P bandwidth processing range outputs 2048 pixel width which cannot exceed the VESA standard generally, and thus, the FPGA implements scaling in the horizontal direction to 3840 size.
The process of implementing the fade-in and fade-out special effect by the FPGA includes, for example: firstly, the MCU sends a freezing instruction to the FPGA, the FPGA captures a frame of image transmitted by the video processing IC and caches the image in the SDRAM after acquiring the freezing instruction, and the frame of image is continuously output.
And then, the MCU sends a video source switching instruction to the video processing IC, and the video processing IC finishes the processes of video source switching action, video source zooming processing and the like after obtaining the instruction.
And finally, after the FPGA receives the switched video source, aliasing the received image and the image which is cached in the SDRAM, gradually reducing the transparency (Alpha) of the frozen frame cached before, gradually increasing the transparency of the new image frame until the transparency of the new image is 1 and the transparency of the frozen frame is 0, thereby realizing the complete fade-in and fade-out effect.
In summary, the video processing chip in the video controller disclosed in the embodiment of the present invention performs the first-direction scaling on the target video source, and then sends the target video source to the programmable logic device for the second-direction scaling, and then outputs the target video source, thereby avoiding the disadvantage that the FPGA realizes the video scaling and the card sending part function in the prior art, reducing the pin requirement on the FPGA, avoiding the excessive consumption of BRAM resource of the FPGA, reducing the scaling function difficulty, shortening the development cycle, having wider applicability, avoiding the situation of loading multiple video devices, reducing the cost, avoiding the tedious work of manual operation, and improving the user experience.
[ second embodiment ]
Referring to fig. 4, a second embodiment of the present invention proposes an image display method. As shown in fig. 4, the image display method includes, for example, steps S11 to S15.
Step S11: acquiring a target video source;
step S13: performing first-direction scaling processing on the target video source according to a first scaling coefficient to obtain a first scaled video source;
step S15: and sending the first zoomed video source to a programmable logic device, carrying out second-direction zooming processing on the first zoomed video source by the programmable logic device according to a second zooming coefficient, wherein the second-direction zooming processing is vertical to the first direction, so as to obtain a second zoomed video source, and outputting the second zoomed video source to a target display screen for displaying, wherein the length of the target display screen in the second direction is at least three times that of the target display screen in the first direction.
The target video source mentioned in step S11 is, for example, a video source in a video format such as an HDMI video source, a DVI video source, or a USB video source. Step S11 includes, for example: receiving at least one input video source; and selecting the target video source from the at least one input video source according to a video source switching instruction. The mentioned video source switching instruction is issued by the MCU, for example.
Step S13 includes, for example: and carrying out first-direction reduction processing on the target video source according to the first scaling coefficient to obtain the first scaled video source. The first mentioned direction is, for example, a vertical direction, corresponding to a height direction of the video source, and the first mentioned scaling factor is a height scaling factor of the video source, which is, for example, a target height/an initial height, and the first mentioned scaling factor is, for example, smaller than 1.
The step S15, where the obtaining of the second scaled video source by the programmable logic device performing the second direction scaling processing perpendicular to the first direction on the first scaled video source according to the second scaling factor, includes: and carrying out second direction amplification processing on the first zoomed video source by the programmable logic device according to the second zoom coefficient to obtain a second zoomed video source. The second direction is, for example, a horizontal direction, and corresponds to a width direction of the video source, the second scaling factor is a width scaling factor of the video source, which is, for example, a target width/an initial width, and the second scaling factor is, for example, greater than 1.
Further, the outputting, by the programmable logic device, the second scaled video source to the target display screen for displaying in step S15 includes: and performing fade-in processing on the second zoomed video source by the programmable logic device and outputting and displaying. The fade-in process mentioned is for example to gradually increase the transparency of the second scaled video source until the transparency is 1. Abnormal phenomena such as a black screen often can appear in a plurality of video source switching processes, and when an input video source is switched to be displayed in an output mode, fade-in and fade-out processing is carried out on the video source to be output, so that better user experience can be brought to a client.
Further, before step S13, the image display method according to this embodiment further includes, for example: and performing de-interlacing processing on the target video source. It can be understood here that the deinterlacing of the target video source is performed by, for example, issuing a command by the MCU, informing that the received video source is an interlaced type video source, and the deinterlacing is required, and then the deinterlacing of the video source is started, so that the processing speed of the video source is increased.
It should be noted that, for example, the image display method provided in the embodiment of the present invention is implemented in the video processing chip in the video controller disclosed in the first embodiment, and for brevity, the description of the specific method steps may refer to the description of the working process of the video processing chip in the first embodiment, and will not be repeated herein.
In summary, the image display method provided in the second embodiment of the present invention performs the first-direction scaling on the target video source and then sends the target video source to the programmable logic device for the second-direction scaling and then outputs the target video source, thereby avoiding the disadvantage that the FPGA implements the video scaling and the card sending part functions in the prior art, reducing the pin requirement for the FPGA, avoiding excessive consumption of BRAM resources of the FPGA, reducing the scaling function difficulty, shortening the development cycle, having wider applicability, avoiding the situation of loading multiple video devices, reducing the cost, avoiding the tedious work of manual operation, and improving the user experience.
[ third embodiment ]
Referring to fig. 5, a third embodiment of the present invention provides an image display device. As shown in fig. 5, the image display device 20 includes, for example, a video source acquisition module 21, a scaling processing module 22, and a video source transmission module 23.
The video source obtaining module 21 is configured to obtain a target video source. The scaling module 22 is configured to perform a first-direction scaling process on the target video source according to a first scaling coefficient to obtain a first scaled video source. The video source sending module 23 is configured to send the first zoomed video source to a programmable logic device, so that the programmable logic device performs a second-direction zooming process perpendicular to the first direction on the first zoomed video source according to a second zooming coefficient to obtain a second zoomed video source, and outputs the second zoomed video source to a target display screen for display; wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction.
It should be noted that the image display method implemented by the image display device 20 provided in the present embodiment is as described in the foregoing second embodiment, and therefore, the detailed description thereof is omitted here. Optionally, each module and the other operations or functions in the third embodiment are respectively for implementing the method in the second embodiment of the present invention, and the technical effect of the image display device 20 provided in this embodiment is the same as that of the method in the second embodiment, and for brevity, are not described herein again.
[ fourth example ] A
Referring to fig. 6, a fourth embodiment of the present invention provides an image display system. As shown in fig. 6, the image display system 30 includes, for example: a video controller 31 and a target display screen 32.
For example, the video controller 31 is the video source controller 10 disclosed in the first embodiment, which is configured to execute the image display method described in the second embodiment, and for related descriptions, reference may be made to the first embodiment and the second embodiment, which are not described herein again for brevity.
The target display screen 32 is, for example, an LED display screen, the width of which is at least 3 times the height, so that it as a whole assumes a long and narrow shape, also referred to as a long and narrow display screen. The width to height ratio of conventional displays is typically 19:9, 4:3, etc., while the target display 32 is an outdoor display, such as a football field billboard or a mall billboard, typically having a narrow-to-long shape with a width to height ratio greater than 3:1, and the resolution of the target display 32 is 3840 x 330, for example.
It should be noted that the target display screen 32 is configured with a receiving card for carrying the target display screen 32 to display, the video controller 31 is connected to the receiving card through a network cable, for example, and the receiving card is connected to the target display screen 32 through a flat cable. The mentioned receiving cards include, for example: network cable interface, programmable logic device, microcontroller, bus cable interface, etc.
The technical effect of the image display system 30 provided in this embodiment is the same as that of the video controller 10 described in the first embodiment, and for brevity, no further description is provided here.
[ fifth embodiment ]
Referring to fig. 7, a fifth embodiment of the present invention provides an image display system. As shown in fig. 7, the image display system 40 includes, for example: a processor 41 and a memory 42 connected to the processor 41. Wherein the memory 42 stores instructions executed by the processor 41, and the instructions cause the processor 41 to perform operations to perform the image display method as described in the second embodiment.
The image display method performed by the processor 41 according to the second embodiment is the same as that described in the second embodiment, and therefore, the image display system 40 according to the present embodiment is not described in detail herein. The technical effect of the image display system 40 provided in the present embodiment is the same as that of the image display method in the second embodiment.
[ sixth embodiment ]
Referring to fig. 8, a sixth embodiment of the present invention provides a computer-readable medium. As shown in fig. 8, the computer readable medium 50 stores computer readable instructions, which include instructions for executing the image display method according to the second embodiment, and therefore, will not be repeated here.
The computer-readable medium 50 is, for example, a non-volatile memory, and includes: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., Read Only Memories (ROMs), Random Access Memories (RAMs), flash memories, etc.). The computer-readable medium 50 may be executable by one or more processors or processing devices to execute computer-readable instructions. The technical effect of the computer readable medium 50 provided in this embodiment is the same as that of the image display method in the second embodiment, and is not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An image display method, comprising:
acquiring a target video source;
performing first-direction scaling processing on the target video source according to a first scaling coefficient to obtain a first scaled video source;
sending the first zoomed video source to a programmable logic device, carrying out second-direction zooming processing on the first zoomed video source by the programmable logic device according to a second zooming coefficient, wherein the second direction zooming processing is vertical to the first direction, so as to obtain a second zoomed video source, and outputting the second zoomed video source to a target display screen for displaying;
wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction.
2. The image display method according to claim 1, wherein the acquiring the target video source comprises:
receiving at least one input video source;
and selecting the target video source from the at least one input video source according to a video source switching instruction.
3. The image display method according to claim 1, wherein the performing the first direction scaling process on the target video source according to the first scaling factor to obtain a first scaled video source comprises:
and carrying out first-direction reduction processing on the target video source according to the first scaling coefficient to obtain the first scaled video source.
4. The image display method according to claim 1, wherein the obtaining, by the programmable logic device, a second scaled video source by performing a second direction scaling process perpendicular to the first direction on the first scaled video source according to a second scaling factor comprises:
and carrying out second direction amplification processing on the first zoomed video source by the programmable logic device according to the second zoom coefficient to obtain a second zoomed video source.
5. The image display method of claim 1, wherein outputting, by the programmable logic device, the second scaled video source to a target display screen for display comprises:
and performing fade-in processing on the second zoomed video source by the programmable logic device and outputting and displaying.
6. The image displaying method according to claim 1, wherein before the performing the first direction scaling process on the target video source according to the first scaling factor to obtain the first scaled video source, the method further comprises:
and performing de-interlacing processing on the target video source.
7. An image display apparatus, comprising:
the video source acquisition module is used for acquiring a target video source;
the zooming processing module is used for carrying out first-direction zooming processing on the target video source according to a first zooming coefficient to obtain a first zoomed video source;
the video source sending module is used for sending the first zoomed video source to a programmable logic device, so that the programmable logic device performs zooming processing on the first zoomed video source in a second direction perpendicular to the first direction according to a second zooming coefficient to obtain a second zoomed video source, and outputs the second zoomed video source to a target display screen for display;
wherein a length of the target display screen in the second direction is at least three times a length of the target display screen in the first direction.
8. A video controller, comprising:
a microcontroller;
the programmable logic device is connected with the microcontroller;
a video processing chip connected to said microcontroller and said programmable logic device for performing the image display method of any one of claims 1-6.
9. The video controller of claim 8,
the programmable logic device is to:
receiving and responding to a freezing instruction sent by the microcontroller, acquiring the first zoomed video source input by the video processing chip, performing second-direction zooming processing on the first zoomed video source to obtain a second zoomed video source, caching the second zoomed video source and continuously reading the cached second zoomed video source for output and display;
the video processing chip is used for:
receiving and responding to a video source switching instruction sent by the microcontroller, selecting a second target video source from at least one path of video sources, and performing first-direction reduction processing on the second target video source according to the first scaling coefficient to obtain a third scaled video source; and sending the third scaled video source to the programmable logic device;
the programmable logic device is further to: and gradually reducing the transparency of the second zoomed video source and improving the transparency of the fourth zoomed video source to output the second zoomed video source and the fourth zoomed video source in an aliasing manner until the transparency of the second zoomed video source is zero and the transparency of the fourth zoomed video source is one.
10. An image display system, comprising:
the system comprises a video controller and a target display screen connected with the video controller;
wherein the video controller is configured to perform the image display method of any one of claims 1 to 6.
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