FR2844053A1 - Electronic pulse duration evaluation circuit for natural radiation effect assessment has memory connected to outputs of chain of integrated circuits and counts outputs reset - Google Patents

Abstract

An electronic pulse duration evaluation circuit has a chain of integrated circuits (D1-n) with outputs connected to memory comprising flip flops (Bi) with the other input connected to a clock (CLK) and computation circuit (1) to determine the number of circuits disturbed from the rest condition. Includes an Independent claim for connection to the flip flops through multiplexers with one input fed from the flip flop outputs.

Description

CIRCUIT FOR EVALUATING THE DURATION OF ELECTRIC PULSES

  The present invention relates to the analysis of electrical pulses induced in an integrated circuit receiving occasional external disturbances such as natural radiation. More particularly, the present invention aims to provide a device for precise evaluation of the duration of an electric pulse induced in an element of an integrated circuit by an external disturbance. Such a circuit element can for example be a transistor, an elementary logic circuit such as an OR gate, an AND gate, or an inverter,

  or any item in a cell library.

  Knowledge of the duration of such electrical pulses makes it possible to predict by simulation the behavior of integrated circuits affected by such disturbances, to design integrated circuits having an operation less sensitive to external disturbances, and / or to provide modes

suitable repairs.

  Thus, the present invention provides a circuit for evaluating the duration of an electric pulse induced in an element of an integrated circuit, comprising a chain of said elements in series, having at their output a given level of rest, each element being likely to receive a disturbance

  occasional external causing it to supply a pulse and being connected to transmit a revised pulse to the next element, storage means for storing at a given instant the output levels of the elements and a determination means for determining the number of storage means indicating levels distinct from the rest level.

  According to an alternative embodiment of such an evaluation circuit, the storage means consist of flip-flops controlled by the same clock signal, the output of each circuit element being connected to the data input of a flip-flop, the data output of each flip-flop being

connected to the means of determination.

  According to another alternative embodiment of such an evaluation circuit, the storage means consist of flip-flops in series controlled by the same clock signal and of several multiplexers, the output of a flip-flop being connected to a first input of a multiplexer whose output is connected to the data input of the next flip-flop, the second inputs of the multiplexers receiving the outputs of the 20 circuit elements, the data output of the last flip-flop

  being connected to the means of determination.

  According to one embodiment of such an evaluation circuit, a detector circuit indicates whether none, only one,

  or several scales have changed state.

  According to one embodiment of such an evaluation circuit, the data output of the last flip-flop is connected to a counter which counts the number of successive flip-flops whose stored levels are distinct from the rest levels, the counter receiving the levels memorized in series when the multiplexers are positioned so as to pass the memorized levels from one scale to another at the rate

of the clock signal.

  According to one embodiment, the evaluation circuit described above further comprises a control circuit which initially positions the multiplexers in a capture mode by connecting the outputs of the circuit elements to the data inputs of the flip-flops, which positions the multiplexers in a counting mode so as to pass the memorized levels from one flip-flop to another when the detector circuit 5 indicates that at least two flip-flops have changed state, and which reposition the multiplexers in capture mode when

  the counter indicates the end of the count.

  According to an embodiment of an evaluation circuit as described above, the circuit elements are non-inverting circuits and the flip-flops are initialized at level "0", and in which the detector circuit comprises two first OR gates, each first OR gate receiving one out of two flip-flop data outputs, the outputs of the first two OR gates entering a second OR gate and into an AND gate, the control circuit receiving the outputs of the

second OR gate and AND gate.

  According to an embodiment of an evaluation circuit as described above, the circuit elements are inverter circuits and the flip-flops are initialized for half at level "0" and for half at level "1", and in which the detector circuit comprises a first OR gate receiving the outputs of the flip-flops initialized at "0", and a first AND gate receiving the outputs of the flip-flops initialized at "1", the outputs of the first two gates entering a second OR gate and in a second AND gate, the control circuit receiving the outputs of the second OR gate and the

second AND gate.

  The present invention also provides a method for evaluating the duration of an electric pulse induced in an integrated circuit element comprising the following steps: - placing a large number of said circuit elements in series in a state of rest, each element circuit being connected to propagate to the next circuit element, a pulse supplied by the preceding circuit element; - Periodically store in storage means the level at the output of each circuit element; - determine the number of storage means

  indicating levels distinct from the rest level.

  According to an alternative implementation of the above-mentioned evaluation method, the determination step is only implemented when it has been detected that at least two means of

  successive memorizations have changed state.

  These and other objects and features and advantages of the present invention will be explained in detail.

  in the following description of particular embodiments given without limitation in relation to the

  attached figures, among which: FIG. 1 is a diagram of an evaluation circuit 15 according to an embodiment of the present invention; Figure 2 is a diagram of an evaluation circuit according to another embodiment of the present invention; and Figure 3 is a more detailed diagram of the circuit of

Figure 2.

  FIG. 1 is a diagram of a circuit for evaluating the duration of an electrical pulse induced in a circuit element by an external disturbance. The evaluation circuit, produced as an integrated circuit, comprises several circuit elements D1 to Dn in series between an input E and an output S. Each circuit element D1 to Dn is connected so as to be able to propagate towards the next circuit element, a pulse from the previous circuit element. In the case for example where the circuit elements are AND gates with two inputs, each AND gate has an input connected to a fixed voltage equal to "1", an input connected to the output of the AND gate

  previous and an output connected to the next AND gate. The circuit elements D1 to Dn shown in FIG. 1 are non-inverting logic circuits. It is used in the present invention the fact that any element of an integrated circuit 35 transmitting a signal imposes a delay on this signal.

  To be placed in conditions close to the conditions of actual use, the circuit elements D1 to Dn can be connected to the charges represented here in the form of capacitors C1 to Cn connected between the output of each circuit element and the ground. The output of each circuit element Di, i being between 1 and n, is connected to the data input of a flip-flop Bi. The flip-flops B1 to Bn are controlled by the same clock signal CLK. A calculation circuit 1 receives the levels 10 stored in the flip-flops B1 to Bn and provides on an output 2,

  the duration of the electrical pulse.

  Input E is permanently positioned at a level

  determined, for example at level "0". In the absence of external disturbance, the output of each circuit element is equal to "0".

  When a circuit element receives an external disturbance, its internal state is liable to be modified. The output of the circuit element "affected" changes state and passes, in this example, from level "O" to level "1". When the state of the affected circuit element returns to normal, its output reverts to level "0". The affected circuit element thus produces a

  electrical impulse whose duration is desired.

  The electric pulse propagates in the circuit elements positioned after the affected circuit element 25 until the last circuit element Dn. During the propagation of the electric pulse, the number of circuit elements having an output at "1" at a given time depends on the delay imposed by

  each circuit element and the duration of the pulse.

  At each rising edge of the clock signal CLK, the flip-flops B1 to Bn store the level at the output of each circuit element. The duration of the electrical pulse is proportional to the number of levels "1" stored in flip-flops B1 to Bn. The calculation circuit 1, counts the number k of flip-flops having a level "1" and supplies on output 2 this number k in binary form. The propagation time of a

  circuit element is generally short and much less than the duration of an electrical pulse induced by a disturbance.

  The number k is therefore at least equal to two.

  The duration of the measured electrical pulse is then 5 equal to the number k recorded multiplied by the propagation time Tp of a circuit element Di. The duration of the pulse is longer

  precisely between (k-l) Tp and (k + l) Tp.

  Before a pulse duration measurement can be made, it is necessary to know the propagation time of a circuit element. This propagation time may be provided by the manufacturer of integrated circuits, be obtained by electrical simulation (for example with a SPICE simulator), or be measured using the circuit of the present invention. One could for example create a pulse on the input E and raise the level at the output of each of the circuit elements at the rate of the clock signal CLK whose period varies. When the levels "1" stored on two consecutive edges of the clock signal are shifted on average by more than one flip-flop, the period of the clock signal CLK is greater than the propagation time of a circuit element . When the levels "1" memorized on two consecutive edges of the clock signal are shifted - on average by less than one rocker, the period of the clock signal CLK is shorter than the propagation time of a circuit element . By successive tests, the propagation time of a circuit element can be determined. Of course, other means may be used to measure this propagation time. FIG. 2 represents an evaluation circuit according to another embodiment of the present invention. The evaluation circuit comprises, as before, several circuit elements D1 to Dn (possibly associated with loads not shown) in series between an input E and an output S. The output of each circuit element Di is connected to a first input of a multiplexer Mi. The output of each multiplexer Mi is connected to the data input of a flip-flop Bi. The data output of each flip-flop Bi is connected to the second input of the multiplexer Mi + l. The second input of the first multiplexer M1 is connected to its first input or to a terminal SC which can be controlled or positioned at level "0". The output of 5 data from the last flip-flop Bn is connected to a counter 4 (CNT). The flip-flops B1 to Bn are controlled by a clock signal CLK. The multiplexers M1 to Mn are controlled by the same selection signal Il. The outputs of flip-flops B1 to Bn are connected to a detector circuit 5 which indicates to a control circuit 10 of control CTR 6, on each rising edge of the clock signal CLK, if none, only one or more flip-flops have changed state. As for the evaluation circuit of FIG. 1, the input E is permanently positioned at level "0". The 15 outputs of circuit elements D1 to Dn, non-inverters in this

  example, are at "0" in the absence of external disturbance.

  As long as the detector circuit 5 indicates that no flip-flop has changed state, the control circuit provides the multiplexers with a selection signal O such that each multiplexer links the output of a circuit element to the input d 'a rocker. We are then in a "capture" mode. The flip-flops B1 to Bn store at the rate of the clock signal CLK,

  the output level of each of the circuit elements.

  When the detector 5 indicates that a single flip-flop has changed state, we are in the case where a multiplexer Mi or a flip-flop Bi has been affected by a disturbance. The control circuit 6 does not change the state of the selection signal (and possibly activates a reset signal r which

  resets flip-flops B1 to Bn at level "0".

  When the detector circuit 5 indicates that several flip-flops have changed state, we are in the case where a circuit element has been touched. The control circuit 6 changes the state of the selection signal O and we go into "counting" mode. The output of each flip-flop B1 to Bn is connected to the input of the next flip-flop. At the rate of the clock signal CLK, the levels memorized in the flip-flops B1 to Bn (a series of "O", a series of "1" and a series of "O") pass from one flip-flop to another and arrive in series in counter 2. Counter 2 is incremented for each level "1" received. Preferably, the counter 2 is stopped when the received levels become equal to "0". The counter 2 then supplies on an output 7, the number of levels "1" memorized. The counter 2 activates an end of counting signal SF which indicates to the control circuit 6 that the circuit can return to capture mode. The control circuit 6 10 controls a change of state of the selection signal O so that the outputs of the circuit elements D1 to Dn are again connected to the flip-flops B1 to Bn and activates the signal of

  reset r of flip-flops B1 to Bn.

  FIG. 3 shows the diagram of the evaluation circuit 15 of FIG. 2, detailing the detector circuit 5 and the

circuit elements D1 to Dn.

  Each circui-t element Di is composed of two inverters in series Dia and Dib. The detector circuit 5 includes three OR gates 10, 11, 12 and an AND gate 13. The OR gate 10 20 receives the output of the odd flip-flops, B1, B3, B5, etc. The

  OR gate 11 receives the output of even flip-flops, B2, B4, - B6 etc. The OR gates 12 and AND 13 receive the outputs of the OR gates 10 and 11. The OR gate 12 supplies the control circuit 6 with a detection signal SD. The AND gate 13 supplies the control circuit 6 with a validation signal SV.

  Initially, the flip-flops B1 to Bn are at level "0".

  The outputs of the OR gates 10 and 11 are at "0", and the SD signals

and Sv are zero.

  When an external disturbance occurs on a multiplexer Mi or a flip-flop Bi, only the level memorized in this flip-flop Bi is modified. In this case, only one of the two OR gates 10 and 11 goes to "1". The signal SD then goes to "1" and the signal Sv remains at "0". The control circuit 6 activates the

  reset signal r of flip-flops B1 to Bn.

  When an external disturbance occurs on an element

  circuit, several flip-flops B1 to Bn, at least two, store a "1" on the next edge of the clock signal CLK.

  The two signals SD and SV go to "1", and the control circuit 6 changes state of the selection signal O in order to enter the counting mode. Once the counting is finished, the control circuit 6 resets the flip-flops B1 to Bn and the circuit

  evaluation returns to capture mode.

  Of course, the present invention is susceptible to various variations and modifications which will be apparent to those skilled in the art. In particular, flip-flops B1 to Bn can be flip-flops that can be activated on a rising or falling edge or a

  level "1" or "0" of the CLK clock signal.

  In the case where the detection system is slow, and the reaction time of the detector circuit 5 and of the control circuit 6 is greater than one period of the clock signal CLK, the flip-flops which have switched at the first attempt clock will return to their initial state on the second clock stroke. In order to avoid losing the information stored in the flip-flops, according to a variant of the invention, a system for preserving their state is provided. In the case where the circuit elements are non-inverting, it is possible to add n OR gates with two inputs (not shown) between the circuit elements D1 to Dn and the multiplexers M1 to Mn, the output of each OR gate 25 being connected to an input of a multiplexer and receiving the output of the circuit element initially connected to this multiplexer and the data output of the flip-flop to which this multiplexer is connected. Consequently, once the flip-flops have changed to "1", they remain in this state at each clock stroke as long as the signal (O has not caused them to be connected in series. In this case, it is necessary that the pulse to be detected is found in the circuit elements at a position disjoint from its previous position during the next clock stroke. To do this, the clock period must be greater than the sum of the duration of l 'impulse

  and the propagation time of a circuit element.

  In addition, provision could be made for the circuit elements to be reversers, for example NAND gates, 5 NOR gates or even simple reversers. The even flip-flops are initialized at a fixed level, for example "0", and the odd flip-flops are initialized at a different fixed level, for example "1". In this case, the detector circuit will not comprise two OR gates 10 and 11 but a NAND gate 10 connected to the data outputs of the pair flip-flops and a gate

  OR connected to the data outputs of the odd flip-flops.

  Of course, those skilled in the art will choose the number of circuit elements and the period of the clock signal, taking into account the minimum possible duration between two incidences of disturbances, the propagation time of the circuit elements used. and the estimated duration of a pulse. The number of circuit elements must be sufficiently high for the probability of receiving a disturbance to be sufficiently high. In addition, the period of the clock signal 20 must be short enough so that the probability of missing a disturbance is relatively low. It is also necessary that during the minimum time between two disturbances there is time to carry out the detection and counting operations

described above.

  We can place on a single chip several chains of separate circuit elements for which we want to analyze the reaction to a disturbance. We could possibly make a chain composed of various circuit elements in series to

  use a common detection and measurement circuit.

Claims (10)

  1. Circuit for evaluating the duration of an electric pulse induced in an element of an integrated circuit, comprising: - a chain of said elements (D1 to Dn) in series, 5 having at output a given level of rest, each element being capable of receiving an occasional external disturbance causing it to supply a pulse and being connected to transmit a received pulse to the next element; storage means for storing the output levels of the elements at a given instant; and - determining means (1; 4) for determining the number of storage means indicating levels separate from the rest level.   2. Evaluation circuit according to claim 1, in which the storage means consist of flip-flops (B1 to Bn) controlled by the same clock signal (CLK), the output of each circuit element (Di) being connected to the data input of a flip-flop (Bi), the data output of each   rocker being connected to the means of determination.   3. Evaluation circuit according to claim 1, in which the storage means consist of flip-flops (B1 to Bn) in series controlled by the same clock signal (CLK) and several multiplexers (M1 to Mn), the output of a flip-flop (Bi) being connected to a first input of a multiplexer (Mi) 25 the output of which is connected to the data input of the next flip-flop (Bi + 1), the second inputs of the multiplexers receiving the outputs of the circuit elements (D1 to Dn), the data output of the last flip-flop (Bn) being connected to the determination means. 4. Evaluation circuit according to claim 3, further comprising a detector circuit (5) indicating whether   none, only one, or several scales have changed state.   5. Evaluation circuit according to claim 3, in which the data output of the last flip-flop (Bn) is   connected to a counter (4) which counts the number of successive flip-flops whose memorized levels are distinct from the rest levels, the counter receiving the levels memorized in series when the multiplexers (M1 to Mn) are positioned so as to pass the memorized levels from one rocker to another at the rate of the clock signal (CLK).   6. Evaluation circuit according to claims 4 and   , further comprising a control circuit (6) which: - initially positions the multiplexers (M1 to Mn) 10 in a capture mode by connecting the outputs of the circuit elements (D1 to Dn) to the data inputs of the flip-flops (B1 to Bn), - positions the multiplexers in a counting mode so as to pass the memorized levels from one flip-flop to another when the detector circuit indicates that at least two flip-flops have changed state, and - reposition the multiplexers in capture mode   when the counter indicates the end of the count.   7. Evaluation circuit according to claim 6, in which the circuit elements (D1 to Dn) are non-inverting circuits and the flip-flops (B1 to Bn) are initialized at level "O", and in which the detector circuit (5) comprises two first OR gates (10, 11), each first OR gate receiving a second flip-flop data output, the outputs of the first two OR gates entering a second OR gate (12) and 25 into an AND gate (13), the control circuit receiving the   second OR gate and AND gate outputs.   8. Evaluation circuit according to claim 7, in which the circuit elements (D1 to Dn) are inverter circuits and the flip-flops (B1 to Bn) are initialized for half at level 11011 and for half at level "1" , and in which the detector circuit (5) comprises a first OR gate receiving the outputs of the flip-flops initialized at "0", and a first AND gate receiving the outputs of the flip-flops initialized at "1", the outputs of the first two doors entering a second OR gate (12) and in a second AND gate (13), the control circuit receiving the outputs of the second OR gate and the second AND gate.   9. Method for evaluating the duration of an electric pulse induced in an integrated circuit element, characterized in that it comprises the following steps: - placing a large number of said circuit elements (D1 to Dn) in series in a idle state, each circuit element being connected to propagate to the next circuit element, a pulse supplied by the preceding circuit element; - Periodically store in storage means the level at the output of each circuit element; - determine the number of storage means   indicating levels distinct from the rest level.   10. The evaluation method as claimed in claim 9, in which the determination step is only implemented when at least two successive storage means have been detected. have changed state.