GB2266608A - Protocol simulation apparatus for dynamically verifying a communication protocol - Google Patents
Protocol simulation apparatus for dynamically verifying a communication protocol Download PDFInfo
- Publication number
- GB2266608A GB2266608A GB9308627A GB9308627A GB2266608A GB 2266608 A GB2266608 A GB 2266608A GB 9308627 A GB9308627 A GB 9308627A GB 9308627 A GB9308627 A GB 9308627A GB 2266608 A GB2266608 A GB 2266608A
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- simulation
- processes
- protocol
- diagram
- state transition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
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- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
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- Computer And Data Communications (AREA)
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Abstract
Data for a process relation diagram 5, simulation environment diagram, and a communication protocol, for communication software under development are input at 2. According to the communication protocol, a state transition diagram for each process is generated at 8. According to the state transition diagram, a simulation is executed at 11. Before the execution of the simulation, the simulation environment is checked. In addition, any error which takes place during the simulation is detected. The execution result of the simulation is displayed at 3 on the simulation environment diagram and on the state transition diagram. <IMAGE>
Description
Protocol Simulation Apparatus For Dynamically Verifying
A Communication Protocol
The present invention relates to a protocol simulation apparatus for simulating a communication protocol being designed upon developing a communication software application.
When a protocol (namely a communication procedure required in processes which are operational substances of a communication system) is verified in a development stage of a communication software application, defects such as deadlock and reception disable state can be detected by statically analyzing the description of the protocol.
However, when a protocol is dynamically verified in consideration of a transmission time (for example, when a task processing time in a process is verified or in the case where a signal is transmitted through a channel), a site test should be conducted with a real system or a simulation system after the protocol has been designed and coded. Thus, the dynamic verification requires a large amount of time and cost. In this case, if a relevant protocol has an error, the protocol should be sometimes redesigned from the beginning. The necessity of such dynamic verification causes a sequence of protocol design work to be complicated.
As described above, dynamic verification of a communication protocol (namely, verification associated with a time element) involves various problems. Thus, so far, it was difficult to simulate such a protocol with high efficiency.
The present invention is made from the above-mentioned point of view.
A first object of the present invention is to provide a protocol simulation apparatus for automatically performing dynamic verification of a protocol without necessity of real environment or simulation environment so as to remarkably improve the efficiency of protocol verification work.
A second object of the present invention is to provide a protocol simulation apparatus for allowing an error which took place in a dynamic verification process for a protocol to be user-friendly displayed so as to easily analysis the cause thereof.
To accomplish such objects, the present invention is a protocol simulation apparatus for dynamically verifying a communication protocol, comprising a first input means for inputting a process relation diagram, the process relation diagram being adapted to graphically represent at least a plurality of processes and channels connected thereof, a second input means for inputting at least a communication amount of each of the channels, a signal transmission time of each of the channels, and an entire task processing time of a simulation on the process relation diagram so as to generate simulation environment diagram, a third input means for inputting at least a plurality of communication protocols for the processes, a protocol description and generation means for generating a state transition diagram for each of the processes according to the communication protocols, a simulation execution means for executing a simulation according to the state transition diagram, for checking the communication amount, the signal transmission time, the entire task processing time, and for detecting an error which takes place during the simulation, and a display means for displaying an execution result of the simulation execution means on the simulation environment diagram and on the state transition diagram.
According to the present invention, simulation environment such as the communication amount of a channel connected between processes, the signal transmission time of the channel, the task processing time of a process, and a timeout time is preset. In the simulation environment, the operation of the communication protocol is simulated according to the state transition diagram. While the simulation is being executed, if errors such as an unexecutable transition state and a channel overflow take place, they are defected and displayed on the display means.
Therefore, according to the present invention, a protocol can be automatically verified without necessity of special real environment or simulation environment and thereby the efficiency of the protocol verification process can be remarkably improved.
These and other obJects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
Fig. 1 is a block diagram showing the system construction of a protocol simulation apparatus according to an embodiment of the present invention
Fig. 2 is a schematic diagram showing an example of a process relation diagram of a communication system described by a process relation diagram description portion;
Fig. 3 is a schematic diagram showing simulation environment which is set by simulation environment set portion according to the process relation diagram of Fig. 2;
Figs. 4 (a) and (b) are schematic diagrams showing communication protocols described by a protocol description portion;
Figs. 5 (a) and (b) are schematic diagrams showing examples of state transition diagrams of processes PI and P2 composed by a state transition schematic generation portion;
Fig. 6 is a flow chart showing a processing procedure of the entire system of the protocol simulation apparatus of Fig.
1;
Fig. 7 is a flow chart showing a processing procedure of an event of each process of Fig. 6;
Fig. 8 is a flow chart showing a processing procedure of a channel;
Fig 9 is a flow chart showing a processing procedure of a FIFO queue;
Fig. 10 is a schematic diagram showing a verification result display upon occurrence of a channel overflow;
Fig. 11 is a schematic diagram showing a state transition diagram where the channel overflow of Fig. 10 took place;
Fig. 12 is a schematic diagram showing a processing procedure between processes according to the state transition diagram of Fig. 11;
Fig. 13 is a schematic diagram showing a verification result display upon occurrence of an unexecutable transition state;
Fig. 14 is a state transition diagram where an unexecutable transition state of Fig. 13 took place;;
Fig. 15 is a schematic diagram showing a processing procedure between processes according to the state transition diagram of Fig. 14;
Fig. 16 is a schematic diagram showing a verification result display upon occurrence of a deadlock state;
Fig. 17 is a state transition diagram where the deadlock of Fig. 16 took place;
Fig. 18 is a schematic diagram showing a processing procedure between processes according to the state transition diagram of Fig. 17;
Fig. 19 is a schematic diagram showing a verification result display upon occurrence of an unspecified reception state;
Fig. 20 is a state transition diagram where the specified ree ion state of Fig. 19 took place; and
Fig. 21 is a schematic diagram showing a processing procedure between processes according to the state transition diagram of Fig. 20.
Next, with reference to the accompanying drawings, an embodiment of the present invention will be described.
Fig. 1 is a block diagram showing the system construction of a protocol simulation apparatus according to an embodiment of the present invention.
In the figure, reference numeral 1 is a main body of the apparatus. Reference numeral 2 is an input unit such as a keyboard. Reference numeral 3 is a display unit such as a
CRT. Reference numeral 4 is an external storage unit (for database) such as a floppy disk unit. In the main body of the apparatus, reference numeral 5 is a process relation description portion generates a process relation diagram according to data being input by the user. Reference numeral 6 is a protocol description portion describes a communication protocol according to data being input by the user. Reference numeral 7 is a static protocol verification portion which automatically (and logically) verifies a communication protocol described by the protocol description portion 6.
Reference numeral 8 is a state transition diagram generation portion which automatically composes a state transition diagram according to a protocol which has been designed.
Reference numeral 9 is a source code generation portion which automatically generates a source code according to a state transition diagram which has been composed. Reference numeral 10 is simulation environment set portion which sets simulation environment necessary for dynamically verifying a communication protocol according to data being input by the user. Reference numeral 11 is a simulation execution portion which dynamically verifies a communication protocol in predetermined simulation environment according to a state transition diagram. Reference numeral 12 is a display control portion which displays a current simulation situation for example a state transition diagram of a protocol which is being simulated, simulation environment, an error position of the protocol, and the contents of the error so that the user can easily understand the situation.
Fig. 2 is a schematic diagram showing an example of a process relation diagram of a communication system. The process relation diagram has been described by the process relation diagram description portion 5. In the process relation diagram, circles represent processes. The user is present outside each process. Arrow marks which connect between the user and each process and between processes represent channels.
Fig. 3 is a schematic diagram showing simulation environment which has been set by the simulation environment set portion 10 according to the process relation diagram. The simulation environment includes the communication capacity of each channel (capacity), the signal transmission time between two channels (timer), the task processing set time T (= 6.0its), and the time unit. The unit of the channel communication capacity is the number of messages.
Along with the contents of such environment, the entire task processing time (Ta) of the simulation is displayed on simulation environment screen. In addition, as a process manager PM, the task processing time of each process (ptime), the event-awaited state (wait), and the timer time (not shown in the figure) are displayed on the simulation environment screen. These contents are updated by the simulation execution portion 11 during the simulation process.
Figs. 4 (a) and (b) are schematic diagrams showing communication protocols described by the protocol description portion 6. These figures show sequential charts with respect to signal exchange and each processing of processes P1 and P2.
Figs. 5 (a) and (b) are schematic diagrams showing examples of state transition diagrams of processes P1 and P2 which are automatically composed by the state transition diagram generation portion 8. In these figures, an oval symbol (for example, symbol a) represents the state of a process. A rectangular symbol (for example, symbol b) represents the processing of a task, In addition, a concave symbol (for example, symbol c) represents a signal reception processing. A convex symbol (for example, symbol d) represents a signal transmission processing. Moreover, each transmission/ reception symbol describes the contents thereof with a process name (signal name). A process which does not have a process name represents a processing communicating with the external environment.A long rectangular symbol (for example, symbol c) represents a conditional branch state.
In addition, for example "1T" associated with a task processing symbol (symbol b) represents a time for which the processing of the task requires. For instance, "T.O = 20T" associated with a reception symbol e in Fig. (a) represents a timeout time These task processing time and timeout time are set by the simulation environment set portion 10.
When a simulation is executed, the simulation environment diagram and the state transition diagram are displayed at a time
Next, the operation of the protocol simulation apparatus according to the present invention will be described.
Fig. 6 is a flow chart showing the entire processing procedure of the system. The simulation execution portion 11 interprets each symbol on the state transition diagram of each process and executes a corresponding event process (at step 602). However, in advance, the simulation execution portion 11 has checked the event-awaited state of each process (at step 601). Only when the event-a waited state of each process is neither "initial state (IDLE)" nor "internal signal-awaited state (I)", the simulation execution portion 11 executes such an event processing.
Fig. 7 is a flow chart showing an event processing procedure of each process. The event processing of each process is executed when the task processing time of each process (ptime) is equal to the entire task processing time (Ta) of the simulation (at step 701).
The simulation execution portion 11 checks the type of the event (at step U2). Whe the simulation execution portion 11 has detected an "external signal reception" event or an "internal condition determination (state transition branch)" event, it displays all available branch states to prompt the user for selection (at step 703). Thereafter, the simulation execution portion 12 executes the processing of the next event (at step 704) and returns control back to step 702.
At step 702, when the simulation execution portion 11 has detected an "internal signal reception" event, it checks the current state of the FIFO queue (at step 705). When the simulation execution portion 11 has determined that the FIFO queue stores a correct signal, it obtains the signal therefrom (at step 706). At this point, the simulation execution portion 11 sets the event-awaited state to "else" (at step 707). Thereafter, the simulation execution portion 11 executes the processing of the next event (at step 708) and returns control back to step 701. On the other hand, when the simulation execution portion 11 has determined that the FIFO queue is empty, it sets the event-awaited state to "internal signal reception wait (I)" (at step 709). At this point, the processing is normally terminated (at step 710).When the simulation execution portion 11 has determined that the FIFO queue stores a signal other than the desired signal, it informs the user of the unspecified reception state (at step 711). At this point, the processing is abnormally terminated (at step 712).
When the simulation execution portion 11 has detected an "external/internal signal transmission" event at step 702, it sends this signal to 2 channel connected to a relevant process (at step 713). Thereafter, the simulation execution portion 11 executes the processing of the next event (at step 708) and returns control back to step 701.
As shown in Fig. 8, the signal which is sent to the channel is stored therein until the signal transmission time which is set thereto elapses. After the set time has elapsed (at step 801), the simulation execution portion obtains the signal from the channel and sends it to the FIFO queue (at step 802).
As shown in Fig. 9, the FIFO queue can receive a number of signals which are equivalent to the communication capacity of the channel which is set in the simulation environment set processing. When the number of signals exceeds the communication capacity (at step 901), the simulation execution portion 11 estimates that a channel overflow took place and informs the user thereof (at step 902).
At step 702, when the simulation execution portion 11 has detected a "timer ON" event at step 702, it activates a timer attribute of the process manager PM so as to set a timer (at step 714). Thereafter, the simulation execution portion 11 executes the processing of the next event (at step 708) and returns control back to step 701.
When the simulation execution portion 11 has detected a "timer OFF" event at step 702, it cancels the setting of the timer (at step 715). Thereafter, the simulation execution portion 11 executes the processing of the next event (at step 708) and returns control back to step 701.
When the simulation execution portion 11 has detected a "task processing" event at step 702, it wastes the task processing time which is set in the simulation environment set processing so as to advance the task processing time (ptime) of the process managed by the process manager PM for the event processing time (at step 716). Thereafter, the simulation execution portion 11 executes the processing of the next event (at step 717). At this point, the processing is normally terminated (at step 718).
At step 601 shown in Fig. 6, when the wait states of all processes are "internal signal reception wait (I)", the simulation execution portion 11 executes the following processing or the like.
The simulation execution portion 11 checks the states of all channels and the FIFO queue and whether a timer has been set (at step 604). As a result, when all the channels and all the FIFO queues are blank and a timer has not been set, the simulation execution portion 11 assumes that a deadlock state took place and informs the user thereof (at step 605). At this point, the processing is abnormally terminated (at step 606).
When all the awaited states are "internal signal reception wait (I)" and at least one of the channels and the
FIFO queue has a signal, or when all the channels and all the
FIFO queues do not have signals and a timer has been set, both the entire task processing time Ta and the task processing time of the relevant process (ptime) are extended for one task processing time (at steps 607 and 608). In addition, the timer time of a process where a timer has been set is extended for one task processing time 609).
Thereafter, the simulation execution portion 11 compares the timer time with the timeout time (at step 610). When the timer time exceeds the timeout time, the simulation execution portion 11 assumes that an unexecutable state transition state took place and informs the user thereof (at step 611). When the timer time does not exceed the timeout time, the simulation execution portion 11 returns control back to step 601.
The simulation execution portion 11 executes the simulation according to the state transition diagram of each process in the above-mentioned procedure. When the simulation execution portion 11 has determined that all the states of the processes are "initial state (IDLE)" at step 601, it terminates the processing of the simulation (at step 612).
Next, with reference to Figs e 10 to 12, the operation with respect to an occurrence of a channel overflow will be described. Fig. 10 shows an example of the display in this case.
As described above, the channel overflow is detected when the number of signals which have been sent to a relevant channel exceeds the communication capacitance thereof. In the example shown in Fig. 10, it is assumed that a communication capacity of "2" has been set to a channel. In addition, although the FIFO queue stores two signals, another signal is sent from the channel to the FIFO queue. Thus, a channel overflow took place. Fig. 11 shows a state transition diagram where a channel overflow took place. In the figure, the symbols which are hatched are being verified. On the state transition diagram, a process P2 has a processing for "saving data for a time of 4T (save data)". Thus, a channel overflow took place. Fig. 12 is a schematic diagram showing the detail of the occurrence of the channel overflow of Fig. 11.As shown in Fig. 12, at "4T" of the entire task processing time, the third signal which exceeds the communication capacity of the channel is sent to the FIFO queue.
Next, with reference to Figs. 13 to 15, the operation with respect to an occurrence of an unexecutable transition state will be described. Fig. 13 is a schematic diagram showing an example of the display in this state.
When the timer time of the process exceeds the timeout time of the process, an unexecutable transition state takes place. Fig. 14 is a state transition diagram where the unexecutable transition state took place. Fig. 15 shows the processing procedure between processes according to the state transition diagram. For a process P1, "4T" is defined as a set timeout time. However, since the signal transmission for each of channels P12 and P21 between processes P1 and P2 takes "2T" and the processing of the process P2 takes "iT", a total of "5T" is required. In the state 1 of the process P1, a timeout takes place. Thus, "+P2(ack)" and "+P2(nck)" are not executed.
Next, with reference to Figs. 16 to 18, the operation with respect to an occurrence of a deadlock state will be described. Fig. 16 shows an example of the display in this case.
As described above, an occurrence of a deadlock state is detected when each process is in an "internal signal wait state, channels between processes and the FIFO queue are empty, and a timer has not been set. Fig. 17 shows a state transition diagram where a deadlock state took place. Fig. 18 shows the processing procedure between processes according to the state transition diagram. In this example, in "state 1" of processes P1 and P2, a deadlock state took place.
Last, with reference to Figs. 19 to 21, the operation with respect to an occurrence of an unspecified reception state will be described. Fig. 19 shows an example of the display in this case.
As described above, when a signal other than a required signal is stored in the FIFO queue, an occurrence of the unspecified reception state is detected. Fig. 20 shows a state transition diagram where an unspecified reception state took place. Fig. 21 shows the processing procedure between processes according to the state transition diagram. In this example, processes P1 and P2 wait for a "- > P2(ack)" signal and a "+Pl(ack)" signal, respectively. However, instead,
Pl(call)" and "-P2(call)" signals are received. Thus, since the received signals differ from the required signals, the unspecified reception state is detected.
Thus, according to the protocol simulation apparatus of the present invention, a protocol can be designed while the operation thereof is being checked. Therefore, a protocol dealing with a timeout processing can be accurately designed.
As a result, the protocol can be effectively designed and verified.
In addition, according to the present invention, dynamic verification of a protocol can be automatically and interactively performed. As a result, the development time and cost of a communication system can be remarkably reduced.
Moreover, according to the present invention, error states such as channel overflow state, unexecutable transition state, deadlock state, and unspecified reception state can be user-friendly displayed. Furthermore, since the state transition diagram which is being verified is also displayed, the user can easily know the cause of an error.
Although the present invention has been shown and described with respect to a best mode embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions, and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention.
Claims (11)
1. A protocol simulation apparatus for dynamically verifying a communication protocol, comprising:
first input means for inputting a process relation diagram, said process relation diagram being adapted to graphically represent at least a plurality of processes and channels connected thereof;
second input means for inputting at least a communication amount of each of said channels, a signal transmission time of each of said channels, and an entire task processing time of a simulation on said process relation diagram so as to generate simulation environment diagram;
third input means for inputting at least a plurality of communication protocols for said processes;
protocol description and generation means for generating a state transition diagram for each of said processes according to said communication protocols;;
simulation execution means for executing a.simulation according to said state transition diagram, for checking said communication amount, said signal transmission time, said entire task processing time, and for detecting an error which takes place during said simulation; and
display means for displaying an execution result of said simulation execution means on said simulation environment diagram and on said state transition diagram.
2. The protocol simulation apparatus as set forth in claim 1,
wherein said state transition diagram is adapted to represent at least the state of each of said processes, a signal reception processing, a signal transmission processing, and a task processing with respective discrete symbols, and
wherein said simulation execution means is adapted to interpret symbols on said state transition diagram and to execute event processing according to said symbols so as to execute said simulation.
3. The protocol simulation apparatus as set forth in claim 1,
wherein said simulation execution means has timer means, said timer means being activated when a timer setting according to said state transition diagram is detected, said simulation execution means being adapted to detect an error as an unexecutable transition state when a timer time of said timer means exceeds said signal transmission time or said entire task processing time which are input from said second input means.
4. The protocol simulation apparatus as set forth in claim 3,
wherein said display means is adapted to display said error as said unexecutable transition state on said simulation environment diagram and on said state transition diagram.
5. The protocol simulation apparatus as set forth in claim 1,
wherein said simulation execution means is adapted to detect an error as a channel overflow when the number of signals sent to each of said channels exceeds the communication capacity thereof.
6. The protocol simulation apparatus as set forth il; claim 5,
wherein said display means is adapted to display said error as said channel overflow on said simulation environment diagram and on said state transition diagram.
7. The protocol simulation apparatus as set forth in claim 1, further comprising
logical verification means for logically verifying said communication protocols of said processes being input from said third input means.
8. A simulation apparatus for simulating a system having a plurality of processes which are mutually correlated, comprising:
first input means for inputting said processes and mutual relations thereof;
second input means for inputting a dynamic condition of each of said processes and a dynamic condition of each of said mutual relations;
simulation execution means for correlating said processes so as to execute a simulation of said system, for checking the dynamic condition of each of said processes and the dynamic condition of each of said relations, and for detecting errors of these dynamic conditions which take place during said simulation; and
display means for displaying an execution result of said simulation execution means.
9. The simulation apparatus as set forth in claim 8, further comprising:
logical verification means tor logically verifying said relations of said processes being input from said third input means
10. A simulation method for dynamically verifying a communication protocol, comprising the steps of::
inputting a process relation diagram, said process relation diagram being adapted to graphically represent at least a plurality of processes and channels connected thereof;
inputting at least a communication amount of each of said channels, a signal transmission time of each of said channels, and an entire task processing time of a simulation on said process relation diagram so as to generate simulation environment diagram;
inputting at least a plurality of communication protocols for said processes;
generating a state transition diagram for each of said processes according to said communication protocols;
executing a simulation according to said state transition diagram, for checking said communication amount, said signal transmission time, said entire task processing time, and for detecting an error which takes place during said simulation; and
displaying an execution result of said simulation execution step on said simulation environment diagram and on said state transition diagram.
11. The simulation method as set forth in claim 10, further comprising the step of:
logically verifying communication protocols of said processes.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4111538A JPH05307511A (en) | 1992-04-30 | 1992-04-30 | Protocol simulation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9308627D0 GB9308627D0 (en) | 1993-06-09 |
| GB2266608A true GB2266608A (en) | 1993-11-03 |
Family
ID=14563903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9308627A Withdrawn GB2266608A (en) | 1992-04-30 | 1993-04-26 | Protocol simulation apparatus for dynamically verifying a communication protocol |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH05307511A (en) |
| FR (1) | FR2690803B1 (en) |
| GB (1) | GB2266608A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040429A1 (en) * | 1996-04-19 | 1997-10-30 | Kvaser Consultant Ab | Method and equipment for setting up a protocol/system protocol |
| GB2430328A (en) * | 2005-09-19 | 2007-03-21 | Itt Mfg Enterprises Inc | Modelling/simulating a network node including a plurality of protocol layers with selectively configurable switches disposed between and coupling the layers |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3169896B2 (en) | 1998-07-03 | 2001-05-28 | 日本電気株式会社 | Program development device, program development method, and storage medium storing program development program |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61208945A (en) * | 1985-03-14 | 1986-09-17 | Kokusai Denshin Denwa Co Ltd <Kdd> | Split verification system of protocol |
| JPS62114358A (en) * | 1985-11-14 | 1987-05-26 | Kokusai Denshin Denwa Co Ltd <Kdd> | System for synthesizing automatically protocol |
| JPS63286947A (en) * | 1987-05-20 | 1988-11-24 | Hitachi Ltd | Automatic verification system for protocol |
| US5038307A (en) * | 1989-10-30 | 1991-08-06 | At&T Bell Laboratories | Measurement of performance of an extended finite state machine |
| JPH03178245A (en) * | 1989-12-07 | 1991-08-02 | Nippon Telegr & Teleph Corp <Ntt> | Protocol processing system |
| JPH03295339A (en) * | 1990-04-13 | 1991-12-26 | Oki Electric Ind Co Ltd | Test system for protocol verification |
-
1992
- 1992-04-30 JP JP4111538A patent/JPH05307511A/en active Pending
-
1993
- 1993-04-26 GB GB9308627A patent/GB2266608A/en not_active Withdrawn
- 1993-04-30 FR FR9305138A patent/FR2690803B1/en not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| INSPEC abstract B84038124 & Proc.'83 Military CommunicationsConference, Vol 2, pp 481-485 * |
| INSPEC abstract B87028162-C87025952 & Proc. IEEE Int. Conf. on Communications '86, Vol 1, pp 222-227 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040429A1 (en) * | 1996-04-19 | 1997-10-30 | Kvaser Consultant Ab | Method and equipment for setting up a protocol/system protocol |
| US7188162B1 (en) | 1996-04-19 | 2007-03-06 | Kvaser Consulant Ab | Method and equipment for setting up a protocol/system protocol |
| GB2430328A (en) * | 2005-09-19 | 2007-03-21 | Itt Mfg Enterprises Inc | Modelling/simulating a network node including a plurality of protocol layers with selectively configurable switches disposed between and coupling the layers |
| GB2430328B (en) * | 2005-09-19 | 2010-03-10 | Itt Mfg Enterprises Inc | Network modelling system and method of simulating network operation with configurable node models |
| US7765093B2 (en) | 2005-09-19 | 2010-07-27 | Itt Manufacturing Enterprises, Inc. | Network modeling system and method of simulating network operation with configurable node models |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2690803B1 (en) | 1996-03-15 |
| GB9308627D0 (en) | 1993-06-09 |
| JPH05307511A (en) | 1993-11-19 |
| FR2690803A1 (en) | 1993-11-05 |
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| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |