GB2423618A

GB2423618A - Addressable device using shared power and communications connections with a switched programming connection

Info

Publication number: GB2423618A
Application number: GB0605231A
Authority: GB
Inventors: Sacho Petkov Parvanov; Stephen Ronald Glover
Original assignee: Novar Systems Ltd
Current assignee: Novar Systems Ltd
Priority date: 2004-03-15
Filing date: 2004-03-15
Publication date: 2006-08-30
Anticipated expiration: 2024-03-15
Also published as: GB0405756D0; GB2423618B; GB0605231D0; GB2412216B; GB2412216A

Abstract

An addressable device 3 is provided with a pair of electrical connections 1J, 1K arranged for both connection to an electrical power supply 1P for powering the device and for connection to a controller 2 for bi-directional communication with the device. A third electrical connection 1Q is provided for receiving a switched input to or output from the device. The device is arranged to receive programming instructions by means of a voltage waveform applied across the pair of electrical connections together with a synchronous voltage waveform applied at the third electrical connection. By using all three connections simultaneously, this device is able to reduce the risk that the device may be accidentally programmed while fitted in an installation. Also disclosed is an addressable device which receives information by means of a cyclic waveform (e.g. a DC or square wave), the device being arranged to confirm, after a delay, the presence of high or low voltage signals.

Description

Improvements in and relating to addressable devices The present invention

relates to addressable devices having a pair of electrical connections for both powering the device and for communicating with the device.

Addressable devices are used for providing communication between controllers and distributed sensors or controls. For example, in burglar alarm systems, they may be used in detectors to communicate an alarm signal to a control panel. In an electrical installation system, addressable devices may be used to provide information on the current status of lighting and power devices, such as heating equipment, or environmental information, such as room temperature or external temperature. Such addressable devices using a single pair of electrical connections for both powering the device and for communicating with the device are particularly easy to install, requiring only simple two conductor wire, running from the controller in series to each addressable device. The controller being arranged to provide a suitable power supply for and communication with the addressable devices.

According to a first aspect of the present invention, there is provided an addressable device having a pair of electrical connections arranged for both connection to an electrical power supply for powering the device and for connection to a controller for bi-directional communication with the device, the device being arranged to receive information by means of a cyclic waveform of the electrical power supply, each cycle comprising a sequence of two consecutive voltage transitions from a low voltage to a high voltage and from the high voltage to the low voltage, or from a high voltage to a low voltage and from the low voltage to the high voltage, the addressable device having means to detect the transitions, means to detect the low or the high voltage levels between transitions, the device being arranged to confirm after a delay the presence of the high or low voltage levels.

A benefit of the addressable device measuring the signal voltage level of each cycle after a delay is that the addressable device is not affected by any noise or instability of the cyclic waveform or the electrical power supply voltage in the period of the delay following the transition.

Preferably the electrical power supply is substantially a direct current voltage.

A benefit of the electrical power supply being a direct current voltage supply is that a source of electrical noise may be avoided.

Preferably the delay is at least forty percent of the half cycle, or time interval between consecutive transitions.

A benefit of the delay being at least forty percent is that any disturbance arising from the voltage transition should have decayed to an insignificant level within this period of time.

Preferably the delay is less than an initial sixty percent of the half cycle, or time interval between consecutive transitions.

A benefit of the delay being no more than 60 percent of the half cycle is that an adequate portion of the cycle remains to allow sufficient time for the addressable device to respond.

Preferably the delay is at least 50 micro-seconds. More preferably the delay is less than 150 micro-seconds.

A benefit of the delay being at least 50 micro-seconds is that transient disturbances arising from each of the voltage transitions has time to decay before the voltage level is measured. A benefit of the delay being less than 150 micro-seconds is that an operating frequency of the cyclic waveform may be sufficiently high to provide acceptable response times for a system having a number of such addressable devices.

Preferably the cyclic waveform comprises a plurality of substantially identical voltage pulses. More preferably the voltage pulses are substantially of a square wave waveform.

A benefit of a square wave cyclic waveform is that reliability of the communication is enhanced, and a high rate of transfer of information may be achieved.

Preferably the addressable device is arranged to detect consecutive low and high voltage levels.

A benefit of the addressable device being arranged to detect consecutive high and low voltage levels is that the addressable device may be arranged to provide a particular response to each of the high and low voltage levels.

Preferably the addressable device is arranged to provide a response or feedback signal only after the delay, and wherein the response or feedback signal is arranged to have a duration substantially of a whole half cycle of the cyclic waveform.

A benefit of the duration being substantially a whole half cycle is that the controller or programmer receiving the response or feedback signal has a similar time period in which to measure the level of the current response as the addressable device had to measure the voltage signal, and hence the controller or programmer may be arranged to confirm after a delay the presence of current response or feedback signal, the delay of the controller or programmer being timed from the cyclic voltage waveform being transmitted by the controller or programmer.

Preferably the addressable device is arranged to respond to the controller by drawing current.

A benefit of this is that the controller may be arranged to simultaneously send voltage signals and receive current signals.

According to a further aspect the present invention, there is provided an addressable device having a pair of electrical connections arranged for both connection to an electrical power supply for powering the device and for connection to a controller for bi-directional communication with the device, and a third electrical connection for receiving a switched input to or output from the device, the device being arranged to receive programming instructions by means of a voltage waveform across the pair of electrical connections and a synchronous voltage waveform at the third electrical connection.

A benefit of the programming instructions being provided by the combination of the synchronous voltage waveforms is that the device may not be accidentally re- programmed in use by applying a voltage waveform across only the pair of electrical connections, hence ensuring the reliability of the device.

Preferably the device being arranged to receive information by means of a cyclic waveform of the electrical power supply, each cycle comprising a sequence of two consecutive voltage transitions from a low voltage to a high voltage and or from a high voltage to a low voltage.

Preferably the cyclic waveform comprises at least a first low voltage level, a second intermediate voltage level, and a third high voltage level, the first low voltage level being sufficiently low to reset the device to a reset condition and sufficiently high to power the addressable device so that it is in a ready condition where it is capable of being responsive to a signal at the intermediate voltage level.

Preferably in an embodiment the addressable device is arranged to confirm by measuring the voltage level for a timed short time after the delay.

Preferably in a further embodiment the addressable device is arranged to confirm by measuring the voltage level from after the delay until a next voltage transition.

Preferably the addressable device is used in an alarm system.

A benefit of using the addressable device of the invention in an alarm system is that the reliability of the alarm system is enhanced, and the alarm system is enabled to operate over greater lengths of cable and with more devices than known alarm systems.

Specific embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:- Figure 1 is a block diagram of a system comprising a controller and a plurality of addressable devices according to the invention; Figure 2 is a block diagram of a programmer connected to one of the addressable devices shown in Figure 1; Figure 3 is a diagram showing an operating waveform of the addressable device of Figure 1; Figure 4 is a diagram showing a step input signal and a corresponding output signal for the system shown in Figure 1; Figure 5 is a diagram showing a noise signal of a similar magnitude to a valid step input signal and a corresponding output signal for the system shown in Figure 1; Figure 6 is a diagram of a waveform produced by the programmer shown in Figure 2 for unlocking the addressable device shown in Figure 1 to enable programming of the device; Figure 7 is a diagram of a waveform produced by the programmer shown in Figure 2 for initiating programming of the addressable device; Figure 8 is a diagram of a waveform produced by the programmer shown in Figure 2 for locking the addressable device to prevent programming of the device; Figure 9 is a diagrammatic representation of the programming operations with respect to time; Figure 10 is an oscilloscope trace showing the reprogramming of an addressable device by the programmer shown in Figure 2; Figure 11 is an oscilloscope trace showing the results of a first pattern noise injection test for a single addressable device; and Figure 12 is an oscilloscope trace showing the results of a first pattern noise injection test for a group of addressable devices; Figure 13 is an oscilloscope trace showing the results of a second pattern noise injection test for a single addressable device; Figure 14 is an oscilloscope trace showing the results of a second pattern noise injection test for a group of addressable devices; and Figure 15 is a block diagram of an addressable device according to the invention.

From Figure 1, a system 1 may be seen to comprise a controller 2 and a plurality of addressable devices 3 and 3'. The controller 2 is connected to a power supply 1P, and has an input means 1B, and connections 1C for a remote input means (not shown), such a remote input means could, for example, be a computer connected to the controller by means of an ethernet network connection, or by means of a modem over a telephone system. Alternatively, such a remote input means could be a remotely connected keyboard and display. The controller is also provided with a feedback means, such as LCD screen IF, and is arranged to provide an output IS, for example such as an audible alarm signal, a visual alarm signal, or by means of a network connection or modem a remote signal. The controller is provided with at least a pair of line connections 1L and 1M to the said plurality of addressable devices, each addressable device being connected in parallel with the other(s) to the line connections ILandiM.

Each addressable device 3, 3' has three connections, a pair of terminals 1J and 1K for connection to the line connections 1L and IM to power the addressable device, and a switched input connection 1Q, the switched input connection being connected through a switch 1W to line connection 1 L. The addressable devices each having at least two states, a first state when the switch 1W is open, and a second state when the switch 1W is closed. In an alarm system, one state may be arranged to correspond to an alarm state.

The controller 2 is arranged so that the state of each of the addressable devices 3 & 3' may be determined by means of the line connections 1 L and 1 M. The controller is arranged to determine the state of each addressable device periodically.

To avoid false indications of the presence or absence of a particular addressable device or a change of state of a particular addressable device, the controller 2 is arranged to confirm a presence or a change of state of a particular switch 1W, by storing information about the previous state of each of the addressable devices over a number of previous determinations. When the change of state is detected for a specified number of sequential detrminations, then the controller is arranged to operate to produce an output iS corresponding to the particular change of state detected.

Where the controller 2 is used within an alarm system, to ensure that an alarm state is detected and confirmed within an acceptably short period of time, the controller must be arranged to determine the state of each addressable device suitable frequently.

European Standard EN5O 131-1: 1997 "Alarm Systems - Intrusion Systems. General Requirements." sets a requirement that a change of state will be detected within 400mS.

Hence, for example, in a system where up to 254 addressable devices 3 are connected in parallel across line connections 1L and 1M to a controller 2, to enable the controller to confirm or verify the change of state by the controller must be arranged to operate sufficiently fast so that all 254 devices are monitored for the required said specified number of sequential determinations within this 400mS period. It has been found in practice in such a system that a suitable line frequency for the controller to operate at is preferably 2.5kHz. Hence, a time of 200 micro- seconds is allowed for the determination of the presence or the state of each addressable device.

Figure 2 shows a programmer 21 for programming an addressable device 3. In a preferred embodiment, each addressable device has its address fixed at the time of manufacture. The address is preferably fixed at address number 255. The addressable devices are arranged to permit the address to be programmed by the installer at the time of system installation. A benefit of this is that an installer need only stock one type of addressable device for any size of installation. The programmer 21 is arranged with three terminals to connect to the switched input terminal 1Q, the first line terminal 1 J, and the second line terminal 1K. The programmer is provided with an input means 2B such as a keypad, and an output means 2F, such as an LED or LCD display, and may be powered from a power supply I P' or may be battery powered. To program an addressable device, the programmer is arranged to communicate simultaneously on all three connections to the addressable device. This reduces the risk that an addressable device may be accidentally programmed while fitted in an installation. Such accidental programming would have potentially serious consequences, particularly where the addressable device was being used in an alarm system, or other system providing personnel protection or safety. The programming of the addressable device is described with reference to Figures 6 to 10 below.

Devices may be re-programmed as required at any time with any address from 1 to 255 giving increased flexibility for an installer during installation or subsequently.

From Figure 3, an addressing protocol for use with the addressable device 3 may be seen shown graphically. The addressing protocol is used to enable communication between the controller 2 and an addressable device 3. In a preferred embodiment, each of the addressable devices will permit an 8 bit address giving a theoretical maximum of 255 addresses, however in the preferred embodiment address 255 is reserved for testing as described below.

The control panel 2 outputs a waveform Vw to all addressable devices 3, 3' connected on a particular 2-wire bus. The waveform Vw comprises 3 voltage levels, a reset voltage VR that is above VB MIN and below VRST, a high signal voltage VH, and a low signal VL as shown in Figure 3 below. All addressable devices use the voltage level between VBMIN and VRST to reset their internal address counter. The first VL phase (VLI) prepares addressable devices for the clock waveform. Voltage VB MIN is a minimum low voltage that is sufficient to maintain the addressable devices in a powered state.

The clock waveform consists of alternate VH and VL phases for each of up to 254 devices, after which the control panel outputs a voltage level between VBMIN and VRST - 10 - to reset all devices. The clock waveform may be terminated early after say 30 addresses.

The first VH phase is a "diagnostic" phase of address #1. An addressable device 3 programmed with address #1 will respond to the diagnostic phase by switching on a constant current sink of nominally l5rnA. This indicates to the control panel 2 that a device at address #1 is connected to the bus. The next VL phase is the "signal" phase of address #1. If the switched input of the addressed device is closed (the switched input 1Q being connected to its line connection 1 L terminal by an external switch) the addressable device will leave its constant current sink switched on until the next rising edge of the clock, otherwise it must switch the constant current sink off on the falling edge. On the next VH phase (now for address #2) the device #1 must ensure that its current sink is switched off.

Figure 3 shows the current response CR of an addressable device with address #2. The device responds to the diagnostic phase of the waveform by drawing a current D, and if the switched input 1Q is connected to its line connection 1L terminal by an external switch, the addressable device #2 continues to draw the same current Ts during the signal phase, shown by line 3S, or if the switched input is not connected to its line connection terminal 1 L, the addressable device will revert to the low current level I as shown by line 3P.

The period tF is used by the addressable device to filter (debounce) the transitions or changes in the voltage waveform Vw produced by the controller 2 to minimise the risk that electrical noise may cause a false clocking. Noise rejection is described below.

From Figure 3, each cycle of the voltage waveform Vw comprises a first voltage transition TR1 from a low voltage, the low bus voltage VL, to a high voltage, the high bus voltage VH, followed by a period at a first substantially steady state voltage region SS1 at the high voltage V11, and a second voltage transition from the high voltage VH - 11 - to the low bus voltage VL, followed by a period at a substantially steady state voltage region SS2 at the low bus voltage VL.

The subsequent cycle hence, comprises a first voltage transition TR1', a first steady state region SS1', a second voltage transition TR2' and a second steady state region SS2'.

Each addressable device connected to a system is arranged so that after each voltage transition TR1, TR2, TR1', TR2', a delay of the debounce or filter period tF is allowed to elapse before the addressable device confirms the presence of the VH signal of steady state region SS1, or the presence of the VL signal of the steady state region SS2.

Hence, the current response CR is lags the voltage signal Vw by a time period of approximately the delay period tF.

In an alternative embodiment not shown in the figures, the system may be arranged so that each cycle comprises a first voltage transition from a high voltage to a low voltage and a second voltage transition from the low voltage to the high voltage.

These Figures show the duration of a current response being substantially a whole half cycle. Hence the controller receiving the current response signal has a similar time period to the time period between one voltage transition and a subsequent voltage transition, in which to measure the level of the current response, as the addressable device had to measure the voltage signal. Hence the controller is also preferably arranged to confirm only after a delay the presence of the current response signal.

Since the controller is generating the cyclic voltage waveform, the controller is preferably arranged to use its own internal timing of the voltage waveform generator to time the delay for detecting the current response.

- 12 - For the preferred embodiment it has been found that suitable bus voltage levels and suitable time periods which enable the optimum use of the addressable device, are given in the Table 1 below: Symbol Parameter Mm Typical Max Units VR Reset Voltage 3.3 3.4 3.5 V VL Address Low voltage (Typical 2%) 6.37 6.5 6.63 V VH Address High Voltage (Typical 2%) 10. 78 11.0 11.22 V tRST Reset period I ms tLI First VL period, that is the "Start-up time" 200 p.s for the addressable device VBUS Bus voltage applied to L+ and L- terminals. 2.0 15 V The addressable device is expected to operate correctly over this voltage range. ________ _______ _______ VRST Reset threshold. A voltage below this 3.5 4.0 4.5 V threshold will reset the addressable device address counter VCLH Clock Low-High threshold. 7.6 8.0 8.4 V VCHL Clock High-Low threshold 6.8 7.0 7. 35 V IQII Quiescent current at VH 150 p.A IQL Quiescent current at VL 150 p.A IR Quiescent Current at VR 150 p.A _______ Signal Current 12 15 18 mA ________ Diagnostic Current 12 15 18 mA tH VHperiod 200 ______ _____ p.s tL VLperiod 200 p.s tF Filter period 80 100 120 p.s Table 1 Bus Parameter Definitions and Suitable Values for Preferred Embodiment - 13 - It is important that the communication between a controller and the addressable devices connected to it is reliable. Since systems may be installed in electrically noisy environments, such communication is liable to be degraded by electromagnetic interference and conducted electrical noise. In order to significantly improve the reliability of the communication, the addressable devices are arranged to ignore or filter portions of the signal from the controller. In order to do this, the addressable device is arranged filter (debounce) all voltage level transitions on the communication/power line (bus) so that a noise spike does not result in a false address clock or an address reset. The filter period (tF) for the preferred embodiment is specified in Table 1.

In Figures 4 and 5, an enlarged portion of the Vw signal shown in Figure 3, is shown on the top waveform, and on the bottom waveform is the corresponding current response CR from the addressable device. The current response CR is the means by which the addressable device communicates its Output Decision to the controller. The middle line depicts graphically the relative timescale of the filtering period tF.

From Figure 4, a valid step input signal VBUS from the controller is shown on the top trace. Since the addressable device is arranged to ignore this signal for the duration of the Debounce Period tF MAX, a corresponding output signal from the addressable device does not occur until after the end of the Debounce Period tF MAX at which time the addressable device recognises the high voltage VBUS signal and produces a step output signal as shown by the bottom waveform.

Figure 5 shows on the top waveform, a input signal VBUS comprising noise, of a similar magnitude to the step signal of Figure 4 from the controller. The addressable device being arranged to ignore this signal for the duration of the Debounce Period tF MAX, hence a corresponding output signal from the addressable device does not occur until after the end of the Debounce Period tF MAX at which time the addressable - 14 - device recognises that the voltage VBUS signal is not at a high level and hence no output signal is produced, as shown by the bottom waveform being a straight line.

Further software filtering (debounce) between full consecutive communication line (bus) scans by the controller may also be incorporated in order to increase immunity of the system to noise and in the case of an alarm system, reduce false alarms.

In Figures 11, 12, 13 and 14 which are oscilloscope traces showing the results of noise injection tests, for each figure, the top trace shows a signal Vw from a controller 2 onto the communication line 1L/1M, where large noise spikes SN have been injected into the signal, and the lower trace shows the resulting current response CR from the addressable device 3 which is largely unaffected by the noise signal.

From Figure 11 which shows the results of a first pattern noise injection test, where noise is injected into the controller signal (shown on the top trace) during a VH portion of the signal 50 micro-seconds after a voltage transition of the rising edge of VH so as to bring the voltage instantaneously down to the level of VL for a period of about 10 micro-seconds, and noise is also injected during a VL portion of the signal 50 micro- seconds after a voltage transition of the falling edge of VH so as to bring the voltage instantaneously down to the level of VR for a period of about 10 micro-seconds. This noise, although having caused a disturbance to the current response, has not prevented the addressable device from responding with an appropriate current response for an addressable device Dl.

The axes and time periods labelled in Figure 11, 12, 13 and 14 correspond to the similarly labelled features shown in Figure 3. Note, in Figures 12 and 14 only a couple of instances of the noise SN are labelled.

- 15 - Figure 12 shows a similar first pattern noise injection test trace to that of Figure 11, showing the response of addressable devices Dl to D8. Although the noise causes a disturbance to the response of an addressable device, it has not prevented each of the addressable devices from responding appropriately, since each of the addressable devices has discarded the noise as it fell within the tF filtering periods.

From Figure 12 it may be seen that addressable device Dl responds that it is present on the system, and that its switch is open, addressable device D2 responds that it is present on the system, and that its switch is closed, addressable device D3 responds that it is present on the system, and that its switch is open, and addressable device D4 responds that it is present on the system, and that its switch is closed. This Figure shows that no other devices are responding that they are present on the system with addresses that correspond to D5, D6, D7 or D8.

Figure 13 shows a second pattern noise injection test, where a relatively long, and hence high energy noise signal with a duration of tN does not prevent a correct response CR from an addressable device. The value of tN in Figure 13 is 70 micro- seconds.

Figure 14 shows a combination of both negative and positive noise signals injected on the control signal, and the response of addressable devices Dl to D4. The combination of both noise signals has no detrimental effect on communication with the addressable devices.

Such levels of noise as shown in Figures 11 to 14, if present on the signals from the controller would prevent known devices from responding appropriately, and hence known systems would fail to operate.

- 16 - Although induced noise may occur anywhere through the cycle, the effect of such noise which is not identified in particular in any of the above figures, but is evidenced by the irregularities in the voltage and current waveforms Vw and CR, is exacerbated by the transition or step change in voltage from VL to VH or vice versa. Hence, by filtering out the effects of this on the initial portion of each cycle, significant improvements in the reliability of the communication between the controller 2 and the addressable devices 3, 3' are achieved in practice.

A benefit of improving the tolerance to noise is that lower signal levels may be safely used.

An important requirement for larger systems, where up to 254 addressable devices may now be connected, is that line lengths may be increased from, say the lOOm of known systems, to in excess of 400m for an embodiment of the invention. Line lengths are limited by the voltage drop arising from resistive losses along the line length preventing effective powering and communication with devices attached across the line.

In the preferred embodiment of the invention arranged as shown in Figure 1, the addressable devices are arranged so that when they are connected to the system across the line connections 1L and 1M, they draw a very low quiescent current IQH, IQL and Preferably such a low quiescent current is less than 500 micro-amps, and more preferably the low quiescent current is less than 250 micro-amps.

In practice it has been found possible to operate with a maximum quiescent current as low as 150 micro-amps at a maximum bus voltage of 15 volts. In this embodiment, it - 17 - has been found that the quiescent current R at a VR of 3 volts is from 60 to 80 micro- amps, and the quiescent currentIQL at a VL of 6.5 volts is from 80 to 110 micro-amps, and the quiescent current lio at a VH of 11 volts is from 100 to 135 micro-amps.

Known devices require a relatively high quiescent current of approximately 2.5 milli- amps.

A low quiescent current enables a low voltage drop along the length of the power line, and ensures that there is a significant and discernable difference between the quiescent current drawn by a large number of addressable devices, which for example when 254 devices are connected, the combined quiescent current in the example mentioned above will be less than 40 milli-amps, and the signal current 1s or the diagnostic current ID drawn by a device to provide feedback to the controller. In the preferred embodiment, a suitable maximum value for the signal current Ts or the diagnostic current D has been found in practice to be 18 milli- amps.

Figures 6, 7, and 8 show the synchronous waveform produced by a programmer to program an addressable device as shown in Figure 2. The synchronous waveform comprises a clock waveform VBUS which is applied to the addressable device on the line terminals 1J and 1K, and a logic waveform SW that is synchronously applied to switch terminal 1Q. The addressable device is arranged to provide feedback to the programmer by drawing a high current D between terminals 1J and 1K as shown in the bottom trace in each of these Figures.

Figure 6 is a diagram of a waveform produced by the programmer shown in Figure 2 for unlocking the addressable device shown in Figure 1 to enable programming of the device.

- 18 - Figure 7 is a diagram of a waveform produced by the programmer shown in Figure 2 for initiating programming of the addressable device.

Figure 8 is a diagram of a waveform produced by the programmer shown in Figure 2 for locking the addressable device to prevent programming of the device.

Figure 9 is a diagrammatic representation of the programming operations with respect to time.

It is not possible to program an addressable device without progressing through the steps shown by Figures 6, 7 and 8 as shown in Figure 9. Hence, accidental re-programming of an addressable device arising from noise or other interference with the system is in practice, not possible while the addressable device is installed in a system. Hence, the reliability and security of such a system can not be compromised by the re-programming of an addressable device.

Figure 10 is an oscilloscope trace showing the reprogramming of an addressable device by the programmer shown in Figure 2. The addressable device 3 when first connected to the programmer 21 has a default address, which in the preferred embodiment is address number 255.

Address number 255 is preferably not used for a programmed addressable device correctly attached to a system. A benefit of using only a default address of 255 for all new addressable devices, is that it is possible to verify that all addressable devices in a system have been correctly programmed by checking that no device is present that responds to an address of number 255.

- 19 - From Figure 10, three separate traces are shown on the same horizontal axis. The top trace shows the voltage output SW from the programmer 21 (shown in Figure 2) applied to the switch contact l of the addressable device 3, the middle trace shows the voltage output VIJS from the programmer applied to the line terminals 1J and 1K, and the lower trace shows the current response CR from the addressable device to provide feedback to the programmer.

The programmer starts a programming sequence at 1 OA by unlocking the addressable device to enable the reprogramming of its address. The unlocking sequence 1OA comprises starting from a reset voltage VR followed by four clock pulses of voltage VH applied to the line terminals 1 J and 1K with two synchronised pulses P1 applied to the switch terminal IQ which are shown on the top trace. A check pulse VCHK from the programmer evokes a response Cl from the addressable device to confirm that it is unlocked and has entered a programmable state.

The programmer at lOB programs the addressable device with a new address, in this case the address is number 15. The sequence starts at 1OF with four clock cycles starting from a reset voltage VR and a single pulse P2 applied to terminal l. The addressable device confirms that it is expecting new programming instructions by drawing the current confirmation pulse C2. The sequence at 1OF, shows a further eight clock cycles at V11, which sets the address of the device to 15, followed by a delay at a low VBUS voltage of VL, which is followed by a VH signal pulse to confirm the device has been reprogrammed. The device confirms it has been programmed with a new address and has subsequently locked itself to prevent accidental further programming by drawing current pulse C3.

The programmer at 1 OC checks that the addressable device is locked by sending VBUS clock pulses on the line terminals and a synchronous series of pulses P4 on the switch terminal 1c. The final V11 pulse is to verify that the addressable device is - 20 - correctly locked. That the device is locked is confirmed by the lack of a current response from the addressable device.

The programmer at 1OD, then confirms that the addressable device does indeed respond correctly at its new address, and at no other. Hence, the programmer sends a stream of 255 clock pulses (only first few shown in Figure 10) to which the addressable device correctly responds at the fifteenth pulse by drawing a current confirmation pulse C4. Provided that no other confirmation pulse is received, when the stream of 255 clock pulses is complete, the programmer indicates to a user that the addressable device has been correctly re-programmed with the new address number 15.

From Figure 15, a block diagram of an addressable device 150 according to the invention. The addressable device 150 has two line connections 15J and 15K for connecting to an external power supply for powering the addressable device. The line connections are connected through a reverse polarity protection means 1 5P to a voltage detector 1 5D which is arranged to detect a transition of the external power supply from a low voltage to a high voltage and or from a high voltage to a low voltage, and to provide a timing signal 1 5A when such a transition is detected. Delay timer 1ST is arranged to start timing when a timing signal iSA is received, and is arranged to provide an output signal I SB to a logic device 1 5L after a time delay. The voltage detector 1 SD is also arranged to measure the voltage across line connections 1 5J and 15K and provide an output signal 1 SE corresponding to the voltage measured.

When the signal 15B is received by the logic device, indicating that the time delay has elapsed, the logic device is arranged to determine the voltage level corresponding to the signal 1 SE. The switched input 1 SQ is connected to a voltage comparator I SF which provides an output ISC if the switched input 15Q is connected by an external switch, such as switch 1W shown in Figure 1, to a line connection 1 L. The logic device 1SL is also provided with a non-volatile memory that is arranged to hold an - 21 address number so as to provide a unique identifier for each addressable device connected to a system such as shown and described with reference to Figure 1.

In normal operation the voltage level corresponding to the signal 15E will be either a low bus address voltage VL or a high bus address voltage VH. A consecutive pair of VH and VL voltages indicate to the logic device that a complete cycle of a signal waveform has been received from a controller powering the line connections. The addressable device is arranged to count such cycles, and to compare the number of cycles with its own address number. When the number of cycles received from the controller matches the address number of the addressable device, the logic device is arranged to respond by operating switch 15S so that a diagnostic current D and / or a signal current 1s is drawn through current limiter 1 5R from the controller through line connections l5J and 15K.

The response provided by the addressable device depends on the mode in which it is operating as described above with reference to Figure 3. In a diagnostic mode, the addressable device is arranged to operate the switch 15S so as to signal its presence to the controller. In an operational mode, the addressable device is arranged to close the switch 15S, only if an output signal 15C is present.

It should be noted that an optimum value for the time delay is a compromise between maximising the initial portion of the voltage signal from the controller that is discarded or disregarded by the addressable device, while still allowing sufficient time before a subsequent voltage transition for the addressable device to both determine that a valid VL or VH signal is present and to respond by drawing a diagnostic current ID or a signal current Is as appropriate. Hence the optimum time delay will depend on the operating frequency of the controller when sending the voltage signal waveform.

In a preferred embodiment, for which values have been given in Table 1, it may be seen that at an operating frequency of 2.5 kHz for the cyclic waveform, the values of - 22 - the delay are given in the table as between a minimum of 80 micro-seconds and a maximum of 120 micro-seconds.

Where a longer delay of say, 200 micro-seconds is desirable, a lower operating frequency is required, for example 2 kHz maximum, or more preferably to provide a more reliable operation with this delay, a frequency of 1.5 kHz for the cycle waveform is desirable.

Where a yet longer delay of say, 250 micro-seconds is desirable, a still lower operating frequency is required, for example 1.6 kHz maximum, and more preferably for reliable operation a frequency of 1 kHz for the cycle waveform.

The addressable device 150 may be arranged so that the time delay is set at manufacture of the device.

In a further embodiment the addressable device may be arranged so that the time delay is set or adjusted using a programmer as shown in Figure 2. The time delay in the further embodiment is preferably preset to a default value at manufacture, and more preferably only adjustable within limits from this preset value.

Claims

- 23 - CLAIMS

1. An addressable device having a pair of electrical connections arranged for both connection to an electrical power supply for powering the device arid for connection to a controller for bi-directional communication with the device, and a third electrical connection for receiving a switched input to or output from the device, the device being arranged to receive programming instructions by means of a voltage waveform applied across the pair of electrical connections together with a synchronous voltage waveform applied at the third electrical connection.

2. An addressable device as claimed in claim 1, wherein the device is arranged to receive information by means of a cyclic waveform of the electrical power supply, each cycle comprising a sequence of two consecutive voltage transitions from a low voltage to a high voltage and from the high voltage to the low voltage, or from a high voltage to a low voltage and from the low voltage to the high voltage.

3. An addressable device as claimed in Claim 1 or 2, wherein the addressable device further comprises means to detect the transitions, means to detect the low or the high voltage levels between transitions, the addressable device being arranged to confirm after a delay the presence of the high or low voltage levels.

4. An addressable device as claimed in any of the preceding claims wherein the addressable device is arranged to be powered by drawing a first low level of current from the pair of electrical connections and a second high level of current to provide a - 24 - feedback to a confirm receipt and result of the programming instructions.

5. An addressable device as claimed in claim 4 when dependant on claim 3, wherein the addressable device is arranged to provide the feedback signal only after the delay, and wherein the feedback signal is arranged to have a duration substantially of a whole half cycle of the cyclic waveform.

6. A system comprising an addressable device as claimed in any one of the preceding claims and a programmer arranged to provide said programming instructions and to receive said feedback, the programmer further comprising a means for receiving a data input, and a means for producing feedback to a user.

7. An addressable device as claimed in any of the preceding claims wherein the cyclic waveform comprises at least a first low voltage level, a second intermediate voltage level, and a third high voltage level, the first low voltage level being sufficiently low to reset the device to a reset condition and sufficiently high to power the addressable device so that it is in a ready condition where it is capable of being responsive to a signal comprising a change in voltage from the first low voltage level to the second intermediate voltage level.

8. An addressable device as claimed any of the preceding claims when dependant on Claim 3, wherein the addressable device is arranged to confirm by measuring the voltage level for a timed short time after the delay.

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9. An addressable device as claimed in any of the claims 3 or 4 to 7 when dependant on Claim 3, wherein the addressable device is arranged to confirm by measuring the voltage level from after the delay until a next voltage transition.

10. An addressable device having a pair of electrical connections arranged for both connection to an electrical power supply for powering the device and for connection to a controller for bi-directional communication with the device, the device being arranged to receive information by means of a cyclic waveform of the electrical power supply, each cycle comprising a sequence of two consecutive voltage transitions from a low voltage to a high voltage and from the high voltage to the low voltage, or from a high voltage to a low voltage and from the low voltage to the high voltage, the addressable device having means to detect the transitions, means to detect the low or the high voltage levels between transitions, the device being arranged to confirm after a delay the presence of the high or low voltage levels.

11. An addressable device as claimed in claim 10, wherein the delay is at least an initial forty percent of a time interval between consecutive transitions.

12. An addressable device as claimed in claim 10, wherein the delay is at least 50 micro-seconds.

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13. An addressable device as claimed in claim 10 or 11, wherein the delay is less than sixty percent of the time interval.

14. An addressable device as claimed in claim 10 or 12, wherein the delay is less than 150 micro-seconds.

An addressable device as claimed in any of the claims 10 to 14, wherein the addressable device is arranged to detect consecutive low and high voltage levels.

16. An addressable device as claimed in any of the claims 10 to 15, wherein the electrical power supply is substantially a direct current voltage.

17. An addressable device as claimed in any of the claims 10 to 16, wherein the cyclic waveform comprises a plurality of substantially identical voltage pulses.

18. An addressable device as claimed in any of the claims 10 to 17, wherein the cyclic waveform comprises a substantially square wave waveform.

19. A system comprising an addressable device as claimed in any of the claims 10 to 18 and a controller arranged to interrogate the device and to receive information from the device.

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20. A system as claimed in claim 19 wherein the addressable device is arranged to be powered by the controller by drawing a low current, the low current being less than 250 micro amps.

21. A system as claimed in either of claims 19 or 20, wherein the addressable device is arranged to respond to the controller by drawing a high current, the high current being more than 10 milli-amps.

22. An addressable device as claimed in claim 21, wherein the addressable device is arranged to provide the response high current signal only after the delay, and wherein the response signal is arranged to have a duration substantially of a whole half cycle of the cyclic waveform.

23. An addressable device as claimed in any of the claims 10 to 22 wherein the cyclic waveform comprises at least a first low voltage level, a second intermediate voltage level, and a third high voltage level, the first low voltage level being sufficiently low to reset the device to a reset condition and sufficiently high to power the addressable device so that it is in a ready condition where it is capable of being responsive to a signal comprising a change in voltage from the first low voltage level to the second intermediate voltage level.

24. An addressable device as claimed any of the preceding claims when dependant on Claim 10, wherein the addressable device is arranged to confirm by measuring the voltage level for a timed short time after the delay.

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25. An addressable device as claimed in any of claims 10 to 23 when dependant on Claim 10, wherein the addressable device is arranged to confirm by measuring the voltage level from after the delay until a next voltage transition.

26. An alarm system comprising an addressable device as claimed in any of the preceding claims.

27. An addressable device substantially as described herein with reference to the Figures 1,3 to 5, and 11 to 15.

28. An addressable device substantially as described with reference to Figures 2 and Figuresóto 10.