JP2002184192A - Non-volatile semiconductor memory and its rewriting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the erasure characteristic of a memory cell of a rewritable non-volatile semiconductor memory in which data erasure, data write or the like is possible. SOLUTION: In order to erase data of a memory cell array 103 in which a plurality of memory cells where data can be written and erased electrically by a floating gate are arranged, there are provided a temperature detecting circuit 110 for detecting the temperature of a chip, a voltage conversion circuit 104 for varying erasure voltage supplied to the source of the memory cell, and a voltage conversion control circuit 111 for controlling the voltage conversion circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data rewriting method in an electrically rewritable nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art Flash EEPROMs (Electrically
Erasable and Programmable Read Only Memor
y) means that even if the power is turned off, the data in the memory cells does not disappear,
Also, flash memories that can be erased in a batch are used for large-capacity memories such as digital cameras and for storing numbers of mobile phones, and the market is expanding.

FIG. 14 shows a sectional structure of an example of a memory cell used in a flash EEPROM. 13
07 is a P-type semiconductor substrate, 1305 and 1306 are drain and source regions, 1304 is a tunnel oxide film, 1
303 is a floating gate, 1302 is an insulating film, and 1301 is a control gate.

Data writing is performed by a control gate 1301.
10 volts, 5 volts to the drain region 1305, and 0 volts to the source region 1306, respectively. As a result, the source region 1306 moves to the drain region 1305.
Some of the electrons traveling toward are heated by the high electric field near the drain region 1305 and injected into the floating gate 1303.

On the other hand, data is erased by the control gate 130.
0 volts is applied to 1, the drain region 1305 is made floating, and 12 volts is applied to the source region 1306. Thus, a relatively high electric field is applied between the floating gate 1303 and the source region 1306 via the thin tunnel oxide film 1304. Electrons in the floating gate 1303 are emitted to the source region 1306 by Fowler-Nordheim tunnel effect.

The data reading is performed by the control gate 1
5 volts at 301, 1 volt at drain region 1305,
0 volt is applied to each of the source regions 1306. Thus, depending on the presence or absence of electrons in the floating gate 1303,
Data 0 or data 1 is obtained.

FIG. 13 shows a conventional flash EEPROM using this memory cell. Memory cell array 120
Reference numeral 3 denotes an array of memory cells each having a floating gate and a control gate each having the configuration shown in FIG. The memory cell arrays 1203 are arranged in a matrix of m rows and n columns. The sources of these memory cell arrays 1203 are commonly connected. Also, the memory cell array 1
The control gate 203 is connected for each row. The drains of the memory cell array 1203 are connected for each column. The common source of the memory cell array 1203 is
4 to supply a high voltage required for erasing. The row line WL of the memory cell array 1203 is connected to the X decoder 120
2 is connected. Column line BL of memory cell array 1203
Is a sense amplifier circuit 1 including a load transistor for reading data via a Y gate transistor 1206.
207. This sense amplifier circuit 1207
Is an input / output circuit 1 for inputting / outputting data to / from external terminals.
208, a control circuit 1201 for controlling the operation of each unit
Connected to. The control gate of Y gate transistor 1206 is connected to Y decoder 1205. Control circuit 1
201 denotes an X decoder 1202, a Y decoder 1205,
Connected to booster circuit 1204.

[0008]

In a conventional erasing method for a semiconductor memory device, 0 volt is applied to a control gate of a memory cell, a drain region is floated, and a constant erasing voltage and a constant pulse width are applied to a source region. Can be

When erasing data, 1 is added to the source area.
Although a voltage of 2 volts is applied, when the temperature of the device rises, due to the temperature characteristics of peripheral circuits, 1
Voltages lower than 2 volts are applied. As a result, the intensity of the electric field applied to the tunnel oxide film of the memory cell decreases, and the erasing speed decreases. At this time, if the time is delayed so as to exceed the standard of the erasing time, it becomes defective. For this reason,
When the temperature dependence is large, the temperature range in which the erasing operation can be guaranteed has to be narrowed.

Further, a problem at the time of erasing is the occurrence of over-erasing. When erasing data, a high voltage of 12 volts is applied to the source region.
A large potential difference occurs between the source region and the substrate. Therefore, band-to-band tunneling (ba
nd to band tunneling) and electron avalanche breakdown occurs. As a result, the region is accelerated by an electric field in the deep depletion layer region formed in the source junction region, becomes a high energy hot hole, is injected into the tunnel oxide film, and a part of the hole is captured by the oxide film. The holes captured in this way have the effect of greatly increasing the erase speed during erase. As a result, the erase threshold voltage of a cell in which holes are captured in the tunnel oxide film is lower than the erase threshold voltage of another cell in which holes are not captured in the tunnel oxide film.

Therefore, a case may occur where the erase threshold voltage of the cell has a negative value. In such a case, a leakage current always flows from these cells, resulting in an error when reading data. When the temperature of the device becomes low, the temperature 12
A voltage higher than volts is applied. As a result, the electric field intensity applied to the tunnel oxide film of the memory cell increases, and the erasing speed increases. For this reason, the Vt of the memory cell is greatly reduced by one pulse, and the memory cell is likely to fall into an overerased state.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving the rewriting characteristics of writing and erasing of a memory cell and suppressing an over-erased state, and a rewriting method therefor. With the goal.

[0013]

According to the present invention, there is provided a nonvolatile semiconductor memory device, comprising: a temperature detecting circuit for detecting a temperature of a memory cell array; and a detecting circuit for detecting a temperature of the memory cell array when rewriting a memory cell constituting the memory cell array. A voltage conversion control circuit for controlling a state of a voltage applied to the source region so that an electric field between the source region and the floating gate of the memory cell is constant.

According to the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device, comprising the steps of: providing a semiconductor substrate of a first conductivity type; a source region and a drain region of a second conductivity type formed on one main surface of the semiconductor substrate; At the time of rewriting a nonvolatile semiconductor memory device having a floating gate formed through a first insulating film and a memory cell formed of a control gate formed on the floating gate through a second insulating film, Rewriting is performed by controlling a voltage application state according to a temperature of the nonvolatile semiconductor memory device so that an electric field between a source region and the floating gate becomes constant.

According to this configuration, the rewriting characteristics of writing and erasing of the memory cell can be improved, and the overerased state can be suppressed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to claim 1 of the present invention has a temperature detecting circuit for detecting the temperature of a memory cell array, and the temperature detecting circuit detecting the temperature of a memory cell constituting the memory cell array when rewriting. A voltage conversion control circuit for controlling a state of a voltage applied to the source region so that an electric field between the source region and the floating gate of the memory cell becomes constant according to a temperature is provided.

According to a second aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device, comprising: a first conductivity type semiconductor substrate; a second conductivity type source region and a drain region formed on one main surface of the semiconductor substrate; Nonvolatile semiconductor memory device having a memory cell composed of a floating gate formed on a semiconductor substrate via a first insulating film and a control gate formed on the floating gate via a second insulating film When rewriting, the rewriting is executed by controlling the voltage application state according to the temperature of the nonvolatile semiconductor memory device so that the electric field between the source region and the floating gate becomes constant.

According to a third aspect of the present invention, in the method for rewriting a nonvolatile semiconductor memory device according to the second aspect, the pulse width of the voltage applied to the gate region is controlled according to the temperature of the nonvolatile semiconductor memory device. It is characterized by.

According to a fourth aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device according to the second aspect, wherein a voltage applied to the gate region is controlled according to a temperature of the nonvolatile semiconductor memory device. I do.

According to a fifth aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device according to the second aspect, wherein the second conductive type is formed on one main surface of the semiconductor substrate on which the memory cell is formed. The temperature of the non-volatile semiconductor storage device is determined by the amount of current flowing between the drain region and the source region in a transistor including a source region and a drain region, and a control gate formed on the semiconductor substrate via a first insulating film. It is characterized by detecting.

According to a sixth aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device according to any one of the second to fourth aspects, wherein a temperature is generated at both ends of the resistance component by flowing a current from the constant current source to the resistance component. The temperature of the nonvolatile semiconductor memory device is detected by comparing a voltage having dependency and a reference voltage whose voltage value does not fluctuate with temperature by a comparator.

According to a second aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device according to any one of the second to fourth aspects, wherein a current is supplied from a constant current source to a diode-connected type reference voltage generating circuit so that the resistance component is reduced. The temperature of the nonvolatile semiconductor memory device is detected by comparing a voltage having a temperature dependency generated at both ends of the nonvolatile semiconductor memory device and a reference voltage whose voltage value does not fluctuate with temperature by a comparator.

According to an eighth aspect of the present invention, there is provided a method for rewriting a nonvolatile semiconductor memory device according to the second to fourth aspects, wherein odd-numbered inverters are connected in a ring shape, and the oscillation frequency thereof is temperature-dependent. A signal is supplied from the oscillator to the capacitance component to store a temperature-dependent electric charge. Detecting the temperature of the nonvolatile semiconductor memory device.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
2 will be described. (Embodiment 1) FIGS. 1 and 2 show (Embodiment 1) of the present invention.

The flash EEPROM of FIG. 1 includes a voltage conversion circuit 104 for changing a voltage value boosted by a booster circuit 105, a temperature detection circuit 110 for detecting the temperature of a device, and a voltage conversion control for controlling the voltage conversion circuit 104. The circuit 111 is employed.

101, 102, 103, 106, 10
The other circuits 7, 108 and 109 are respectively shown in FIG.
1201, 1202, 1203, 1205, 120
6, 1207, 1208.

In the flash EEPROM of FIG.
In the memory cell array 103, memory cells each having a floating gate and a control gate having the configuration shown in FIG. 14 are arranged. The memory cell array 103 is arranged in a matrix of m rows and n columns. The sources of these memory cell arrays 103 are commonly connected. The control gates of the memory cell array 103 are connected for each row. The drain of the memory cell array 103 is connected for each column. A common source of the memory cell array 103 is connected to a booster circuit 105 via a voltage conversion circuit 104, and is supplied with a high voltage required for erasing. Memory cell array 10
The third row line WL is connected to the X decoder 102. A column line BL of the memory cell array 103 is connected via a Y gate transistor 107 to a sense amplifier circuit 108 including a load transistor for reading data. The sense amplifier circuit 108 is connected to an input / output circuit 109 for inputting / outputting data to / from external terminals and a control circuit 101 for controlling the operation of each unit. The temperature detection circuit 110 that detects the temperature of the device is connected to a voltage conversion control circuit 111 that controls the voltage conversion circuit 104. The voltage conversion control circuit 111 is connected to the voltage conversion circuit 104. Y
The control gate of gate transistor 107 is connected to Y decoder 106. The control circuit 101 includes the X decoder 1
02, the Y decoder 106, the booster circuit 105, and the temperature detection circuit 110.

In response to the address input from control circuit 101, X decoder 102 selects word line WL of memory cell array 103, and Y decoder 106 activates Y gate transistor 107 connected to bit line BL of memory cell array 103. select. As a result, a predetermined voltage is applied to the word line WL and the bit line B for each selected address.
L.

At the time of erasing, the boosting circuit 105 is a circuit for supplying a high voltage necessary for erasing.
Is converted into several voltage values by the voltage conversion circuit 104 and applied to the common source line of the memory cell array 103. The voltage conversion circuit 104 is controlled by the voltage conversion control circuit 111, and the voltage conversion control circuit 111 is controlled by the control circuit 101.

At the time of verification, when a predetermined voltage is applied to the selected address of the memory cell array 103 to the word line WL and the bit line BL, the bit line BL
Is input to the sense amplifier circuit 108 via the Y gate transistor 107. The sense amplifier circuit 108 performs pass / fail judgment, and the control circuit 10
Output to 1.

The present invention differs from the conventional erase operation in that the device temperature is detected before the erase operation. Before performing the erase operation, the control circuit 101 controls the temperature detection circuit 110 to detect the temperature of the device. The result is output to the voltage conversion control circuit 111, which determines the erase voltage of the memory cell array 103 based on the output value of the temperature detection circuit 110 and controls the voltage conversion circuit 104.

Thus, at the time of data erasure, the erase voltage of the source region of the memory cell can be controlled according to the device temperature. In addition, the voltage conversion control circuit 111 controls the erase voltage of the source region of the memory cell so that the electric field intensity applied to the tunnel oxide film of the memory cell becomes constant regardless of the temperature. Dependency can be eliminated. FIG. 2 is a diagram showing a change in the erase voltage of the source region according to the temperature in the embodiment of FIG. 1, and the temperature becomes high so that the electric field applied to the tunnel oxide film of the memory cell becomes constant regardless of the temperature. The erasing voltage of the source region increases with the increase in the number.

(Embodiment 2) FIGS. 3 and 4 show (Embodiment 2) of the present invention. Flash EEP shown in FIG.
The ROM includes a voltage conversion circuit 304 for changing a voltage value boosted by the booster circuit 305, a pulse width conversion circuit 305 for converting a pulse width, a temperature detection circuit 310 for detecting a device temperature, and a pulse width conversion circuit 305. Is controlled by using a pulse width conversion control circuit 311 for controlling.

301, 302, 303, 306, 30
Other circuits 7, 308 and 309 are shown in FIG.
1201, 1202, 1203, 1205, 120
6, 1207, 1208.

In the flash EEPROM of FIG.
In the memory cell array 303, memory cells each having a floating gate and a control gate having the configuration shown in FIG. 14 are arranged. The memory cell array 303 is arranged in a matrix of m rows and n columns. The sources of these memory cell arrays 303 are commonly connected. The control gates of the memory cell array 303 are connected for each row. The drains of the memory cell array 3303 are connected for each column. The common source of the memory cell array 303 is connected to the booster circuit 304 and supplied with a high voltage required for erasing. The booster circuit 304 is connected to the pulse width conversion circuit 305, and converts the pulse width of the erase voltage. The row line WL of the memory cell array 303 is connected to the X decoder 302. The column line BL of the memory cell array 303 is connected via a Y gate transistor 307 to a sense amplifier circuit 308 including a load transistor for reading data. The sense amplifier circuit 308 is connected to an input / output circuit 309 for inputting / outputting data to / from an external terminal and a control circuit 301 for controlling the operation of each unit. The temperature detection circuit 310 that detects the temperature of the device is connected to a pulse width conversion control circuit 311 that controls the pulse width conversion circuit 305. The pulse width conversion control circuit 311 is connected to the pulse width conversion circuit 305. Y gate transistor 30
7 is connected to the Y decoder 306. The control circuit 301 includes an X decoder 302, a Y decoder 30
6, connected to the booster circuit 304 and the temperature detection circuit 310.

The operation of the above configuration will now be described. For the address input from the control circuit 301, the X decoder 302 selects the word line WL of the memory cell array 303, and the Y decoder 306 selects the Y gate transistor 307 connected to the bit line BL of the memory cell array 303. As a result, a predetermined voltage is applied to the word line WL and the bit line B for each selected address.
L.

At the time of erasing, the boosting circuit 304 is a circuit for supplying a high voltage necessary for erasing, and boosts the voltage converted to several pulse widths by the pulse width converting circuit 305. The high voltage supplied by the booster circuit 304 is applied to a common source line of the memory cell array 303. The pulse width conversion control circuit 311 is controlled by the pulse width conversion control circuit 311.
01.

At the time of verification, when a predetermined voltage is applied to the selected address of the memory cell array 303 to the word line WL and the bit line BL, the bit line BL
Is input to the sense amplifier circuit 308 via the Y gate transistor 307. The sense amplifier circuit 308 performs pass / fail judgment, and the control circuit 30
Output to 1.

The present invention differs from the conventional erase operation in that the device temperature is detected before the erase operation. Before performing the erase operation, the control circuit 301 controls the temperature detection circuit 310 to detect the temperature of the device. The result is output to the pulse width conversion control circuit 311. The pulse width conversion control circuit 311 determines the pulse width of the erase voltage of the memory cell array 303 based on the output value of the temperature detection circuit 310, and controls the pulse width conversion circuit 305. I do.

Thus, at the time of data erasing, the pulse width of the erasing voltage of the source region of the memory cell can be controlled according to the device temperature. If the erasing speed is high due to the temperature characteristics of the device, excessive erasure can be prevented by controlling the pulse width of the erasing voltage of the source region of the memory cell or the pulse width of the voltage applied to the control gate of the memory cell. Can be suppressed. FIG. 4 is a diagram showing a change in the pulse width of the erase voltage of the source region with temperature in the embodiment of FIG. 3. In order to suppress the occurrence of over-erasure, the pulse width of the erase voltage of the source region decreases as the temperature decreases. Is decreasing.

(Embodiment 3) FIGS. 5 and 6 show (Embodiment 3) of the present invention. Flash EEP shown in FIG.
The ROM includes a negative boosting circuit 511 and a voltage conversion circuit 512 for changing a voltage value negatively boosted by the negative boosting circuit 511.
A temperature detection circuit 509 for detecting the temperature of the device;
Voltage conversion control circuit 510 for controlling voltage conversion circuit 512
Is adopted.

501, 502, 503, 505, 50
6, 507 and 508 are shown in FIG.
1201, 1202, 1203, 1205, 120
6, 1207, 1208.

In the flash EEPROM of FIG.
In the memory cell array 503, memory cells each having a floating gate and a control gate having the configuration shown in FIG. 14 are arranged. The memory cell array 503 is arranged in a matrix of m rows and n columns. The sources of these memory cell arrays 503 are commonly connected. The control gates of the memory cell array 503 are connected for each row. The drain of the memory cell array 503 is connected for each column. The common source of the memory cell array 503 is connected to the booster circuit 504, and is supplied with a high voltage required for erasing. The row line WL of the memory cell array 503 is connected to the X decoder 502. Column line B of memory cell array 503
L is a sense amplifier circuit 5 including a load transistor for reading data via a Y gate transistor 506.
07. The sense amplifier circuit 507 includes an input / output circuit 508 for inputting / outputting data to / from external terminals,
It is connected to a control circuit 501 for controlling the operation of each unit. The temperature detection circuit 509 is connected to a voltage conversion control circuit 510 that controls the voltage conversion circuit 512. The control gate of Y gate transistor 506 is connected to Y decoder 505. The control circuit 501 includes an X decoder 502, a Y decoder
Decoder 505, booster circuit 504, temperature detection circuit 50
9, connected to a negative booster circuit 511 for generating a negative voltage. Negative booster circuit 511 is connected to voltage converter circuit 512. The voltage conversion circuit 512 is connected to the control gate of the memory cell array 503 via the X decoder 502.

The operation of the above configuration will now be described. For the address input from the control circuit 501, the X decoder 502 selects the word line WL of the memory cell array 503, and the Y decoder 505 selects the Y gate transistor 506 connected to the bit line BL of the memory cell array 503. As a result, a predetermined voltage is applied to the word line WL and the bit line B for each selected address.
L.

At the time of erasing, the boosting circuit 504 is a circuit for supplying a high voltage necessary for erasing.
Is applied to the common source line of the memory cell array 503. Further, the negative voltage supplied from the negative booster circuit 511 is converted into some voltage values by the voltage converter circuit 512 and applied to the control gate of the memory cell array 503 via the X decoder 502. The voltage conversion circuit 512 is controlled by the voltage conversion control circuit 510, and the voltage conversion control circuit 510 is controlled by the control circuit 501.

At the time of verification, when a predetermined voltage is applied to the selected address of the memory cell array 503 to the word line WL and the bit line BL, the bit line BL
Is input to the sense amplifier circuit 507 via the Y gate transistor 506. The sense amplifier circuit 507 performs pass / fail judgment, and the control circuit 50
Output to 1.

The present invention differs from the conventional erase operation in that the device temperature is detected before the erase operation. Before performing the erasing operation, the control circuit 501 controls the temperature detection circuit 509 to detect the temperature of the device. The result is output to the voltage conversion control circuit 510. The voltage conversion control circuit 510 determines the voltage of the control gate of the memory cell array 503 based on the output value of the temperature detection circuit 509, and controls the voltage conversion circuit 512.

Thus, at the time of data erasure, the voltage of the control gate of the memory cell can be controlled according to the temperature of the device. Further, by the voltage conversion control circuit 510,
By controlling the voltage of the control gate of the memory cell so that the electric field intensity applied to the tunnel oxide film of the memory cell is constant regardless of the temperature, the temperature dependence of the erase characteristics can be eliminated. FIG. 6 is a diagram showing a change in the voltage of the control gate with temperature in the embodiment of FIG. 5. As the electric field applied to the tunnel oxide film of the memory cell becomes constant irrespective of the temperature, it becomes higher as the temperature becomes higher. The control gate voltage is decreasing.

(Embodiment 4) FIGS. 7 and 8 show (Embodiment 4) of the present invention. FIG. 7 shows the flash E of the present invention.
1 shows a main part of an EPROM, which is a specific example of temperature detection circuits 110, 310, and 509 for detecting the temperature of a device employed in FIG. 1, FIG. 3, or FIG. Other circuits are the same as those in FIG. 1 or FIG. 3 or FIG.

FIG. 7 shows a MOS (Metal-Oxide-Semiconduc)
The present invention detects the temperature of a device by utilizing the temperature characteristics of the current flowing through the transistor.

FIG. 8 shows the temperature characteristics of the transistor in FIG. As the voltage of the control gate increases, the amount of current between the drain region and the source region increases. In addition, as the temperature increases, the threshold voltage of the transistor increases, and the current amplification factor with respect to the voltage increases.

Thus, the temperature of the device can be known by applying a voltage to the control gate of the transistor and detecting the amount of current between the drain region and the source region where the change in current due to temperature becomes large.

(Embodiment 5) FIG. 9 shows (Embodiment 5) of the present invention. FIG. 9 shows a flash EEPROM of the present invention.
The main part of M is shown, and this circuit is an embodiment of the temperature detecting circuits 110, 310, 509 for detecting the temperature of the device employed in FIG. 1, FIG. 3, or FIG. Other circuits are the same as those in FIG. 1 or FIG. 3 or FIG.

The circuit shown in FIG. 9 includes a constant current source 901 for supplying a constant current, a resistance component 902 through which a current flows from the constant current source 901, and a reference whose voltage value does not fluctuate due to the voltage and temperature at both ends of the resistance component 902. It comprises a comparator 903 for comparing the voltage (Vref).

Next, the operation of the above configuration will be described. Although the resistance value of the resistance component 902 changes depending on the temperature, the constant current source 901 supplies a constant current regardless of the temperature. When the temperature rises, the resistance value of the resistance component 902 increases, so that the voltage across the resistance component 902 increases. Therefore, the reference voltage (V) whose voltage value does not fluctuate due to the voltage and the temperature at both ends of the resistance component 902 is determined by the comparator 903.
By comparing ref), the temperature of the device can be detected. As a method of generating a reference voltage (Vref) whose voltage value does not change with temperature, there is a band gap reference voltage generation circuit as shown in FIG.

(Embodiment 6) FIG. 10 shows (Embodiment 6) of the present invention. FIG. 10 shows a flash EEP of the present invention.
1 shows a main part of a ROM, and this circuit is an embodiment of temperature detecting circuits 110, 310, and 509 for detecting the temperature of a device employed in FIG. 1, FIG. 3, or FIG. Other circuits are the same as those in FIG. 1 or FIG. 3 or FIG.

The circuit shown in FIG. 10 includes a constant current source 1001 for supplying a constant current, a diode-connected reference voltage generation circuit 1002 connected in series with the constant current source 1001, and a voltage of the reference voltage generation circuit 1001. It comprises a comparator 1003 for comparing a reference voltage (Vref) whose voltage value does not change with temperature.

The operation of the above configuration will now be described. Diode-connected reference voltage generating circuit 10
Reference numeral 02 denotes a circuit for connecting a MOS diode to obtain a relatively high reference voltage such as 4V. If there is no MOS substrate effect, the reference voltage is the product of the number of MOSs and the threshold (Vt). Temperature dependence of Vt is -2 mV / ° C
Therefore, when the bonding temperature changes from 0 ° C. to 100 ° C., the voltage changes by 0.2V. If as many as six such diodes are connected and used as a reference voltage, a temperature change of 100 ° C. causes a fluctuation of 1.2 V. Therefore, the temperature of the device can be detected by comparing the reference voltage of the diode-connected reference voltage generation circuit 1002 with the reference voltage (Vref) whose voltage value does not change with temperature by the comparator 1003. As a method of generating a reference voltage (Vref) whose voltage value does not change with temperature,
There is a bandgap reference voltage generation circuit as shown in FIG.

(Embodiment 7) FIG. 11 shows (Embodiment 7) of the present invention. FIG. 11 shows a flash EEP of the present invention.
1 shows a main part of a ROM, and this circuit is a temperature detection circuit 1 for detecting the temperature of a device employed in FIGS.
10 or 310 or 509 are examples. Other circuits are the same as those in FIG. 1 or FIG. 3 or FIG.

The circuit shown in FIG. 11 is a ring oscillator 11 which is an oscillation circuit in which odd-numbered inverters are connected in a ring.
01, a charge pump circuit 1104 connected to the ring oscillator 1101, a capacitance component 1102, and a comparator 110 that compares a voltage across the capacitance component 1102 and a reference voltage (Vref) whose voltage value does not change with temperature.
3 is comprised.

The operation of such a configuration will now be described. The ring oscillator 1101 is used to periodically drive the charge pump circuit 1104 to generate a boosted power supply and a substrate voltage. The oscillation frequency fOSC of the ring oscillator 1101 is given by fOSC = 1 / [(2n + 1) (tH + tL)] where the number of stages is 2n + 1. Here, tH and tL are delay times of the constituent inverters, that is, a delay time when each input changes to H level and a case when each input changes to L level. Since tH and tL have temperature dependence, the oscillation frequency fOSC of the ring oscillator 1101 has temperature dependence. Thus, the temperature-dependent charge is stored in the capacitance component 1102. Therefore, the comparator 1103 can detect the temperature of the device by comparing the voltage between both ends of the capacitance component 1102 with the reference voltage (Vref) whose voltage value does not fluctuate depending on the temperature. As a method for generating a reference voltage (Vref) whose voltage value does not change with temperature, there is a band gap reference voltage generation circuit as shown in FIG.

[0062]

As described above, according to the present invention, at the time of data erasure, the erase voltage of the source region of the memory cell or the voltage applied to the control gate of the memory cell can be controlled according to the temperature of the device. Also, by controlling the erase voltage of the source region of the memory cell or the voltage applied to the control gate of the memory cell so that the electric field intensity applied to the tunnel oxide film of the memory cell becomes constant regardless of the device temperature. In addition, the temperature range that guarantees the erasing operation can be widened.

At the time of data erasing, the pulse width of the erasing voltage of the source region of the memory cell can be controlled according to the temperature of the device. When the erasing speed is high due to the temperature characteristics of the device, the occurrence of over-erasing can be suppressed by controlling the pulse width of the erasing voltage in the source region of the memory cell.

[Brief description of the drawings]

FIG. 1 is a block diagram showing (Embodiment 1) a flash EEPROM of the present invention;

FIG. 2 is a diagram showing a change in an erase voltage of a source region according to a temperature in the embodiment;

FIG. 3 is a block diagram showing a flash EEPROM according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a change in pulse width of an erase voltage of a source region according to temperature in the embodiment;

FIG. 5 is a block diagram showing (Embodiment 3) a flash EEPROM of the present invention;

FIG. 6 is a diagram showing a change in voltage applied to a gate region according to temperature in the embodiment;

FIG. 7 is a circuit diagram showing a flash EEPROM (Embodiment 4) of the present invention;

FIG. 8 is a graph showing temperature characteristics of the transistor according to the embodiment.

FIG. 9 is a configuration diagram of a flash EEPROM (Embodiment 5) of the present invention;

FIG. 10 is a configuration diagram of a flash EEPROM (Embodiment 6) of the present invention;

FIG. 11 is a configuration diagram of a flash EEPROM (Embodiment 7) of the present invention;

FIG. 12 is a diagram showing a bandgap reference voltage generation circuit.

FIG. 13 is a configuration diagram of a conventional flash EEPROM.

FIG. 14 is a diagram showing a sectional structure of a flash EEPROM cell;

[Explanation of symbols]

101, 301, 501, 1201 Control circuit 102, 302, 502, 1202 X decoder 103, 303, 503, 1203 Memory cell array 104, 512 Voltage conversion circuit 105, 304, 504, 1204 Booster circuit 106, 306, 505, 1205 Y Decoders 107, 307, 506, 1206 Y gate transistors 108, 308, 507, 1207 Sense amplifier circuits 109, 309, 508, 1208 Input / output circuits 110, 310, 509 Temperature detection circuits 111, 510 Voltage conversion control circuits 305 Pulse width conversion Circuit 311 Pulse width conversion control circuit 511 Negative booster circuit 1301 Control gate 1302, 1304 Insulating film 1305 Drain region 1306 Source region 1307 P substrate 901, 1001 Constant current source 902 Resistance component 903,1003,1103 comparator 1002 diode-connected reference voltage generating circuit 1101 ring oscillator 1102 capacitive component 1104 charge pump circuit

Claims (8)

[Claims] A temperature detecting circuit for detecting a temperature of the memory cell array; and an electric field between a source region and a floating gate of the memory cell according to a temperature detected by the temperature detecting circuit when a memory cell constituting the memory cell array is rewritten. And a voltage conversion control circuit for controlling a state of a voltage applied to the source region so as to be constant. 2. A semiconductor substrate of a first conductivity type, a source region and a drain region of a second conductivity type formed on one main surface of the semiconductor substrate, and formed on the semiconductor substrate via a first insulating film. When rewriting a nonvolatile semiconductor memory device having a floating gate and a memory cell formed of a control gate formed on the floating gate via a second insulating film, an electric field between the source region and the floating gate is constant. A rewriting method for a non-volatile semiconductor storage device, wherein rewriting is performed by controlling a voltage application state according to a temperature of the non-volatile semiconductor storage device so that 3. A rewriting method for a nonvolatile semiconductor memory device according to claim 2, wherein a pulse width of a voltage applied to said gate region is controlled according to a temperature of said nonvolatile semiconductor memory device. 4. The rewriting method for a nonvolatile semiconductor memory device according to claim 2, wherein a voltage applied to said gate region is controlled according to a temperature of said nonvolatile semiconductor memory device. 5. A source region and a drain region of a second conductivity type formed on one main surface of a semiconductor substrate on which a memory cell is formed, and a control gate formed on the semiconductor substrate via a first insulating film. 5. The temperature of the nonvolatile semiconductor memory device is detected by an amount of current flowing between the drain region and the source region in the transistor including
The rewriting method of the nonvolatile semiconductor memory device according to any one of the above. 6. A temperature-dependent voltage generated at both ends of the resistance component by flowing a current from the constant current source to the resistance component;
5. The rewriting method for a nonvolatile semiconductor memory device according to claim 2, wherein a temperature of the nonvolatile semiconductor memory device is detected by comparing a reference voltage whose voltage value does not fluctuate with temperature by a comparator. 7. A voltage having a temperature dependency generated at both ends of said resistance component by flowing a current from a constant current source to a diode-connected reference voltage generating circuit, and a reference voltage whose voltage value does not vary with temperature, 5. The rewriting method for a nonvolatile semiconductor memory device according to claim 2, wherein the temperature of the nonvolatile semiconductor memory device is detected by comparing with a comparator. 8. An odd number of stages of inverters are connected in a ring shape, and a signal is supplied from a ring oscillator whose oscillation frequency has temperature dependence to a capacitance component to accumulate temperature-dependent charges, and generated at both ends of the capacitance component. The nonvolatile semiconductor memory according to any one of claims 2 to 4, wherein a voltage to be detected and a first reference voltage whose voltage value does not fluctuate with temperature are compared by a comparator to detect the temperature of the nonvolatile semiconductor memory device. A method for rewriting a storage device.