JP2002246598A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002246598A JP2002246598A JP2001039110A JP2001039110A JP2002246598A JP 2002246598 A JP2002246598 A JP 2002246598A JP 2001039110 A JP2001039110 A JP 2001039110A JP 2001039110 A JP2001039110 A JP 2001039110A JP 2002246598 A JP2002246598 A JP 2002246598A
- Authority
- JP
- Japan
- Prior art keywords
- section
- resistance
- semiconductor device
- transistor element
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 40
- 230000001681 protective effect Effects 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 33
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000008188 pellet Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 silicon boron ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関し、特にその静電耐圧を向上させた半
導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with improved electrostatic withstand voltage and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の半導体装置として、ペレットサイ
ズ：０．５ｍｍ□程度の小信号縦型ＭＯＳＦＥＴは、図
８の回路図に示されるように、双方向ツェナーダイオー
ド部２を保護ダイオードとして設けたものがある。この
ＭＯＳＦＥＴは、その素子部５のゲートに抵抗部３の一
端が接続され、この抵抗部３の他端と素子部５のソース
との間に双方向ツェナーダイオード部２が接続されたも
のである。2. Description of the Related Art As a conventional semiconductor device, a small signal vertical MOSFET having a pellet size of about 0.5 mm square is provided with a bidirectional Zener diode section 2 as a protection diode as shown in a circuit diagram of FIG. There is something. In this MOSFET, one end of the resistor 3 is connected to the gate of the element 5, and the bidirectional Zener diode 2 is connected between the other end of the resistor 3 and the source of the element 5. .
【０００３】この従来の小信号縦型ＭＯＳＦＥＴでは、
図９の平面図に示されるように、半導体チップ１が、素
子部５、双方向ツェナーダイオード部２、抵抗部３の三
つに分かれており、静電耐圧を向上する手段として、抵
抗部３の多結晶（ポリ）シリコン層（１３）の長さＬを
長くして静電耐圧を向上していた。In this conventional small signal vertical MOSFET,
As shown in the plan view of FIG. 9, the semiconductor chip 1 is divided into three parts, an element part 5, a bidirectional Zener diode part 2, and a resistance part 3. The length L of the polycrystalline (poly) silicon layer (13) was increased to improve the electrostatic withstand voltage.
【０００４】この抵抗部３の多結晶シリコン抵抗Ｒは、
多結晶シリコンの長さをＬ、幅をＷとし、層抵抗をρｓ
とした時、次の式（１）で計算される。The polycrystalline silicon resistance R of the resistance part 3 is
The length of the polycrystalline silicon is L, the width is W, and the layer resistance is ρs
Is calculated by the following equation (1).
【０００５】Ｒ＝ρｓ（Ｌ／Ｗ）……（１） また、この半導体チップの製造方法は、その製造工程順
を示す、図１０（ａ）〜（ｄ）の断面図に示される。ま
ず図１０（ａ）に示すように、Ｎ+型半導体基板７上に
Ｎ-層エピタキシャル層８を形成し、双方向ツェナーダ
イオード部２、抵抗部３の下にＰウェル領域１８を形成
後、素子部５のＮ-層エピタキシャル層８上にゲート酸
化膜１２を２０〜６０ｎｍ（ナノメータ）成長させ、Ｐ
ウェル領域１８上にフィールド酸化膜１７を形成し、こ
れらの上に多結晶シリコン膜１３を４００〜６００ｎｍ
成長させる。次に、チップ全面に多結晶シリコン・ボロ
ンのイオン注入を行い、さらに、図１０（ｂ）に示すよ
うに、フォトリソグラフィ技術を用いて多結晶シリコン
膜１３を所定の形状にし、ベース・イオン注入を行い、
Ｐ型ベース領域９及び双方向ツェナーダイオード部２、
抵抗部３をＰ型領域１９に形成する。R = ρs (L / W) (1) The method of manufacturing the semiconductor chip is shown in the sectional views of FIGS. 10A to 10D showing the order of the manufacturing steps. First, as shown in FIG. 10A, an N − layer epitaxial layer 8 is formed on an N + type semiconductor substrate 7, and a P well region 18 is formed below the bidirectional Zener diode portion 2 and the resistor portion 3. A gate oxide film 12 is grown on the N − layer epitaxial layer 8 of the element portion 5 by 20 to 60 nm (nanometer).
A field oxide film 17 is formed on the well region 18, and a polycrystalline silicon film 13 is
Let it grow. Next, ion implantation of polycrystalline silicon boron is performed on the entire surface of the chip. Further, as shown in FIG. 10B, the polycrystalline silicon film 13 is formed into a predetermined shape using a photolithography technique, and base ion implantation is performed. Do
A P-type base region 9 and a bidirectional Zener diode unit 2;
The resistance section 3 is formed in the P-type region 19.
【０００６】次に、図１０（ｃ）に示すように、フォト
リソグラフィ技術を用いて双方向ツェナーダイオード部
２をレジスト２３でカバーして、素子部５のスイッチン
グ・スピードを上げるため、素子部５と抵抗部３にポリ
シリ・リン拡散を行い、多結晶シリコン膜１３の層抵抗
ρｓを５〜２０Ω／□にする。Next, as shown in FIG. 10C, the bidirectional Zener diode section 2 is covered with a resist 23 using a photolithography technique to increase the switching speed of the element section 5. And the resistance portion 3 are diffused with polysilicon and phosphorus to make the layer resistance ρs of the polycrystalline silicon film 13 5 to 20 Ω / □.
【０００７】その後、図１０（ｄ）に示すように、所定
の部分をカバーし、素子部５にＮ+型ソース領域１１
と、Ｐ+型のバックゲート１０とを形成し、双方向ツェ
ナーダイオード部２、抵抗部３にＮ+領域２０を形成さ
せ、抵抗部３をポリシリコン抵抗部２１とする。次に、
層間絶縁膜１４を成長させ、ソース電極用配線１５とゲ
ート電極用配線１６を形成する。Thereafter, as shown in FIG. 10D, a predetermined portion is covered, and an N + type source region 11 is
And a P + -type back gate 10, an N + region 20 is formed in the bidirectional Zener diode section 2 and the resistor section 3, and the resistor section 3 is a polysilicon resistor section 21. next,
An interlayer insulating film 14 is grown, and a source electrode wiring 15 and a gate electrode wiring 16 are formed.
【０００８】なお、縦型ＭＯＳＦＥＴの保護ダイオード
の静電耐圧を向上させた例として、ダイオードのアノー
ド領域とカソード領域の接合面積を増加するようにした
ものが、特開平４−２３４１７３号公報や特開平９−９
７９０１号公報に示されている。As an example of improving the electrostatic withstand voltage of a protection diode of a vertical MOSFET, an example in which the junction area between an anode region and a cathode region of a diode is increased is disclosed in Japanese Patent Laid-Open No. 4-234173. Kaihei 9-9
No. 7901.
【０００９】[0009]
【発明が解決しようとする課題】しかし、この従来技術
では、次のような問題点があった。まず、この小信号縦
型ＭＯＳＦＥＴは静電耐圧（特にＭＩＬ法）が弱く、破
壊箇所は全て、双方向ツェナーダイオード部２であっ
た。その理由は、マスクレイアウト上、双方向ツェナー
ダイオード部２はゲートパッド部６の直下に配置してい
るため、双方向ツェナーダイオード部２の領域はゲート
パッドサイズで必然的に決まってしまい、小信号縦型Ｍ
ＯＳＦＥＴの場合は、ゲートパッドサイズが小さいため
に双方向ツェナーダイオード部２も小さくなり、双方向
ツェナーダイオード部２の周囲長が短くなり、ジュール
熱により双方向ツェナーダイオード部２で破壊してい
た。また、縦型ＭＯＳＦＥＴの場合は、素子部５のスイ
ッチングスピードを上げるため、多結晶ポリシリの層抵
抗値ρｓを下げており、素子部５の多結晶シリコンの層
抵抗値ρｓと抵抗部３の多結晶シリコンの層抵抗値ρｓ
を同時にポリシリコンリン拡散を行い、多結晶シリコン
の層抵抗値ρｓを決定していたために抵抗部３の抵抗値
を大きくすることが困難であった。However, this conventional technique has the following problems. First, this small-signal vertical MOSFET had a weak electrostatic withstand voltage (particularly the MIL method), and all the destruction points were the bidirectional Zener diode sections 2. The reason is that, on the mask layout, the bidirectional Zener diode section 2 is disposed directly below the gate pad section 6, so that the area of the bidirectional Zener diode section 2 is inevitably determined by the gate pad size, and the small signal Vertical M
In the case of the OSFET, since the gate pad size is small, the size of the bidirectional Zener diode unit 2 is also reduced, the circumference of the bidirectional Zener diode unit 2 is shortened, and the bidirectional Zener diode unit 2 is broken by Joule heat. In the case of a vertical MOSFET, the layer resistance value ρs of the polycrystalline polysilicon is reduced in order to increase the switching speed of the element portion 5. Layer resistance ρs of crystalline silicon
At the same time, polysilicon phosphorus diffusion was performed to determine the layer resistance value ρs of the polycrystalline silicon, so that it was difficult to increase the resistance value of the resistance portion 3.
【００１０】また、前述の特開平４−２３４１７３号公
報や特開平９−９７９０１号公報に記載されたものは、
保護ダイオードを対象とするため、その構造が複雑とな
っていた。[0010] Further, those described in the above-mentioned JP-A-4-234173 and JP-A-9-97901,
Since the protection diode is used, its structure is complicated.
【００１１】本発明の目的は、以上の問題点を解決し、
抵抗部の抵抗値を大きくして、トランジスタの静電耐圧
を向上させた半導体装置及びその製造方法を提供するこ
とにある。An object of the present invention is to solve the above problems,
It is an object of the present invention to provide a semiconductor device in which a resistance value of a resistance portion is increased and an electrostatic withstand voltage of a transistor is improved, and a manufacturing method thereof.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体装置の構
成は、小信号縦型ＭＯＳＦＥＴとして、トランジスタ素
子部に隣接して、その周囲長を長くしこのトランジスタ
素子部のソース電極に一端を接続した保護ダイオード部
と、この保護ダイオード部の外周に配置され前記トラン
ジスタ素子部のゲート電極に一端が接続され他端が前記
保護ダイオード部の他端に接続される第１の抵抗部とが
配置されたパターンを有することにより、前記第１の抵
抗部の抵抗値を大きくなるようにしたことを特徴とす
る。A semiconductor device according to the present invention is configured as a small-signal vertical MOSFET, which is adjacent to a transistor element portion, has a longer peripheral length, and has one end connected to a source electrode of the transistor element portion. And a first resistance portion disposed on the outer periphery of the protection diode portion and having one end connected to the gate electrode of the transistor element portion and the other end connected to the other end of the protection diode portion. The first resistor section has a large resistance value by having a pattern.
【００１３】本発明において、保護ダイオード部が、双
方向ツェナーダイオード部からなることもでき、第１の
抵抗部が、双方向ツェナーダイオード部の最外周を囲む
ように配置されることができ、また、第２の抵抗部が、
双方向ツェナーダイオード部最内周に配置され、この第
２の抵抗部と第１の抵抗部とがそれぞれの一端で接続さ
れることができ、さらに第１または第２の抵抗部の層抵
抗値を前記トランジスタ素子部のゲート電極の層抵抗値
より大きくなるようにできる。In the present invention, the protection diode section may comprise a bidirectional Zener diode section, and the first resistor section may be arranged so as to surround the outermost periphery of the bidirectional Zener diode section. , The second resistor section
The second resistance part and the first resistance part are arranged at the innermost circumference of the bidirectional Zener diode part, and can be connected at one end thereof. Further, the layer resistance value of the first or second resistance part Can be made larger than the layer resistance value of the gate electrode of the transistor element portion.
【００１４】本発明の他の構成は、小信号縦型ＭＯＳＦ
ＥＴとして、トランジスタ素子部に隣接して、周囲長を
長くした保護ダイオード部と、この保護ダイオード部の
外周に配置され前記トランジスタ素子部のゲートと接続
される抵抗部とが配置されたパターンを有する半導体装
置の製造方法において、前記トランジスタ素子部のゲー
ト電極となる多結晶シリコン膜の層抵抗と前記抵抗部の
多結晶シリコンの層抵抗とを別々の工程により製造し
て、前記抵抗部の層抵抗値を前記ゲート電極の層抵抗値
より大きくなるようにしたこと特徴とする。Another configuration of the present invention is a small signal vertical type MOSF.
As ET, a pattern is provided in which a protection diode portion having a longer perimeter is arranged adjacent to the transistor element portion, and a resistance portion disposed on the outer periphery of the protection diode portion and connected to the gate of the transistor element portion is provided. In a method of manufacturing a semiconductor device, a layer resistance of a polycrystalline silicon film serving as a gate electrode of the transistor element portion and a layer resistance of polycrystalline silicon of the resistance portion are manufactured in separate steps, and the layer resistance of the resistance portion is formed. The value is set to be larger than the layer resistance value of the gate electrode.
【００１５】本発明において、多結晶シリコンの層抵抗
の形成を多結晶シリコン・リン拡散により実施し、抵抗
部およびトランジスタ素子部のゲート電極の各層抵抗値
を調整することができ、また、トランジスタ素子部に多
結晶シリコン・リン拡散を実施する際に、抵抗部および
保護ダイオード部がレジストで覆われるようにすること
ができる。In the present invention, the layer resistance of polycrystalline silicon is formed by polycrystalline silicon phosphorus diffusion, whereby the resistance of each layer of the resistance portion and the gate electrode of the transistor element portion can be adjusted. The resistive portion and the protective diode portion can be covered with a resist when polycrystalline silicon phosphorus diffusion is performed on the portion.
【００１６】[0016]
【発明の実施の形態】次に本発明の実施形態を図面によ
り説明する。図１，図２は本発明の一実施形態の半導体
チップの平面図およびそのＡ―Ａ線の断面図である。こ
の実施形態の回路図は従来例の図８と同じであり、その
製造工程も従来例と同様であり、図３（ａ）〜（ｄ）に
示される。本実施形態の半導体装置は、ペレットサイズ
０．５ｍｍ□程度の小信号縦型ＭＯＳＦＥＴのレイアウ
ト設計を、図１に示すように、素子部５、周囲長の長い
双方向ツェナーダイオード部２、この双方向ツェナーダ
イオード部２の最外周に抵抗部３を配置したパターンを
有するものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are a plan view of a semiconductor chip according to an embodiment of the present invention and a sectional view taken along line AA thereof. The circuit diagram of this embodiment is the same as that of FIG. 8 of the conventional example, and the manufacturing process is the same as that of the conventional example, and is shown in FIGS. In the semiconductor device of the present embodiment, the layout design of a small-signal vertical MOSFET having a pellet size of about 0.5 mm square is performed, as shown in FIG. It has a pattern in which a resistance portion 3 is arranged on the outermost periphery of the directional Zener diode portion 2.
【００１７】この半導体チップの製造工程について、Ｎ
チャネル型小信号縦型ＭＯＳＦＥＴの場合を図３（ａ）
〜（ｄ）により説明する。このチップの製造に当たって
は、まず図３（ａ）に示すように、Ｎ+型半導体基板７
上にＮ-層エピタキシャル層８を形成し、双方向ツェナ
ーダイオード部２、抵抗部３の下にＰウェル領域１８を
形成し、Ｐウェル領域１８上にフィールド酸化膜１７を
形成した後、これら素子部５のＮ-層エピタキシャル層
８上にゲート酸化膜１２を２０〜６０ｎｍ成長させ、そ
の上に多結晶シリコン膜１３を４００〜６００ｎｍ成長
させる。次に、図３（ｂ）に示すように、フォトリソグ
ラフィ技術を用いて多結晶ポリシリ膜１３を所定の形状
にし、ベース・イオン注入を行い、Ｐ型ベース領域９及
び、双方向ツェナーダイオード部２、抵抗部３をＰ型領
域１９に形成する。In the manufacturing process of this semiconductor chip, N
FIG. 3A shows a case of a channel type small signal vertical MOSFET.
This will be described with reference to (d). In the manufacture of the chip, first, as shown in FIG. 3 (a), N + -type semiconductor substrate 7
An N − layer epitaxial layer 8 is formed thereon, a P well region 18 is formed below the bidirectional Zener diode portion 2 and the resistor portion 3, and a field oxide film 17 is formed on the P well region 18. A gate oxide film 12 is grown to a thickness of 20 to 60 nm on the N − layer epitaxial layer 8 in the portion 5, and a polycrystalline silicon film 13 is grown to a thickness of 400 to 600 nm. Next, as shown in FIG. 3B, the polycrystalline polysilicon film 13 is formed into a predetermined shape using a photolithography technique, base ions are implanted, and the P-type base region 9 and the bidirectional Zener diode portion 2 are formed. , The resistance portion 3 is formed in the P-type region 19.
【００１８】次に、チップ全面に多結晶シリコン・ボロ
ン・イオン注入を行い、図３（ｃ）に示すように、フォ
トリソグラフィ技術を用いて双方向ツェナーダイオード
部２をレジスト２３でカバーして、素子部５のスイッチ
ング・スピードを上げるため、素子部５と抵抗部３にポ
リシリリン拡散を行い、多結晶シリコン膜１３の層抵抗
ρｓを５〜２０Ω／□にする。その後、所定の部分をカ
バーし、素子部５にＮ+型ソース領域１１と、Ｐ+型のバ
ックゲート１０とを形成し、双方向ツェナーダイオード
部２、抵抗部３にＮ+領域２０を形成させ、抵抗部３を
ポリシリコン抵抗部２１とする。次に、図３（ｄ）に示
すように、層間絶縁膜１４を成長させ、ソース電極用配
線１５、ゲート電極用配線１６を形成し、半導体チップ
を完成させる。Next, polycrystalline silicon boron ions are implanted into the entire surface of the chip, and as shown in FIG. 3C, the bidirectional Zener diode 2 is covered with a resist 23 by using a photolithography technique. In order to increase the switching speed of the element section 5, polysilylin is diffused into the element section 5 and the resistor section 3 to set the layer resistance ρs of the polycrystalline silicon film 13 to 5 to 20Ω / □. Thereafter, a predetermined portion is covered, an N + type source region 11 and a P + type back gate 10 are formed in the element portion 5, and a bidirectional Zener diode portion 2 and an N + region 20 are formed in the resistance portion 3. Then, the resistance part 3 is made to be the polysilicon resistance part 21. Next, as shown in FIG. 3D, the interlayer insulating film 14 is grown, the source electrode wiring 15 and the gate electrode wiring 16 are formed, and the semiconductor chip is completed.
【００１９】図４は本発明の第２の実施形態の回路図、
図５，図６はそのチップの平面図およびその断面図であ
る。本実施形態は、図３のように、抵抗部３にさらに抵
抗部４が付加されたもので、図５のように、素子部５、
周囲長の長い双方向ツェナーダイオード部２、双方向ツ
ェナーダイオード部２の最内周に抵抗部３、双方向ツェ
ナーダイオード部２の外側に抵抗部４を配置したパター
ンにしたものである。FIG. 4 is a circuit diagram of a second embodiment of the present invention.
5 and 6 are a plan view and a sectional view of the chip, respectively. In the present embodiment, as shown in FIG. 3, a resistor 4 is further added to the resistor 3, and as shown in FIG.
The pattern has a bidirectional Zener diode portion 2 having a long perimeter, a resistor portion 3 disposed on the innermost periphery of the bidirectional Zener diode portion 2, and a resistor portion 4 disposed outside the bidirectional Zener diode portion 2.
【００２０】従来の小信号縦型ＭＯＳＦＥＴは、図９に
示すように双方向ツェナーダイオード部２はゲートパッ
ド部６の直下にあり、ゲートパッドの大きさに制約さ
れ、ツェナーダイオード部２の周囲長が短かかったが、
本実施例では、図１、４に示すように双方向ツェナーダ
イオード部２の最外周に抵抗部３を配置すること、及
び、双方向ツェナーダイオード部２の最内周に抵抗部３
と双方向ツェナーダイオード部２の最外周に抵抗部４を
配置することにより、双方向ツェナーダイオード部２の
周囲長が約２倍になり、双方向ツェナーダイオード部２
の内部抵抗を低下することができる。In the conventional small signal vertical MOSFET, as shown in FIG. 9, the bidirectional Zener diode section 2 is located immediately below the gate pad section 6 and is limited by the size of the gate pad. Was short,
In this embodiment, as shown in FIGS. 1 and 4, the resistor 3 is disposed on the outermost periphery of the bidirectional Zener diode unit 2, and the resistor 3 is disposed on the innermost periphery of the bidirectional Zener diode unit 2.
By arranging the resistor section 4 on the outermost periphery of the bidirectional Zener diode section 2, the peripheral length of the bidirectional Zener diode section 2 is approximately doubled,
Internal resistance can be reduced.
【００２１】これら第１、第２の実施形態では、抵抗部
３，４の抵抗値が大きくなるように工夫したものである
が、次の第３実施形態のように、これら抵抗部３，４の
層抵抗値を大きくなるようにしてもよい。また、第１、
第２の実施形態と第３実施形態とを組み合わせることに
より、より小型化され、静電耐圧のある半導体装置が得
られることも明らかである。In the first and second embodiments, the resistance values of the resistance portions 3 and 4 are devised so as to increase. However, as in the third embodiment described below, these resistance portions 3 and 4 are devised. May be increased. First,
It is also clear that a combination of the second embodiment and the third embodiment provides a more miniaturized semiconductor device having an electrostatic breakdown voltage.
【００２２】さらに、図７（ａ）〜（ｄ）は本発明の第
３の実施形態の製造工程を説明する半導体チップの断面
図である。本実施形態は、図７の断面図ように素子部５
のゲート電極の多結晶シリコン１３の層抵抗ρｓと抵抗
部３の多結晶シリコン抵抗部２１の層抵抗ρｓを別々に
製造すること特徴とする。FIGS. 7A to 7D are cross-sectional views of a semiconductor chip illustrating a manufacturing process according to a third embodiment of the present invention. In the present embodiment, as shown in the sectional view of FIG.
Is characterized in that the layer resistance ρs of the polycrystalline silicon 13 of the gate electrode and the layer resistance ρs of the polycrystalline silicon resistance part 21 of the resistance part 3 are separately manufactured.
【００２３】まず図７（ａ）に示すように、Ｎ+型半導
体基板７上にＮ-層エピタキシャル層８を形成し、双方
向ツェナーダイオード部２、抵抗部３の下にＰウェル領
域１８を形成後、素子部５のＮ-層エピタキシャル層８
上にゲート酸化膜１２を２０〜６０ｎｍ成長させ、その
上に多結晶シリコン膜１３を約４００〜６００ｎｍ成長
させる。First, as shown in FIG. 7A, an N - layer epitaxial layer 8 is formed on an N + type semiconductor substrate 7, and a P well region 18 is formed below the bidirectional Zener diode portion 2 and the resistor portion 3. After formation, the N − layer epitaxial layer 8 of the element portion 5 is formed.
A gate oxide film 12 is grown thereon by 20 to 60 nm, and a polycrystalline silicon film 13 is grown thereon by about 400 to 600 nm.
【００２４】次に、チップ全面に多結晶シリコン・ボロ
ン・イオン注入を行い、次に、フォトリソグラフィ技術
を用いて双方向ツェナーダイオード部２と抵抗部３をレ
ジストでカバーして、素子部５のスイッチング・スピー
ドを上げるため、素子部５にポリシリコンリン拡散を行
い、多結晶シリコン膜の層抵抗ρｓを５〜２０Ω／□に
する。次に、図７（ｂ）に示すように、フォトリソグラ
フィ技術を用いて多結晶シリコン膜１３を所定の形状に
し、ベース・イオン注入を行い、Ｐ型ベース領域及び、
双方向ツェナーダイオード部２、３をＰ型領域に形成す
る。その後、図７（ｃ）に示すように、所定の部分をカ
バーし、素子部５にＮ+型ソース領域と、Ｐ+型のバック
ゲートとを形成し、双方向ツェナーダイオード部２、抵
抗部３にＮ+領域１０を形成する。次に、図７（ｄ）に
示すように、層間絶縁膜１４を成長させ、ソース電極用
配線１５、ゲート電極用配線１６を形成する。Next, polycrystalline silicon boron ions are implanted into the entire surface of the chip, and then the bidirectional Zener diode section 2 and the resistor section 3 are covered with a resist using photolithography technology. In order to increase the switching speed, the element portion 5 is diffused with polysilicon phosphorus, and the layer resistance ρs of the polycrystalline silicon film is set to 5 to 20 Ω / □. Next, as shown in FIG. 7B, the polycrystalline silicon film 13 is formed into a predetermined shape using a photolithography technique, base ions are implanted, and a P-type base region and
The bidirectional Zener diode units 2 and 3 are formed in a P-type region. Thereafter, as shown in FIG. 7C, a predetermined portion is covered, an N + type source region and a P + type back gate are formed in the element portion 5, and the bidirectional Zener diode portion 2, the resistance portion An N + region 10 is formed in 3. Next, as shown in FIG. 7D, an interlayer insulating film 14 is grown, and a source electrode wiring 15 and a gate electrode wiring 16 are formed.
【００２５】従来は、図１０に示すように、小信号縦型
ＭＯＳＦＥＴにおいては、素子部５の多結晶ポリシリ膜
と抵抗部３の多結晶シリコン膜とを同時にポリシリリン
拡散を行い、層抵抗ρｓを決定してきたため、抵抗部３
を大きくすることが困難であったが、この実施形態で
は、多結晶シリコンリン拡散を素子部５のみに行い、抵
抗部３をレジストでカバーすることにより、抵抗部３の
ポリシリコンの層抵抗ρｓを高ρｓ化することにより、
少ない領域で大きな抵抗値を形成することができる。Conventionally, as shown in FIG. 10, in a small-signal vertical MOSFET, the polycrystalline polysilicon film of the element portion 5 and the polycrystalline silicon film of the resistor portion 3 are simultaneously subjected to polysilicon diffusion, and the layer resistance ρs is reduced. Since it has been decided,
However, in this embodiment, polycrystalline silicon phosphorus diffusion is performed only in the element portion 5 and the resistor portion 3 is covered with a resist, so that the polysilicon layer resistance ρs of the resistor portion 3 is increased. By increasing ρs
A large resistance value can be formed in a small area.
【００２６】[0026]
【発明の効果】以上説明したように、本発明は、ペレッ
トサイズ：０．５ｍｍ□程度の小信号縦型ＭＯＳＦＥＴ
における双方向ツェナーダイオード部と抵抗部のレイア
ウトにより、双方向ツェナーダイオード部の周囲長を長
くし、双方向ツェナーダイオード部の内部抵抗を低下さ
せ、静電耐圧を向上できるという効果があり、また、こ
の小信号縦型ＭＯＳＦＥＴの抵抗部を形成する時に、抵
抗部の多結晶シリコン膜の層抵抗ρｓと素子部のゲート
電極の多結晶シリコン膜の層抵抗ρｓを別々の工程にす
ることにより、抵抗部の多結晶シリコン膜の層抵抗ρｓ
を高ρｓ化し、少ない領域で大きな抵抗値を形成するこ
とができ、小信号縦型ＭＯＳＦＥＴのペレットサイズを
大きくすることなく、静電耐圧を向上できるという効果
がある。As described above, the present invention relates to a small-signal vertical MOSFET having a pellet size of about 0.5 mm square.
The layout of the bidirectional Zener diode part and the resistance part in the above has the effect of increasing the perimeter of the bidirectional Zener diode part, reducing the internal resistance of the bidirectional Zener diode part, and improving the electrostatic withstand voltage. When forming the resistance portion of the small signal vertical MOSFET, the resistance of the polycrystalline silicon film of the resistance portion and the resistance of the polycrystalline silicon film of the gate electrode of the element portion are formed in separate steps, so that the resistance is increased. Resistance ρs of the polycrystalline silicon film
Ρs can be increased, a large resistance value can be formed in a small area, and the electrostatic withstand voltage can be improved without increasing the pellet size of the small signal vertical MOSFET.
【図１】本発明の第１の実施形態を説明する半導体装置
の平面図。FIG. 1 is a plan view of a semiconductor device illustrating a first embodiment of the present invention.
【図２】図１の半導体装置の断面図。FIG. 2 is a cross-sectional view of the semiconductor device of FIG.
【図３】図１の半導体装置の製造工程を説明する断面
図。FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device of FIG. 1;
【図４】本発明の第２の実施形態の半導体装置の回路
図。FIG. 4 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.
【図５】図３の半導体装置の平面図。FIG. 5 is a plan view of the semiconductor device of FIG. 3;
【図６】図５の半導体装置の断面図。FIG. 6 is a sectional view of the semiconductor device of FIG. 5;
【図７】本発明の第３の実施形態の製造工程を説明する
の半導体装置の断面図。FIG. 7 is a cross-sectional view of a semiconductor device illustrating a manufacturing process according to a third embodiment of the present invention.
【図８】従来例の半導体装置の回路図。FIG. 8 is a circuit diagram of a conventional semiconductor device.
【図９】図８の半導体装置の平面図。FIG. 9 is a plan view of the semiconductor device of FIG. 8;
【図１０】図９の半導体装置の製造工程を説明する断面
図。FIG. 10 is a sectional view illustrating a manufacturing process of the semiconductor device of FIG. 9;
【符号の説明】 １ 半導体チップ ２ 双方向ツェナーダイオード部 ３，４ 抵抗部 ５ 素子部 ６ ゲートパッド部 ７ Ｎ+型半導体基板 ８ Ｎ-エピタキシャル層 ９ Ｐ型ベース領域 １０ Ｐ+型バックゲート １１ Ｎ+型ソース領域 １２ ゲート酸化膜 １３ 多結晶シリコン膜 １４ 層間絶縁膜 １５ ソース電極用配線 １６ ゲート電極用配線 １７ フィールド酸化膜 １８ Ｐウェル領域 １９ Ｐ型領域 ２０ Ｎ型領域 ２１ ポリシリコン抵抗部 ２３ レジスト[Description of Signs] 1 semiconductor chip 2 bidirectional Zener diode section 3, 4 resistance section 5 element section 6 gate pad section 7 N + type semiconductor substrate 8 N − epitaxial layer 9 P type base region 10 P + type back gate 11 N + Type source region 12 gate oxide film 13 polycrystalline silicon film 14 interlayer insulating film 15 source electrode wiring 16 gate electrode wiring 17 field oxide film 18 p-well region 19 p-type region 20 n-type region 21 polysilicon resistance portion 23 resist
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/8234 Ｈ０１Ｌ 27/08 １０２Ｆ 27/088 29/90 Ｄ 29/866 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 21/8234 H01L 27/08 102F 27/088 29/90 D 29/866
Claims (8)
ジスタ素子部に隣接して、その周囲長を長くしこのトラ
ンジスタ素子部のソース電極に一端を接続した保護ダイ
オード部と、この保護ダイオード部の外周に配置され前
記トランジスタ素子部のゲート電極に一端が接続され他
端が前記保護ダイオード部の他端に接続される第１の抵
抗部とが配置されたパターンを有することにより、前記
第１の抵抗部の抵抗値を大きくなるようにしたことを特
徴とする半導体装置。1. A small-signal vertical MOSFET, comprising: a protection diode portion adjacent to a transistor element portion and having a longer perimeter and one end connected to a source electrode of the transistor element portion; A first resistor connected to a gate electrode of the transistor element portion, and a first resistor connected to the other end of the protection diode portion. Wherein the resistance value of the semiconductor device is increased.
イオードからなる請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the protection diode section comprises a bidirectional Zener diode.
ード部の最外周を囲むように配置された請求項２記載の
半導体装置。3. The semiconductor device according to claim 2, wherein the first resistance section is arranged so as to surround the outermost periphery of the bidirectional Zener diode section.
ード部の内周にその抵抗部が長くなるように配置され、
この第２の抵抗部と第１の抵抗部とがそれぞれの一端で
接続された請求項２記載の半導体装置。4. A second resistor section is arranged on the inner periphery of the bidirectional Zener diode section so that the resistor section becomes longer,
3. The semiconductor device according to claim 2, wherein said second resistor and said first resistor are connected at one end.
記トランジスタ素子部のゲート電極の層抵抗値より大き
くなるように形成した請求項１，２，３または４記載の
半導体装置。5. The semiconductor device according to claim 1, wherein the layer resistance of the first or second resistance section is formed to be larger than the layer resistance of the gate electrode of the transistor element section.
ジスタ素子部に隣接して、周囲長を長くした保護ダイオ
ード部と、この保護ダイオード部の外周に配置され前記
トランジスタ素子部のゲート電極と接続される抵抗部と
が配置されたパターンを有する半導体装置の製造方法に
おいて、前記トランジスタ素子部のゲート電極となる多
結晶シリコン膜の層抵抗と前記抵抗部の多結晶シリコン
の層抵抗とを別々の工程により製造して、前記第１の抵
抗部の層抵抗値を前記ゲート電極の層抵抗値より大きく
なるようにしたこと特徴とする半導体装置の製造方法。6. A small-signal vertical MOSFET, which is adjacent to the transistor element section and has a longer perimeter, and is disposed on the outer periphery of the protection diode section and connected to a gate electrode of the transistor element section. In a method of manufacturing a semiconductor device having a pattern in which a resistance portion is disposed, a layer resistance of a polycrystalline silicon film serving as a gate electrode of the transistor element portion and a layer resistance of the polycrystalline silicon of the resistance portion are formed by separate steps. The method of manufacturing a semiconductor device, wherein the manufacturing is performed so that a layer resistance value of the first resistance portion is larger than a layer resistance value of the gate electrode.
シリコン・リン拡散により実施して、抵抗部およびトラ
ンジスタ素子部のゲート電極の各層抵抗値を調整する請
求項６記載の半導体装置の製造方法。7. The manufacturing of a semiconductor device according to claim 6, wherein the layer resistance of the polycrystalline silicon is formed by polycrystalline silicon / phosphorus diffusion to adjust the resistance of each layer of the resistance portion and the gate electrode of the transistor element portion. Method.
リン拡散を実施する際に、抵抗部および保護ダイオード
部がレジストで覆われるようにした請求項６または７記
載の半導体装置の製造方法。8. A polycrystalline silicon for a transistor element portion.
8. The method of manufacturing a semiconductor device according to claim 6, wherein the resistive portion and the protective diode portion are covered with a resist when performing the phosphorus diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001039110A JP2002246598A (en) | 2001-02-15 | 2001-02-15 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001039110A JP2002246598A (en) | 2001-02-15 | 2001-02-15 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002246598A true JP2002246598A (en) | 2002-08-30 |
Family
ID=18901970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001039110A Pending JP2002246598A (en) | 2001-02-15 | 2001-02-15 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002246598A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1469523A1 (en) * | 2003-04-18 | 2004-10-20 | STMicroelectronics S.r.l. | A junction electronic component and an integrated power device incorporating said component |
| JP2006093505A (en) * | 2004-09-27 | 2006-04-06 | Sanyo Electric Co Ltd | Protecting device for mos type element, and semiconductor device |
| US9484444B2 (en) | 2007-05-25 | 2016-11-01 | Mitsubishi Electric Corporation | Semiconductor device with a resistance element in a trench |
| JP2020098884A (en) * | 2018-12-19 | 2020-06-25 | 富士電機株式会社 | Resistance element |
-
2001
- 2001-02-15 JP JP2001039110A patent/JP2002246598A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1469523A1 (en) * | 2003-04-18 | 2004-10-20 | STMicroelectronics S.r.l. | A junction electronic component and an integrated power device incorporating said component |
| US7091559B2 (en) | 2003-04-18 | 2006-08-15 | Stmicroelectronics S.R.L. | Junction electronic component and an integrated power device incorporating said component |
| JP2006093505A (en) * | 2004-09-27 | 2006-04-06 | Sanyo Electric Co Ltd | Protecting device for mos type element, and semiconductor device |
| US9484444B2 (en) | 2007-05-25 | 2016-11-01 | Mitsubishi Electric Corporation | Semiconductor device with a resistance element in a trench |
| JP2020098884A (en) * | 2018-12-19 | 2020-06-25 | 富士電機株式会社 | Resistance element |
| JP7180359B2 (en) | 2018-12-19 | 2022-11-30 | 富士電機株式会社 | resistive element |
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