JP2003296097A - Processing element and processing array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To advance an image signal processing, enhance its speed, and reduce the power consumption by reducing circuit elements of a processing element. <P>SOLUTION: This processing element is provided with a storage circuit having a first register 102 subordinately connecting a plurality of registers 1041-1044 thereto and a shift register 104 connecting the output terminal of the last step register 1044 to the input terminal of the second register 1041, a combination circuit 101 executing a logic arithmetic between one of binary information stored in a plurality of registers constituting the shift register and the binary information inputted from a first input terminal group EXI and outputting the results of the logic arithmetic to the first register 102, a selector circuit 103 connecting the input terminal of an arbitrary register 1041 to either one of the output terminal of the register 1044 of the front step of one register 1041 and an output terminal of the first register 102. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing element and a processing array, and more particularly, to a processing element and processing for parallel processing which simplifies a method of accessing a register from a combinational circuit and reduces related circuit elements. For arrays.

[0002]

2. Description of the Related Art A parallel processing LSI is attracting attention, which performs various information processing in a state where image data collected by a sensor such as a CCD (Charge Coupled Device) is two-dimensionally developed. By directly processing the collected image data in parallel, it is possible to avoid low-speed data transmission between the sensor and the parallel processing LSI, which were conventionally separate components, and to perform faster real-time image processing. It can be carried out.

A parallel processing LSI arranges logic circuits called processing elements in a two-dimensional array and performs parallel arithmetic processing of pixel data sampled by a sensor circuit. In order to improve the accuracy of image processing, it is necessary to arrange the processing elements and the sensor circuits as one unit more densely in a grid pattern to improve the processing resolution.

FIG. 22 shows a circuit configuration of a conventional processing element. Processing element 220
Is a combination circuit 221 and a read selection circuit 222.
A write selection circuit 223 and a register circuit 2240
.About.2243. Register circuit 224
The configuration of 0 to 2243 has a bit width of 1 bit and 4 outputs. Read selection circuit 222 and write selection circuit 22
3 means the combination circuit 221 to the register circuit 224.
Control access to 0-2243. The read selection circuit 222 specifies the register circuits 2240 to 2243 to be selected as the input NI of the combinational circuit 221. The write selection circuit 223 specifies a register that stores the output Y of the combination circuit 221.

FIG. 23 shows a circuit configuration of the read selection circuit. The read selection circuit 222 controls the three-state buffers g1 to g4 using the address signal RA [3-0] designating the register, and the register circuits 2240 to 22.
Select one of 43 to input N of the combinational circuit 221.
Type in I.

FIG. 24 shows the circuit configuration of the write selection circuit. The write selection circuit 223 uses the address signal WA.
[3-0] is used to enable or disable the clock signal applied to the specified registers g5 to g8. Thus, when the clock signal is applied, the output Y of the combinational circuit 221 is stored only in the designated register.

[0007]

Table 1 shows the read selection circuit 222 for the bit width and the number of outputs of the register circuit.
The circuit scale of the write selection circuit 223 and the write selection circuit 223 is shown by the number of transistors. Further, the ratio of the circuit scale of the read selection circuit 222 and the write selection circuit 223 to the circuit scale of the register circuit is also shown.

[0008]

[Table 1]

When the bit width is changed from 1 bit to 8 bits, the ratio of the circuit scale of the read selection circuit 222 and the write selection circuit 223 to the circuit scale of the register circuit is reduced, and the area efficiency of the selection circuit is improved. vice versa,
When the bit width is small, the ratio of the selection circuit increases and the area efficiency decreases, so that there is a problem that it is difficult to downsize the entire processing element in the conventional circuit configuration.

The present invention has been made in view of the above problems, and an object of the present invention is to simplify the method of accessing a register and reduce the circuit elements of the processing element to perform image signal processing. Sophistication of
It is an object of the present invention to provide a processing element and a processing array that achieve high speed and low power consumption.

[0011]

In order to achieve such an object, the present invention provides a first aspect of the present invention that stores a result of the logical operation of a combinational circuit that executes a logical operation. And a shift register in which a plurality of registers for storing binary number information are connected in series and the output terminal of the final stage register is connected to the input terminal of the second register which is the initial stage register. , One of binary number information stored in a plurality of registers constituting the shift register, and 2 input from the first input terminal group.
To the input terminal of any one of a plurality of registers forming the shift register and the combinational circuit for performing a logical operation with the decimal information and outputting the result of the logical operation to the first register. , A selector circuit for selecting and connecting any one of the output terminal of the register in the preceding stage of the first register and the output terminal of the first register.

According to this structure, a shift register is configured as a memory circuit, and when the combination circuit accesses the shift register, the access operation is shifted by performing only through a specific register in the shift register. By expanding the register shift operation on the time axis, the fixed circuit elements required for access can be reduced.

According to a second aspect of the present invention, the combinational circuit according to the first aspect inputs the binary number information stored in the first register and further executes a logical operation. To do.

According to a third aspect of the present invention, there is provided a processing array in which units each having the processing element according to the first or second aspect and a sensor circuit for outputting image data are arranged in a grid pattern. The combination circuit of (1) inputs the image data and the output of the first register of the processing element of the adjacent unit to the first input terminal group.

In a fourth aspect of the present invention, a plurality of registers for storing binary number information are connected in cascade, and an output terminal of a final stage register is connected to an input terminal of a second register which is a first stage register. A storage circuit having a shift register and a first register for storing binary number information stored in the final stage register; and an input terminal of any one of a plurality of registers forming the shift register. A selector circuit for selecting and connecting any one of the output terminal of the register preceding the one register and the output terminal of the combinational circuit; and binary number information stored in the first register, The combination circuit for executing a logical operation with binary number information input from the first input terminal group and outputting the result of the logical operation to the selector circuit.

According to this structure, the shift register is configured as the storage circuit, and when the combinational circuit accesses the shift register, the access operation is shifted by performing only through a specific register in the shift register. By expanding the register shift operation on the time axis, the fixed circuit elements required for access can be reduced.

According to a fifth aspect of the present invention, the combinational circuit according to the fourth aspect inputs binary number information stored in the register at the final stage, and further executes a logical operation. To do.

According to a sixth aspect of the present invention, there is provided a processing array in which units each having the processing element according to the fourth or fifth aspect and a sensor circuit for outputting image data are arranged in a grid pattern. The combination circuit of (1) inputs the image data and the output of the register at the final stage of the processing element of the adjacent unit to the first input terminal group.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIG. 1 shows a circuit configuration of a processing element according to a first embodiment of the present invention. The processing element 100 includes a combinational circuit 101 that executes a logical operation, a 1-bit register 102 that stores a logical operation result, and a 2-1 selector circuit 103.
1-bit register 10 that constitutes the shift register 104
41 to 1044. In the present embodiment, the bit width of the register circuit is 1 bit and the number of outputs is 5. However, the present invention is not limited to this.

The combinational circuit 101 includes a multi-bit input signal EXI externally applied from the first input terminal group.
And 1-bit binary number information stored in the 1-bit register 1044 are input, and a logical operation is executed. Output Y
Is output to and stored in the 1-bit register 102.
The type of logical operation to be executed is specified by the control signal CTR. The 1-bit register 102 is an edge-triggered D flip-flop, and has a first write signal PC.
Data is stored on the rising edge of K. The stored data is output to the outside as an output signal EXO.

The input terminal of the 2-1 selector circuit 103 has a 1-bit register 102 and a 1-bit register 104.
4 output terminals are connected, and one of the inputs is selected by the selection signal WR and connected to the input terminal of the 1-bit register 1041. The 1-bit registers 1041 to 1044 are
The shift register 104 is an edge trigger type D flip-flop. 1-bit register 1041
1044 are serially connected in series, and the output terminal of the 1-bit register 1044 is connected to one input terminal of the 2-1 selector circuit 103. The output terminal of the 1-bit register 1044 is the combinational circuit 101.
Is also connected to the input NI of. In the present embodiment, the 2-1 selector circuit 103 is connected to the input terminal of the 1-bit register 1041.
4 may be connected to any of the input terminals.

When the selection signal WR of the 2-1 selector circuit 103 is "0", the shift register 104 closes the shift operation loop with the 1-bit registers 1041 to 1044. At the rising edge of the second write signal RCK,
The binary number information stored in the 1-bit registers 1041 to 1044 is sequentially transferred. When the selection signal WR is “1”, the loop is opened between the 1-bit register 1041 and the 1-bit register 1044, and the 1-bit register 1
The data from 02 is input to the 1-bit register 1041.

Next, a basic operation sequence of the processing element 100 will be described. here,
The 1-bit binary information "d1" stored in the 1-bit register 1042 is logically operated on the input signal EXI, and the operation result "res0" is overwritten on the data "d0" stored in the 1-bit register 1041. The sequence is roughly divided into three steps.

FIG. 2 shows the initial state of the processing element. In the initial state, the 1-bit register 10
41 to 1044 include binary information “d0”, “d1”,
"D2" and "d3" are stored respectively, and the 1-bit register 102 stores arbitrary data.

FIG. 3 shows the designation of the read register which is the first step. The operation of the combinational circuit 101 reading the 1-bit binary number information “d1” stored in the 1-bit register 1042 will be described. FIG. 3 shows data stored in each register at the time when the read operation is completed. The input NI of the combinational circuit 101 is
Only the output terminal of the 1-bit register 1044 is connected. "D1" stored in the 1-bit register 1042
To shift to 1-bit register 1044,
The rising pulse is applied to the second write signal RCK twice in succession.

FIG. 4 shows the second step of executing a logical operation and storing the execution result in a register. The output Y of the combinational circuit 101 is stored in the 1-bit register 102. Binary number information “d” is stored in the 1-bit register 1044.
1 "is stored, the control signal CTR is set so that the combinational circuit 101 executes a predetermined logical operation, and the first write signal PCK is raised. As a result, the operation result" res0 "is registered in the 1-bit register. It stores in 102.

FIG. 5 shows the third step, which is the designation and storage of the write register. 1-bit register 102
The operation result “res0” stored in the above is overwritten on the binary number information “d0” stored in the shift register 104. The selection signal WR of the 2-1 selector circuit 103 is set to "0".
Then, the binary information “d0” is shifted to the 1-bit register 1044 by continuously applying the pulse to the second write signal RCK twice. Select signal WR is "1"
Then, a pulse is applied once to the second write signal RCK, and the operation result “res” is stored in the storage position of the binary number information “d0”.
0 "is overwritten.

FIG. 6 shows an operation sequence of the processing element according to the first embodiment of the present invention. The processing element 100 is connected to the selection signal WR of the 2-1 selector circuit 103 and the first write signal PCK.
And a control signal CTR for designating a logical operation and a second write signal RCK. The time section separated by the dotted line represents a half cycle of the operation cycle. In the first two cycles, the register with the data to perform the logical operation is specified. In the next one cycle, the execution result of the logical operation is stored in the 1-bit register 102. In the next one cycle, the binary number information stored in the register in which the operation result is to be written is shifted to a predetermined register, and in the next two cycles, the operation result is overwritten in the designated register.

According to this embodiment, the 1-bit register 1
The shift register 104 is composed of 041 to 1044, and when the combinational circuit 101 accesses the shift register 104, it is performed only through a specific 1-bit register. In this way, by expanding the access operation on the time axis of the shift operation in the shift register 104, it is not necessary to add a read circuit and a write circuit to each 1-bit register, and the circuit element Can significantly reduce the scale of.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
2 shows a circuit configuration of a processing element according to the embodiment. The processing element 700 includes a combinational circuit 701 that executes a logical operation, a 1-bit register 102 that stores a logical operation result, a 2-1 selector circuit 103, and 1-bit registers 1041 to 1044 that form a shift register 104. Has been done. The second embodiment is a modification of the combination circuit of the first embodiment, in which the output of the 1-bit register 102 is the input NRI of the combination circuit 701. In this embodiment, a logical operation can be performed between the 1-bit register 102 and the 1-bit register 1044. Such an arithmetic mechanism is particularly useful when performing a logical operation with the contents of a plurality of registers as inputs.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
2 shows a circuit configuration of a processing element according to the embodiment. The processing element 800 includes a combinational circuit 101 that executes a logical operation, a 1-bit register 102 that stores a logical operation result, a 2-1 selector circuit 103, and 1-bit registers 1041 to 1044 that form a shift register 104. Has been done. The third embodiment is a modification of the connection of each circuit element in the first embodiment.

The combinational circuit 101 includes a multi-bit input signal EXI externally applied from the first input terminal group.
And the 1-bit 2 stored in the 1-bit register 102
Input the decimal number information and execute the logical operation. Output Y is
It is output to one of the input terminals of the 2-1 selector circuit 103. The type of logical operation to be executed is specified by the control signal CTR. The 1-bit register 102 is an edge-trigger type D flip-flop and stores data at the rising edge of the first write signal PCK.

The output Y of the combinational circuit 101 and the output terminal of the 1-bit register 1044 are connected to the input terminal of the 2-1 selector circuit 103, and one of the inputs is selected by the selection signal WR to the 1-bit register 1041. Output. The 1-bit registers 1041 to 1044 are edge-trigger type D flip-flops and configure the shift register 104. 1-bit registers 1041 to 1
Each of 044 is sequentially connected in series, and the output terminal of the 1-bit register 1044 is connected to one input terminal of the 2-1 selector circuit 103. The data stored in the 1-bit register 1044 is output as the output signal EXO and is also connected to the input terminal of the 1-bit register 102.

When the selection signal WR of the 2-1 selector circuit 103 is "0", the shift register 104 closes the shift operation loop with the 1-bit registers 1041 to 1044. At the rising edge of the second write signal RCK,
The binary number information stored in the 1-bit registers 1041 to 1044 is sequentially transferred. When the selection signal WR is “1”, the loop is opened between the 1-bit register 1041 and the 1-bit register 1044, and the combinational circuit 10
The data from the output Y of 1 is input to the 1-bit register 1041.

Next, a basic operation sequence of the processing element 800 will be described. here,
The 1-bit binary information "d1" stored in the 1-bit register 1042 is logically operated on the input signal EXI, and the operation result "res0" is overwritten on the data "d0" stored in the 1-bit register 1041. The sequence is roughly divided into three steps.

FIG. 9 shows the initial state of the processing element. In the initial state, the 1-bit register 10
41 to 1044 include binary information “d0”, “d1”,
"D2" and "d3" are stored respectively, and the 1-bit register 102 stores arbitrary data.

FIG. 10 shows designation of the read register which is the first step. The operation of transferring the 1-bit binary number information “d1” stored in the 1-bit register 1042 to the 1-bit register 102 will be described. FIG. 10 shows 2
It indicates the time when the decimal information “d1” is transferred to the 1-bit register 1044. FIG. 11 shows the first step, that is, the storage of data in the designated read register. The time when the binary information “d1” is stored in the 1-bit register 102 is shown. Only the output terminal of the 1-bit register 102 is connected to the input NI of the combinational circuit 101.

In order to shift "d1" stored in the 1-bit register 1042 to the 1-bit register 1044, the selection signal WR of the 2-1 selector circuit 103 is set to "0" and rises to the second write signal RCK. The pulse is applied twice in succession. Next, the 1-bit register 10
“D1” stored in 44 is stored in the 1-bit register 102.
In order to transfer to the first write signal PCK, the rising pulse is applied once.

FIG. 12 shows the second step of executing a logical operation and storing the execution result in a register. The output Y of the combinational circuit 101 is set to the 1-bit register 1041.
The binary number data "d0" stored in is overwritten. Figure 1
Reference numeral 2 indicates the time when the data “d0” to be overwritten is transferred to the 1-bit register 1044. By setting the selection signal WR of the 2-1 selector circuit 103 to “0” and applying a pulse once to the second write signal RCK,
The base number information “d0” is shifted to the 1-bit register 1044.

FIG. 13 shows the third step of storing the write register. The selection signal WR of the 2-1 selector circuit 103 is set to "1", a pulse is applied once to the second write signal RCK, and the operation result "res0" is overwritten in the storage position of the data "d0".

FIG. 14 shows an operation sequence of the processing element according to the third embodiment of the present invention.
The processing element 800 is connected to the selection signal WR of the 2-1 selector circuit 103 and the second write signal RCK.
And a control signal CTR designating a logical operation and a first write signal PCK. The time section separated by the dotted line represents a half cycle of the operation cycle. In the first two cycles, the register with the data to perform the logical operation is specified. In the next one cycle, the data to be executed is stored in the 1-bit register 102. In the next 1 cycle, the binary number information stored in the register in which the operation result is to be written is shifted to a predetermined register, and the next 2
In the cycle, the operation result is overwritten on the specified register.

According to this embodiment, the 1-bit register 1
When the shift register 104 is configured by 041 to 1044, and the combinational circuit 101 accesses the shift register 104, the data in the register to be accessed is transferred to a specific register, and only through the specific register. I decided to do it. In this way, by expanding the access operation on the time axis of the shift operation in the shift register 104, it is not necessary to add a read circuit and a write circuit to each 1-bit register, and the circuit element Can significantly reduce the scale of.

(Fourth Embodiment) FIG. 15 shows a circuit configuration of a processing element according to a fourth embodiment of the present invention. The processing element 150 includes a combinational circuit 701 that executes a logical operation, a 1-bit register 102 that stores a logical operation result, a 2-1 selector circuit 103, and 1-bit registers 1041 to 1044 that form a shift register 104. Has been done.
The fourth embodiment is a modification of the combination circuit of the third embodiment, in which the output of the 1-bit register 1044 is the input NRI of the combination circuit 701. In this embodiment, the 1-bit registers 102 and 1
A logical operation can be performed with the bit register 1044. Such an arithmetic mechanism is particularly useful when performing a logical operation with the contents of a plurality of registers as inputs.

(Fifth Embodiment) FIG. 16 shows the arrangement of a processing array according to the fifth embodiment of the present invention. 1 shows a processing array in which the processing elements and sensor circuits of the first embodiment or the second embodiment are arranged in a lattice as one unit. The controller circuit outside the processing array supplies the common control signal CTR, the first write signal PCK, the selection signal WR, and the second write signal RCK to the individual processing elements.

FIG. 17 shows inputs and outputs of processing elements and sensor circuits in the processing array. The processing elements mutually communicate binary information between the left, right, upper and lower processing elements. The sensor circuit digitizes the two-dimensionally distributed analog information and outputs it as binary information to the processing element. The control signal CTR for controlling the processing element, the first write signal PCK, the selection signal WR, and the second write signal RCK are commonly supplied to all the processing elements.

FIG. 18 shows a circuit configuration of a processing element according to the fifth embodiment of the present invention. FIG.
18 shows the processing elements used in the processing array shown in FIGS. The circuit configuration of the processing element is the same as that of the first or second embodiment, and the terminal name of each circuit element is changed. As the input signal EXI of the combinational circuit 101, the output signals of the adjacent processing elements are input signals Ei, Wi, S.
Input as i and Ni. Also, the input signal EXI
The output signal S from the sensor circuit is also input. Output signal EX
O is output as an output signal Po to the adjacent processing element.

In this way, by using the above-mentioned processing element, a high-density processing array can be realized, and a higher processing resolution can be realized in the application field of image processing.

(Sixth Embodiment) FIG. 19 shows the arrangement of a processing array according to the sixth embodiment of the present invention. 7 shows a processing array in which the processing elements and the sensor circuits of the third or fourth embodiment are arranged in a lattice as one unit. The controller circuit outside the processing array supplies the common control signal CTR, the first write signal PCK, the selection signal WR, and the second write signal RCK to the individual processing elements.

FIG. 20 shows inputs and outputs of processing elements and sensor circuits in the processing array. The processing elements mutually communicate binary information between the left, right, upper and lower processing elements. The sensor circuit digitizes the two-dimensionally distributed analog information and outputs it as binary information to the processing element. The control signal CTR for controlling the processing element, the first write signal PCK, the selection signal WR, and the second write signal RCK are commonly supplied to all the processing elements.

FIG. 21 shows a circuit configuration of a processing element according to the sixth embodiment of the present invention. FIG. 19
21 shows processing elements used in the processing array shown in FIGS. The circuit configuration of the processing element is the same as that of the third or fourth embodiment, and the terminal name of each circuit element is changed. As the input signal EXI of the combinational circuit 101, the output signals of the adjacent processing elements are input signals Ei, Wi, S.
Input as i and Ni. Also, the input signal EXI
The output signal S from the sensor circuit is also input. Output signal EX
O is output as an output signal Po to the adjacent processing element.

As described above, by using the above-mentioned processing element, a high-density processing array can be realized, and a higher processing resolution can be realized in the application field of image processing.

[0052]

As described above, according to the present invention,
By simplifying the register access method, reducing the circuit elements of the processing element, and increasing the density of the processing array, it is possible to improve the image signal processing, speed up the processing element, and reduce power consumption. Become.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a processing element according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an initial state of the processing element according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining designation of a read register which is a first step.

FIG. 4 is a diagram for explaining execution of a logical operation and storage of an execution result in a register, which is a second step.

FIG. 5 is a diagram for explaining designation and storage of a write register which is a third step.

FIG. 6 is a timing chart showing an operation sequence of the processing element according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a processing element according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a processing element according to a third exemplary embodiment of the present invention.

FIG. 9 is a diagram illustrating an initial state of a processing element according to a third exemplary embodiment of the present invention.

FIG. 10 is a diagram for explaining designation of a read register which is a first step.

FIG. 11 is a diagram for explaining storage of data in a designated read register, which is the first step.

FIG. 12 is a diagram for explaining execution of a logical operation and storage of an execution result in a register, which is a second step.

FIG. 13 is a diagram for explaining storage of a write register which is a third step.

FIG. 14 is a timing chart showing an operation sequence of the processing element according to the third embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a processing element according to a fourth embodiment of the present invention.

FIG. 16 is a configuration diagram showing an arrangement of processing arrays according to a fifth embodiment of the present invention.

FIG. 17 is a schematic diagram showing inputs / outputs of a processing element and a sensor circuit in the processing array according to the fifth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of a processing element according to a fifth embodiment of the present invention.

FIG. 19 is a configuration diagram showing an arrangement of processing arrays according to a sixth embodiment of the present invention.

FIG. 20 is a schematic diagram showing inputs and outputs of a processing element and a sensor circuit in the processing array according to the sixth embodiment of the present invention.

FIG. 21 is a circuit diagram showing a configuration of a processing element according to a sixth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a configuration of a conventional processing element.

FIG. 23 is a circuit diagram showing a configuration of a read selection circuit of a processing element.

FIG. 24 is a circuit diagram showing a configuration of a write selection circuit of a processing element.

[Description of Reference Signs] 100, 150, 220, 700, 800 Processing elements 101, 221, 701 Combination circuit 102, 1041 to 1044 1-bit register 103 2-1 selector circuit 104 Shift register 222 Read selection circuit 223 Write selection circuit 2240 to 2243 register circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B013 DD04                 5B022 CA02 DA02                 5B045 AA01 GG12                 5B057 CA12 CA16 CH03 CH04 CH08                       CH18                 5J042 BA19 CA00 CA13 CA15 DA01                       DA02 DA03

Claims (6)

[Claims] 1. A first register for storing a result of the logical operation of a combinational circuit for executing a logical operation and a plurality of registers for storing binary number information are cascade-connected, and an output terminal of a register at a final stage is connected. A memory circuit having a shift register connected to an input terminal of a second register which is a first-stage register, one of binary number information stored in a plurality of registers constituting the shift register, and a first input A combination circuit that executes a logical operation with binary number information input from a terminal group and outputs the result of the logical operation to the first register; and a plurality of registers that configure the shift register,
An input terminal of an arbitrary one register is provided with an output terminal of a register in a preceding stage of the one register and a selector circuit for selecting and connecting any one of the output terminals of the first register. Characterizing processing element. 2. The processing element according to claim 1, wherein the combination circuit inputs binary number information stored in the first register and further executes a logical operation. 3. A processing array in which units each having the processing element according to claim 1 or 2 and a sensor circuit for outputting image data are arranged in a grid pattern, wherein the combinational circuit of the processing elements comprises: The image data and the output of the first register of the processing element of the adjacent unit
A processing array that inputs to a group of input terminals. 4. A shift register in which a plurality of registers for storing binary number information are connected in cascade, and an output terminal of a register at the final stage is connected to an input terminal of a second register which is a register at the first stage, and the final stage. A memory circuit having a first register for storing binary number information stored in the register, and among the plurality of registers constituting the shift register,
A selector circuit for selecting and connecting any one of the output terminal of the register in the preceding stage of the one register and the output terminal of the combinational circuit to the input terminal of the arbitrary one register, and the first register A combination circuit for executing a logical operation between the stored binary number information and the binary number information input from the first input terminal group and outputting the result of the logical operation to the selector circuit. Processing element to be. 5. The processing element according to claim 4, wherein the combinational circuit inputs the binary number information stored in the final stage register and further executes a logical operation. 6. A processing array in which units each having a processing element according to claim 4 or 5 and a sensor circuit for outputting image data are arranged in a grid pattern, wherein the combinational circuit of the processing elements comprises: A processing array, wherein image data and an output of a final stage register of a processing element of an adjacent unit are input to the first input terminal group.