JP2005175614A - Frame synchronizer and optical transmitter/receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a frame synchronizer exhibiting excellent reliability by preventing erroneous synchronization in a communication system where the receiving time of a signal requiring synchronization processing is not constant. <P>SOLUTION: The frame synchronizer comprises a timer 11 being initialized by receiving a period signal A, a timing generation circuit 13 for generating/outputting a gate signal A indicating whether the period signal A is passed or not based on the timer value A of the timer 11, a gate circuit 15 for passing or blocking the period signal A based on the gate signal A, a timer 12 being initialized by receiving a period signal B passed through the gate circuit 15, a timing generation circuit 14 for generating/outputting a gate signal B indicating whether the period signal B is passed or not and a reproduction period signal being used when the period signal is missed based on the timer value B of the timer 12, and a gate circuit 16 for passing or blocking the period signal B based on the gate signal B. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a frame synchronizer and an optical transceiver equipped with the frame synchronizer.

  In recent years, optical interfaces used in local area networks (LANs) have become increasingly compatible with higher signal speeds and longer transmission distances, and there are differences from optical interfaces used in wide area networks (WANs). It is narrowing.

  This is a typical transmission standard for public networks and WANs. In an SDH (Synchronous Digital Hierarchy) multiplexed transmission system in which a fixed-length frame accommodates client data, the head portion in which a fixed length frame accommodates client data is managed in an SDH (Synchronous Digital Hierarchy) multiplexed transmission system specified in G707 “Network node interface for the synchronous digital hierarchy” By using the overhead part, abundant network monitoring functions such as alarm forwarding and error monitoring can be realized. Furthermore, in SDH, network-synchronized serial data is composed of repeated 125 microsecond frames, so that the overhead portion is processed for each frame, thereby enabling periodic management and maintenance with a simple device.

  In packet over SONET (POS) and 10-gigabit WAN-PHY (physical layer) SDH packet data mapping and transmission, SDH is applied to the physical layer protocol, and the overhead part is used as it is. The MAC layer and the IP packet are mapped to the payload portion and transmitted on a transmission medium such as an optical fiber to provide physical layer maintenance management information.

  In SDH, the overhead portion is divided into regenerative relay sections, multiple relay sections, and areas corresponding to the hierarchies of paths and multiplexing, and the SDH devices constituting the transmission path perform termination and relay processing for each overhead hierarchy. This enables hierarchical management of transmission paths. At this time, in SDH, termination processing is periodically performed with a fixed-length frame period.

  Since SDH processes maintenance management information at a fixed cycle as described above, for example, a DCC byte group is allocated to the overhead portion of a data communication channel (DCC) for a system administrator to perform data communication. It is done. When DCC data is output from the SDH device to the system, after receiving the DCC byte, it is output in parallel with the clock obtained by dividing the recovered clock from the received data stream. Can be output.

  Furthermore, in SDH, it is possible to communicate APS (Automatic Protection Switching), which is a protocol for maintenance switching of a transmission path in the event of a failure, using the overhead K1 and K2 bytes as a maintenance function, and the fault tolerance of the network , Improving recovery ability.

  In addition, one of the important functions of network management is that the downstream node of the transmission path where failure or signal degradation has occurred detects it, and at the same time, returns the number of code errors and failure information to the upstream node as remote reception failure information. There is a function for notifying that the transmission path is unusable due to a failure. In SDH, since the devices on both transmission and reception transmission paths are synchronized, the failure information updated for each frame by the received signal can be returned to the opposite node without excess or deficiency.

  In contrast, in transmission standards such as Ethernet (registered trademark) that transmit variable-length frames or fixed-length frames intermittently, the client device occupies the transmission band at random, so the network device affects the client data. Therefore, it is difficult to perform periodic management control communication.

  For example, in LAN-PHY, which is a genuine standard of 10 Gbit Ethernet (registered trademark), an extended function for network management maintenance called LSS (Link Signaling Sublayer) has been proposed in IEEE 802.3ae. In LSS, a packet indicating a management signal is inserted and transmitted in an idle code portion indicating a free band of a data stream in which intermittent client data flows. In addition, by periodically transmitting a packet called LSb (Link Signaling Base) indicating a frame delimiter and putting another management signal in a section delimited by LSb, periodic processing for each frame such as SDH is enabled. .

  Further, in LSS, an idle code portion in which client data is not used is replaced with a packet called an LSS ordered set for communication, so that the transmission band does not compete with client data. Furthermore, since LSS packets do not necessarily have to be terminated at Layer 1 and Layer 0 devices, they can be transmitted through these devices and are suitable for network layer management by Ethernet (registered trademark). Yes.

  In the conventional periodic timing generator disclosed in Patent Document 1, the range of possible values of the time difference (ti−t0) between the input time ti of the reception period timing of the period Ti and the output time t0 of the reproduction period timing of the period T0. Are divided into a plurality of areas, and the correction value of the reproduction cycle timing is set for each of the plurality of areas. Then, when reproducing the input reception period timing of the period Ti and outputting it as the reproduction period timing of the period T0, an area including the value of the time difference (ti−t0) is specified, and the specified area is The playback cycle timing is corrected according to the set correction value.

  By applying the periodic timing generation device described in Patent Document 1 to a communication device that requires reproduction of a periodic signal, even if a management signal is lost on a transmission line, the communication device that performs reception or relaying The signal can be reproduced and the new reception cycle can be followed even when there is a phase variation in the reception timing of the periodic signal. For example, by applying this apparatus to a communication apparatus having the above-described LSS function, periodic frame processing can be performed without taking a fixed frame configuration such as SONET / SDH.

JP 2001-358580 A

  In the conventional periodic timing generator disclosed in Patent Document 1, when a reception signal enters a zone in which a dead zone or circuit protection is applied, a counter for synchronizing with the reception signal is not reset. For this reason, when the reception cycle timing is shifted to this section due to the phase fluctuation, there is a problem that it is not possible to determine whether or not the arrival of the periodic signal has a fluctuation exceeding the allowable range. For example, when a periodic signal is received in a section provided with a protection circuit, if the time width of this section is set to be larger than the allowable width of fluctuation of the arrival time of the received signal, even if the reception interval exceeds the allowable width When the protection circuit receives a periodic signal corresponding to the number of protection stages, erroneous synchronization is performed.

  The present invention has been made in order to solve the above-described problems. In a communication system in which the reception time of a signal that requires synchronization processing is not constant, a frame synchronization apparatus that prevents erroneous synchronization and has excellent reliability is obtained. For the purpose.

  Another object of the present invention is to obtain an optical transceiver suitable for processing a maintenance management information signal using such a synchronization device.

  The frame synchronizer according to the present invention includes a first timer that is initialized by receiving an input of a periodic signal, and a first gate signal that indicates whether the periodic signal is passed based on the first timer value. A first timing generation circuit that generates and outputs; a first gate circuit that passes or stops the periodic signal based on the first gate signal; and an input of the periodic signal that has passed through the first gate circuit. And the second timer signal indicating whether or not the periodic signal that has passed through the first gate circuit is allowed to pass based on the second timer value initialized and the second timer value is lost. A second timing generation circuit that generates and outputs a reproduction periodic signal used sometimes, and a second gate circuit that passes or stops the periodic signal that has passed through the first gate circuit based on the second gate signal What we have A.

  An optical transceiver according to the present invention includes an optical / electrical converter that converts a received optical signal into a received electrical signal, a reception-side main signal input processing unit that regenerates a received data sequence from the received electrical signal, and a received data sequence A reception unit having a reception side main signal output processing unit for generating an output electric signal, a transmission side main signal input processing unit for reproducing a transmission data string from the inputted electric signal, and a transmission electric signal from the transmission data string In an optical transceiver including a transmission-side main signal output processing unit and a transmission unit having an electrical / optical converter that converts a transmission electrical signal into a transmission optical signal, the reception unit extracts a control signal from the received data string Receiving side control signal separation circuit that determines the type of control signal, receives side code identification circuit that distributes and outputs to the periodic signal and other control signals, and receives the periodic signal for frame synchronization processing A reception side frame synchronization unit that generates and outputs a frame update signal and a reproduction cycle signal, a reception side termination circuit that receives and terminates other control signals and frame update signals, and other control signals and frame update signals A receiving side relay circuit that receives and encodes the relay control signal and the reproduction period signal, encodes and outputs an encoding control signal, and an encoding control signal. A reception-side control signal insertion circuit periodically inserted in the reception data sequence, and the transmission unit extracts a control signal from the transmission data sequence and outputs it, and a type of control signal A transmission side code identification circuit that distributes and outputs the periodic signal and other control signals, receives the periodic signal, performs frame synchronization processing, and performs a frame update signal and re-transmission. Transmission side frame synchronizer that generates and outputs periodic signals, transmission side relay circuit that receives other control signals and frame update signals and outputs relay control signals, and transmissions that generate generation control signals including failure information Side generation circuit, a transmission side encoding circuit that receives and encodes the relay control signal, the reproduction cycle signal, and the generation control signal, and outputs the encoding control signal, and the encoding control signal code in the transmission data string A transmission-side control signal insertion circuit that is periodically inserted is provided.

  According to the present invention, the first timer is always synchronized with the input timing of the input periodic signal, and the second timer that controls the processing timing in the communication apparatus to generate the output timing is input to the second timer. It is not synchronized with the temporary phase fluctuation of the periodic signal, but the processing timing and the generation timing of the reproduction periodic signal are given based on the previous reception period held internally, so it is correct in synchronization with the reception period of the input periodic signal. Processing timing can be generated, and erroneous synchronization with the phase fluctuation of the temporary input periodic signal can be prevented, thereby improving the reliability of the synchronization device.

  According to the present invention, there is an effect that an optical transceiver capable of managing and monitoring a transmission path without affecting a host switching apparatus can be obtained.

Hereinafter, various embodiments of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a frame synchronization apparatus 10 according to Embodiment 1 of the present invention.
As shown in the figure, the frame synchronization apparatus 10 includes a timer (first timer) 11, a timer (second timer) 12, a timing generation circuit (first timing generation circuit) 13, a timing generation circuit (second timer). A timing generation circuit 14, a gate circuit (first gate circuit) 15, and a gate circuit (second gate circuit) 16 are provided.

  The frame synchronization device 10 is a device that generates a signal for determining processing timing within the communication device, and outputs a periodic signal C that is a processing timing signal based on a periodic signal A received from the outside.

  The periodic signal A received by the frame synchronization apparatus 10 is input to the timer 11 and the gate circuit 15. When the timer 11 receives the input of the periodic signal A, the timer 11 resets the timer value A to zero. Similarly, when the timer 12 receives the input of the periodic signal B, the timer 12 resets the timer value B to zero. When the timer 11 and the timer 12 reach a preset period (hereinafter referred to as a self-reset time), the timer value is automatically reset to 0 and the count-up is restarted from 0.

  The timing generation circuit 13 monitors the timer value A indicated by the timer 11, generates a gate signal A, and outputs it to the gate circuit 15. Based on the gate signal A, the gate circuit 15 performs an operation of passing / stopping the input periodic signal A. The periodic signal A that has passed through the gate circuit 15 is referred to as a periodic signal B.

  The timing generation circuit 14 monitors the timer value B indicated by the timer 12, generates the gate signal B and outputs it to the gate circuit 16, and outputs the reproduction cycle signal. Based on the gate signal B, the gate circuit 16 performs an operation of passing / stopping the input periodic signal B. The periodic signal B that has passed through the gate circuit 16 becomes a periodic signal C.

Next, detailed operation of the frame synchronization apparatus 10 will be described.
FIG. 2 is a timing chart for explaining the operation of the frame synchronization apparatus 10.
Here, the self-reset time of the timer 11 and the timer 12 is (T ₀ −1), and the timer value when the periodic signal A is input is indicated by Ti. Between time 0 and time T ₀ , two time zones, TA and TB, are set. TA is a time zone from time 0 to time M, or time (N + 1) to time (T ₀ −1), and TB is a time zone from time (M + 1) to time N.

  When the monitored timer value A is included in the time zone TA, the timing generation circuit 13 outputs a gate signal A that permits passage of the periodic signal A to the gate circuit 15. When the timer value A is included in the time zone TB, the gate signal A that does not permit the passage of the periodic signal A is output. That is, while the timer value A is included in the time zone TA, the gate circuit 15 passes the input periodic signal A and the periodic signal B is output. While the timer value A is included in the time zone TB, the gate circuit 15 discards the periodic signal A even if it is received.

Similarly, when the timer value B is included in the time zone TA, the timing generation circuit 14 outputs a gate signal B that permits passage of the periodic signal B to the gate circuit 16. When the timer value B is included in the time zone TB, the gate signal B that does not permit the passage of the periodic signal B is output. That is, while the timer value B is included in the time zone TA, the gate circuit 16 passes the input periodic signal B and the periodic signal C is output. While the timer value B is included in the time zone TB, the gate circuit 16 discards the periodic signal B even if it is received.
In addition, the timing generation circuit 14 outputs a reproduction periodic signal when the timer value B indicates M in order to reproduce the periodic signal when the periodic signal disappears.

  The timing chart of FIG. 2 starts from a state in which the timer value A of the timer 11 and the timer value B of the timer 12 are included in the time zone TA. At this time, the timing generation circuit 13 and the timing generation circuit 14 are gate circuits. 15 and the gate circuit 16 output a gate signal for passing the periodic signal. At the time indicated by S21 in the figure, the timer value A and the timer value B become M, and the time zone TB is entered from M + 1. At this time, the gate signal A and the gate signal B are changed to signals that do not pass the periodic signal.

  Further, the timer value A and the timer value B become N, and the time zone TA is entered again from N + 1. At this time, the gate signal A and the gate signal B are changed to a passage permission signal (S22).

Then, the timer value A is when _{T i,} the period signal A is input (S23). At this time, the timer 11 receives the input of the periodic signal A, and the timer value A is reset to zero. Here, if T _i is included in the time zone TA, the timing generation circuit 13 outputs a gate signal A that permits passage of the periodic signal A. The gate circuit 15 receives the gate signal A, passes the periodic signal A, and outputs the periodic signal B.

When the timer 12 receives the periodic signal B output in S23, the timer value B is reset to zero. Also, if T _i is long is included in the time zone TA, the timing generation circuit 14 also outputs a gate signal B to allow passage of the periodic signal B, the gate circuit 16 passes the periodic signals B, A periodic signal C is output.

  Further, when the timer value B becomes M, the timing generation circuit 14 outputs a reproduction cycle signal (S24).

  Next, in S25, the phase variation of the periodic signal A occurs, and the periodic signal A is input when the timer value A is included in the time zone TB. At this time, the timer value A is reset to 0 and synchronized with a new reception cycle. However, at this time, since the timing generation circuit 13 outputs the gate signal A that is not permitted to pass the periodic signal A, the gate circuit 15 does not pass the periodic signal A. For this reason, the periodic signal B is not input to the timer 12, and the timer value B is not reset. Further, the periodic signal C is not output.

When the timer value B reaches T ₀ −1, the timer 12 performs self-reset (S26). That is, at this time, the period of the periodic signal A given in S23 is held. The generation timing of the reproduction cycle signal is similarly held.

When a new reception period of the periodic signal A is maintained, the timer 11 and the gate circuit 15, the periodic signal A is input at time T _i that is included in the time zone TA (S27). At this time, since the gate signal A indicates permission to pass the signal, the gate circuit 15 passes the periodic signal A. The timer 12 receives the periodic signal B, resets the timer value B, and synchronizes with a new reception period. At this time, since the timer value B is included in the time zone TB, the gate signal B indicates that the passage of the periodic signal B is not permitted, and the periodic signal C is not output.

Further, when the periodic signal A is next input, the timer 12 is synchronized with the new periodic signal reception timing, so that the timer value B when the periodic signal B is input is included in the time zone TA, and the timing generation is performed. The circuit 14 outputs a gate signal B that permits passage of the periodic signal B. Therefore, the gate circuit 16 passes the periodic signal B, and the periodic signal C is output.
At this time, the reproduction cycle signal is also synchronized with the new reception timing (S28).

  As described above, the periodic signal A is directly input to the timer 11 as a reset signal, and the timer 11 is constantly synchronized with the input periodic signal A. On the other hand, the timer 12 is synchronized with the periodic signal B that has passed through the gate circuit 15 and is reflected in the periodic signal C that is a frame update signal for correcting the frame delimiter position and the reproduction periodic signal.

  FIG. 3 is a timing chart for explaining the operation of the frame synchronization apparatus 10 when the fluctuation of the reception cycle of the periodic signal A is not stable. The setting of the self-reset time of the timers 11 and 12 and the time zones TA and TB are the same as in FIG.

  In S31, the periodic signal A is received when the timer value A and the timer value B are both included in the time zone TA, and the periodic signal C is output. When the periodic signal A in which the phase variation occurs in S32 is received, the timer value A is reset as in S25 of FIG. 2, but the gate signal A indicates that the periodic signal A is not allowed to pass. B is not output and the timer value B is not reset. The timer value B is self-reset in S33 as in S26 of FIG.

  Here, the phase fluctuation of the periodic signal A in S32 is a temporary fluctuation, and the next periodic signal A is input when the timer value A reset in S32 is included in the time zone TB (S34). At this time, since the gate signal A indicates that the periodic signal A is not allowed to pass, the gate circuit 15 does not pass the periodic signal A. Therefore, the timer 12 is not reset and does not synchronize with fluctuations in the reception period of the periodic signal A due to temporary fluctuations.

  Next, when the periodic signal A is input, the timer value A and the timer value B are included in the time zone TA, and the periodic signal C is output (S35).

  Thus, even if phase fluctuation occurs in the periodic signal A, if it is temporary, the timer 12 is not synchronized, and the generation timing of the periodic signal C and the reproduction periodic signal is not changed. In addition, during the period in which the periodic signal C disappears (period S36 to S37 in the figure), the reproduction periodic signal is used as a frame update signal for periodic processing instead of the periodic signal C.

  As described above, according to the first embodiment, the timer 11 is always synchronized with the reception timing of the periodic signal A, and the timer 12 that determines the output timing of the periodic signal C indicating the processing timing in the communication device is: Since the periodic signal C and the reproduction periodic signal are output based on the previous reception period held internally without being synchronized with the temporary phase fluctuation of the periodic signal A, it is correct in synchronization with the reception period of the periodic signal A. While outputting the periodic signal C at the timing, it is possible to prevent erroneous synchronization with the phase fluctuation of the periodic signal A temporarily, and there is an effect that the reliability of the frame synchronization apparatus 10 is improved.

Embodiment 2. FIG.
FIG. 4 is a configuration diagram of the frame synchronization apparatus 20 according to the second embodiment of the present invention. The same reference numerals as those in FIG. 1 represent the same components. The frame synchronization device 20 includes a protection counter (protection circuit) 41, a protection gate circuit (protection circuit) 42, a count counter 43, and a frame state signal generation circuit 44.

  The protection counter 41 receives the periodic signal A and the gate signal A, and counts up when the periodic signal A is input when the gate signal A indicates that the periodic signal A is allowed to pass. When the period signal A is received during the period in which the gate signal A indicating the passage permission is output, that is, the timer value A is included in the time zone TA, continues for a preset number of times, Output protection release signal.

  When the protection gate circuit 42 receives the protection release signal from the protection counter 41, the protection gate circuit 42 passes the gate signal A.

  The counting counter 43 is a counter that counts up when the periodic signal B is not input while the gate signal B output from the timing generation circuit 14 indicates that the periodic signal B is allowed to pass. An out-of-frame signal is output if the period signal B is continuously detected for a set number of times while the permission is indicated.

  The frame state signal generation circuit 44 uses the periodic signal B as a signal, outputs “1” indicating that the frame synchronization state is asserted when the frame synchronization signal is asserted, and is out of frame when the out-of-frame signal is asserted. Outputs “0” indicating the state.

  FIG. 5 is a timing chart for explaining the operation of the frame synchronization apparatus 20 according to the second embodiment. The self-reset time of timers 11 and 12 and the setting of time zones TA and TB are the same as in the first embodiment. In addition, here, the number of detections of the periodic signal A within the time period TA in which the protection counter 41 outputs the protection cancellation signal is three.

  In S51, phase fluctuation occurs in the periodic signal A, and only the timer 11 is reset as in the first embodiment. Thereafter, when receiving the periodic signal A while the timer value A is included in the time zone TA continues three times, which is the number of protection stages set in the protection counter 41 (S52), the protection counter 41 receives the protection release signal. The protection gate circuit 42 supplies the gate circuit 15 with a gate signal A indicating that the periodic signal A is allowed to pass. Thereby, the periodic signal B is output, and the timer 12 is synchronized with the reception timing of the new periodic signal A.

  Further, the periodic signal C is output in synchronism with a new reception timing from the reception of the next periodic signal A (S53).

  FIG. 6 is a timing chart for explaining the operation of the frame synchronization apparatus 20 when the reception cycle of the periodic signal A is not stable.

In S61, phase fluctuation occurs in the periodic signal A, and only the timer 11 is reset.
The periodic signal A input thereafter is not received while the timer value A indicated by the timer 11 whose reception period is reset by the previous periodic signal A is included in the time zone TA, and the timer value A is in the time zone TA. Receiving is not repeated three times during inclusion. For this reason, the protection cancellation signal is not output from the protection counter 41, and the protection gate circuit 42 does not supply the gate signal A to the gate circuit 15, so that the periodic signal B is not output. Therefore, the timer 12 keeps holding the reception timing of the periodic signal A before the phase fluctuation, and the reproduction periodic signal output in synchronization with the held reception timing is used for processing in the communication apparatus.

  As described above, according to the second embodiment, by providing the protection circuit composed of the protection counter 41 and the protection gate circuit 42, the timer can be used if the periodic signal A is not input at a preset correct number of times. 12 is not synchronized with the new reception timing. Thereby, erroneous synchronization of the frame synchronization device 20 can be prevented, and a highly reliable frame synchronization device can be provided.

  Further, by providing the count counter 43 and the frame state signal generation circuit 44, the periodic signal B is continuously received a certain number of times while the timer value B of the timer 12 indicates the time zone TA, that is, in the correct time zone. In this case, a frame status signal indicating that the frame is synchronized is output, and if a certain number of receptions are not continued within the allowable time, a signal indicating that the frame is out of frame is output. It is possible to obtain a frame synchronization device which is excellent in reliability, high reliability and good maintainability.

Embodiment 3 FIG.
In the first embodiment and the second embodiment, the frame synchronization device 10 and the frame synchronization device 20 are synchronized with the periodic signal A. In the third embodiment, the variable frame synchronization apparatus is applied to an optical transceiver that inserts and extracts a periodic signal code indicating a frame delimiter in an intermittent empty region of a client data string.

FIG. 7 is a block diagram showing the configuration of the optical transceiver 70 according to the third embodiment of the present invention.
As shown in the figure, an optical transceiver 70 includes an optical / electrical converter 71, a main signal input processing unit (reception-side main signal input processing unit) 72, a control signal separation circuit (reception-side control signal separation circuit) 73, a code Identification circuit (reception side code identification circuit) 74, frame synchronizer (reception side frame synchronization unit) 75, termination circuit (reception side termination circuit) 76, relay circuit (reception side relay circuit) 77, encoding circuit (reception side code) 78), control signal insertion circuit (reception side control signal insertion circuit) 79, main signal output processing unit (reception side main signal output processing unit) 710, generation circuit (reception side generation circuit) 723, main signal input processing unit (Transmission side main signal input processing unit) 711, control signal separation circuit (transmission side control signal separation circuit) 712, code identification circuit (transmission side code identification circuit) 713, frame synchronization device (transmission side frame synchronization unit) 714, relay circuit Transmission side relay circuit) 715, encoding circuit (transmission side encoding circuit) 716, control signal insertion circuit (transmission side control signal insertion circuit) 717, main signal output processing unit (transmission side main signal output processing unit) 719, generation A circuit (transmission side generation circuit) 720, a termination circuit (transmission side termination circuit) 722, and an electric / optical converter 721 are provided.
The main signal input processing unit 72, the control signal separation circuit 73, the code identification circuit 74, the frame synchronization device 75, the termination circuit 76, the relay circuit 77, the encoding circuit 78, the control signal insertion circuit 79, and the main signal output processing unit 710 The generation circuit 723 constitutes a reception unit 701, and a main signal input processing unit 711, a control signal separation circuit 712, a code identification circuit 713, a frame synchronization device 714, a relay circuit 715, an encoding circuit 716, and a control signal insertion circuit 717. The main signal output processing unit 719, the generation circuit 720, and the termination circuit 722 constitute a transmission unit 702.

First, functions of each unit of the receiving unit 701 will be described.
The optical / electrical converter 71 converts an input optical signal input via the optical fiber transmission path into an input electrical signal. The main signal input processing unit 72 receives an input electric signal, performs demultiplexing, parallelization, transmission path code processing, and the like, and outputs a main signal input data string. The control signal separation circuit 73 receives the main signal input data sequence, extracts the control signal code inserted for management, and outputs it. The code identification circuit 74 determines the type of the received control signal code. When the control signal code is a periodic signal code indicating a frame delimiter, the code identification circuit 74 sends a signal to the frame synchronizer 75. 76 or the relay circuit 57.

The frame synchronizer 75 generates a frame update signal according to the received periodic signal, and outputs a reproduction periodic signal when relaying an input electrical signal.
For example, the frame synchronization apparatus 10 according to the first embodiment and the frame synchronization apparatus 20 according to the second embodiment can be applied to the frame synchronization apparatus 75. In this case, the frame update signal output from the frame synchronization device 75 corresponds to the periodic signal C of the frame synchronization device 10 and the frame synchronization device 20, and the reproduction periodic signal output from the frame synchronization device 75 is the frame synchronization device 10 and This corresponds to the reproduction cycle signal of the frame synchronizer 20.

  The termination circuit 76, for example, according to the type of the control signal output from the code identification circuit 74 and the frame update signal, for example, alarm processing for raising an alarm by N consecutive reception, data communication processing, and trace signal processing for preventing erroneous connection Management processing such as. The relay circuit 77 performs a relay process according to the type of the control signal output from the code identification circuit 74 and the frame update signal. For example, after performing a management process such as calculation of the number of transmission path errors, the relay circuit 77 A relay control signal for relaying to the node is output. The generation circuit 723 is a generation circuit that generates a control signal.

  The encoding circuit 78 encodes the periodic signal output from the frame synchronization device 75 and the control signal output from the relay circuit 77 or the generation circuit 723 to generate and output a control signal code. The control signal insertion circuit 79 inserts the control signal code received from the encoding circuit 78 in the main signal input data string while avoiding specific data. The main signal output processing unit 710 performs multiplexing, serialization, transmission path code processing, and the like on the main signal input data sequence, and outputs an output electric signal to the inside of the apparatus.

  The functions of each unit of the transmission unit 702 are also substantially the same as those of the reception unit 701. The generation circuit 720 generates a control signal indicating, for example, the number of errors and failure information. In addition, the generation circuit 720 may generate a control signal from information obtained by termination processing of the termination circuit 76 on the reception unit side. The electrical / optical converter 721 converts the output electrical signal into an optical signal and outputs it to the optical fiber transmission line.

  In the third embodiment, a control signal generation circuit 723 and a termination circuit 722 that are output to the inside of the apparatus are provided. However, when maintenance management that is closed to the inside of the apparatus is unnecessary, these are not provided. Also good.

Next, the operation of the optical transceiver 70 will be described.
A control signal code is extracted from the main signal input data sequence output from the main signal input processing unit 72 by the control signal separation circuit 73. When the control signal code is a periodic signal code, the extracted signal is input to the frame synchronization device 75. As shown in the first or second embodiment, the frame synchronization device 75 generates a frame update signal based on the reception timing of the received periodic signal. Further, when the periodic signal disappears due to a transmission path failure or the like, the frame update signal is generated by using the reproduction periodic signal instead of the periodic signal.

The termination circuit 76 and the relay circuit 77 process the control signal based on a variable-length frame section delimited by the frame update signal output from the frame synchronization device 75. For example, when failure information matches within N consecutive frames, an operation such as raising an alarm is performed. The encoding circuit 78 converts the control signal output from the relay circuit 77, the generation circuit 723, and the frame synchronization device 75 into a code for insertion into the main signal data. The control signal insertion circuit 79 monitors the main signal input data string by holding the control signal code output from the encoding circuit 78, and can be exchanged with control signal codes other than client data and some data strings. Is detected, the held control signal code is inserted into the data string. The generation and relay control signal inserted into the main signal input data string is transmitted to the subsequent node through the main signal output processing unit 710.
Similarly, the transmission unit 702 executes control signal generation, relay, and termination processing.

  As described above, according to the third embodiment, in the optical transceiver 70, a circuit that inserts a control signal for management while avoiding client data in the data string, a circuit that receives a control signal and discriminates a frame, By providing a management signal generation circuit, relay circuit, and termination circuit, it is possible to manage and monitor a transparent transmission path that has high functionality and does not affect the higher-level switching equipment by simply placing the optical transceiver 70. Cost reduction in the entire network can be achieved.

  In addition, since the generation circuit 723 is provided on the reception unit 701 side and the termination circuit 722 is provided on the transmission unit side, the same effect can be obtained by arranging the communication device with the electric exchanger interposed therebetween.

Embodiment 4 FIG.
In the fourth embodiment, the multiple relay prevention function is applied to the relay circuit 77 and the relay circuit 715 of the optical transceiver 70 of the third embodiment. FIG. 8 is a block diagram showing the configuration of the relay circuit 80 of the optical transceiver according to the fourth embodiment. The relay circuit 80 includes count counters (control signal count counters) 81-1 to 81-n (n is a natural number of 2 or more), passage count determination circuits 82-1 to 82-n, and a gate circuit (control signal gate circuit) 83. And a relay processing circuit 84.

  The count counters 81-1 to 81-n are prepared for each type of each control signal identified by the code identifying circuit 74 or the code identifying circuit 713 and transmitted to the relay circuit 80. The count counters 81-1 to 81-n receive each branched control signal, add it if it is a corresponding control signal, and use the frame update signal output from the frame synchronizer 75 or the frame synchronizer 714. Reset. The passage number determination circuits 82-1 to 82-n count the input control signals, and when the count counter indicates 1 or more, output a discard signal to the gate circuit 83 to discard the corresponding control signal. For example, the relay processing circuit 84 performs relay processing such as adding the number of errors generated in the immediately preceding transmission line section to the control signal indicating the number of errors.

FIG. 9 is a flowchart of the operation of the relay circuit 80 according to the fourth embodiment.
First, the count counters 81-1 to 81-n are cleared by initialization (step ST91). Next, relay circuit 80 receives a control signal from code identification circuit 74 or 713 (step ST92). The type of the control signal received in step ST92 is determined and input to the corresponding counters 81-1 to 81-n (step ST93).

  Next, the passage number determination circuits 82-1 to 82-n process the control signal based on the counter values of the count counters 81-1 to 81-n (step ST94). When the counting counters 81-1 to 81-n indicate 0, the corresponding passage number determination circuits 82-1 to 82-n output signals that allow the gate circuit 83 to pass the control signal. The relay processing circuit 84 processes the received control signal. When a control signal of the same type is received again, the counter values of the corresponding count counters 81-1 to 81-n are 2 or more. At this time, the passage number determination circuits 82-1 to 82-n determine from the count values of the count counters 81-1 to 81-n that the same control signal is received twice or more in the same frame. The control signal is discarded without performing termination processing or relay processing.

  Thereafter, the counters of the counting counters 81-1 to 81-n corresponding to each type of control signal are incremented (step ST95). This is repeated for all control signals.

  Steps ST92 to ST95 are repeated for all received control signals until it is determined in step ST96 that a frame update signal has been received from the frame synchronizer 75 or 714.

  If it is determined in step ST96 that the frame update signal has been received, the process returns to step ST91, and the counter values of the counting counters 81-1 to 81-n are all reset. The above operation is repeated every time a periodic signal is received from the frame synchronizer 75 or 714. At this time, the timing of resetting the counter values of the counting counters 81-1 to 81-n is not necessarily based on the frame update signal at the time of reception of the periodic signal, and a frame of arbitrary timing generated by the frame synchronizers 75 and 714. An update signal may be used.

  As described above, according to the fourth embodiment, when the same type of control signal is included in the same frame more than a predetermined number of times, the control signal is discarded. Even when a control signal is generated twice due to a failure such as the above, it is possible to prevent a double transfer to a node in the subsequent stage and a highly reliable optical transceiver can be configured.

  In addition, since it is ensured that only one signal is received in one frame inside the optical transceiver, the buffer amount for waiting for processing can be reduced, and the processing circuit scale inside the apparatus can be reduced. .

  Also, there is usually a difference between the reception time of the frame delimiter signal and the playback time, and when the reception signal of the frame delimiter signal is lost, the playback signal is generated after that, so the control signal between them is It becomes impossible to identify which frame it belongs to. Therefore, it is necessary to provide a control signal insertion prohibition time. However, according to the fourth embodiment, when the frame delimiter signal disappears, the control signal belonging to the subsequent frame is counted by the counter counters 81-1 to 81-n. Can be distinguished. For this reason, it becomes possible to insert the control signal even during the insertion prohibition time, and the band in which the management signal flows can be expanded.

Embodiment 5 FIG.
In the fifth embodiment, the termination circuit of the reception unit and the generation circuit of the transmission unit of the optical transceiver 70 of the third embodiment are provided with a function of transmitting / receiving communication data for network management. FIG. 10 is a block diagram illustrating a configuration of an optical transmission / reception system 100 including the optical transceiver 101 and the optical transceiver 107 according to the fifth embodiment. The same reference numerals as those in FIG. 7 represent the same components. As shown in the figure, the optical transceivers 101 and 107 are different from those of the third embodiment in the configuration of the generation circuit 102 of the transmission unit and the termination circuit 108 of the reception unit. The transmission unit includes a reference clock 106, and the reception unit includes a clock recovery circuit 1012.

  The generation circuit 102 includes a frequency dividing circuit (first frequency dividing circuit) 103, an accumulation circuit (first accumulation circuit) 104, and a control circuit (first control circuit) 105. The termination circuit 108 includes an accumulation circuit (second accumulation circuit) 1011, a frequency divider circuit (second frequency divider circuit) 109, and a control circuit (second control circuit) 1010.

  The frequency dividing circuit 103 divides the reference clock 106 and outputs the divided clock to the outside. The accumulation circuit 104 accumulates data input according to the divided clock. The control circuit 105 receives a signal indicating whether or not communication data can be inserted into the main signal data string from the control signal insertion circuit 717, and controls the storage circuit 104 to control the insertion of communication data into the encoding circuit 716. Do.

  The optical transceiver 101 transmits the main signal input data string to the optical transceiver 107 via the optical fiber transmission line. The optical transceiver 107 stores the communication data separated from the received main signal input data string in the storage circuit 1011. The clock recovery circuit 1012 recovers a clock from the main signal input data string. The frequency divider 109 divides the recovered clock obtained from the clock recovery circuit 1012. The control circuit 1010 controls the frequency dividing circuit 109 and the storage circuit 1011 according to the amount of stored information in the storage circuit 1011.

  The optical transceiver 101 transmits the periodically generated control signal to the optical transceiver 107 by inserting the control signal into the data string while avoiding specific data in the client data. The optical transceiver 107 receives a data string via an optical fiber transmission line and performs a periodic termination process. The network and device management system on the optical transceiver 101 side has communication data at a constant rate to be transmitted to the optical transceiver 106 without affecting the client data input to the main signal input processing unit 711.

  First, a frequency-divided clock having a desired rate is generated by the frequency dividing circuit 103 using the reference clock 103 inside the optical transceiver 101. The external system continues to input communication data to the storage circuit 104 according to the divided clock. The control circuit 105 constantly monitors the control signal insertion circuit 717 and receives a control signal code insertion enabling signal notified from the control signal insertion circuit 717 when detecting a position where the control signal can be inserted in the data string. At this time, if the storage circuit 104 has communication data to be transmitted and transmits a holding notification, an insertion notification is generated and the communication data in the storage circuit 104 is inserted into the data string via the control signal insertion circuit 717. Let At this time, since the client data is inserted while avoiding the client data string, fluctuations occur in the input phase of the communication data from the outside to the storage circuit 104 and the insertion phase from the storage circuit 104 to the data string.

  Communication data inserted into the data string is transmitted through an optical fiber transmission line, reproduced by the main signal input processing unit 72, and then separated from the client data string by the control signal separation circuit 73. Information determined as communication data by the code identification circuit 74 is stored in the storage circuit 1011.

  The clock recovery circuit 1012 extracts a recovered clock from the received data string, and the frequency dividing circuit 109 divides the extracted recovered clock. At this time, the frequency dividing circuit 109 is adapted to the frequency dividing ratio of the frequency dividing circuit 103 of the optical transceiver 101. The duty ratio is not necessarily constant between the divided clock and the frequency dividing circuit 103 and the frequency dividing circuit 109, and may be set so that the number of clocks is the same within a certain period.

FIG. 11 is a flowchart of the operation of the control circuit 1010.
The control circuit 1010 waits until the number of stored data in the storage circuit 1011 reset in step ST111 reaches a fixed number N set from 0, and continues to output a busy signal during that time (step ST112 to step ST114). The frequency dividing circuit 109 that has received the busy signal from the control circuit 1010 stops the clock, and the storage circuit 1011 holds the communication data. After the accumulated communication data reaches a certain amount N, the control circuit 1010 stops the busy signal (step ST115). In response to this, the frequency dividing circuit 109 outputs a clock to the outside (step ST116), and the storage circuit 1011 starts outputting data in accordance with the frequency divided clock (step ST117). Thereafter, while the communication data generated by the optical transmitter / receiver 101 and the communication data output by the optical transmitter / receiver 106 are in an equilibrium state, the communication data is output at a fixed transmission rate in accordance with the divided clock.

  If it is determined in step ST118 that the number of communication data has been input exceeding the amount that can be stored in the storage circuit 1011, the process returns to step ST111, the data in the storage circuit 1011 is discarded, a busy signal is output, and 0 again. Accumulate from. Also, if it is determined in step ST118 that the accumulated data in the accumulation circuit 1011 has become empty, the process returns to step ST111, outputs a busy signal, waits for a certain amount of communication data to accumulate, and then outputs the communication data. Start.

  As described above, according to the fifth embodiment, it is possible to configure a data communication channel that outputs at a fixed transmission rate in a communication system such as Ethernet (registered trademark) that does not synchronize with the network. An optical transceiver can be provided.

  Further, if it is determined in step ST118 in FIG. 11 that there is no accumulated communication data, if the divided clock is stopped, it can be shown to the external system whether the output data is significant data, Communication is possible even when data is transmitted at a transmission rate lower than the set transmission rate, and the versatility is improved.

Embodiment 6 FIG.
In the sixth embodiment, the optical transceiver 70 of the third embodiment is provided with a remote reception failure information return function. FIG. 12 is a configuration diagram of the optical transceiver 121 according to the sixth embodiment. The same reference numerals as those in FIGS. 7 and 10 represent the same components. In the sixth embodiment, when a transmission line failure occurs in the optical fiber transmission line, the optical transceiver 121 as a downstream node that detects the failure returns the remote reception failure information to the upstream node through the optical fiber transmission line.

  As shown in the figure, in the sixth embodiment, the configurations of the termination circuit 122 of the reception unit 1211 and the generation circuit 123 of the transmission unit 1212 are different from those of the third to fifth embodiments. As shown in the figure, the termination circuit 122 includes a failure information holding circuit 125, return information memories 127-1 and 127-2, a delay circuit 128, a phase comparison circuit 129, and a selection circuit 1210. The generation circuit 123 includes a remote failure information generation timing circuit 126.

  If the control signal output from the code identification circuit 74 includes network monitoring information such as failure information or the number of transmission path errors, the failure information holding circuit 125 records the information in a register or gives an alarm. Perform termination processing. The remote failure information generation timing circuit 126 generates a timing for generating remote reception failure information and an update prohibition signal. The return information memories 127-1 and 127-2 hold the monitoring information held by the failure information holding circuit 125 at the timing of the frame update signal output from the frame synchronizer 75 and the timing changed through the delay circuit 128. The phase comparison circuit 129 compares the frame update signal and the changed timing with the update prohibition signal and determines which return information memory output is selected by the selection circuit 1210.

The operation of the optical transceiver 121 will be described.
When the optical transceiver 121 receives the main signal input data via the optical fiber transmission line, if a failure occurs on the optical fiber transmission line, or if failure information is transmitted as a control signal from an upstream node, A control signal including fault information is extracted through the main signal input processing unit 72, the control signal separation circuit 73, and the code identification circuit 74. Further, the failure information holding circuit 125 holds information on the number of transmission path faults and the number of transmission path errors obtained by notifying or not receiving this control signal. Information held in the return information memories 127-1 and 127-2 is written at the generated timing. When failure information or transmission path error number information is periodically transmitted, these return information memories 127-1 and 127-2 are updated at different timings.

  The remote failure information generation timing circuit 126 notifies the phase comparison circuit 129 of an update prohibition signal at the timing of creating remote reception failure information. The phase comparison circuit 129 that has received this signal, when the timing of the update prohibition signal and the return information memory 127 selected by the selection circuit 1210 out of the return information memories 127-1 and 127-2 is close, The return information memory 127 is selected and output. Based on the remote failure information generation timing from the remote failure information generation timing circuit 126 and the failure information from the selection circuit 1210 or the number of errors, the encoding circuit 716 creates a control signal code indicating the remote reception failure information, and the control signal The insertion circuit 717 inserts the client data that is the main signal output data, and returns it to the upstream node through the optical fiber transmission line.

  FIG. 13 is a timing chart for explaining the relationship between the return information memory and the generated control signal having remote reception failure information. In the figure, the vertical line indicates the frame update timing based on the frame update signal, and the arrow vertical line indicates the control signal generation timing, that is, the remote reception signal generation timing. Here, it is assumed that the number of errors is handled as remote failure information, and the generation control signal in FIG. 13 is generated from a plurality of return information memories 127. In FIG. 13, a return information memory 127 that changes at update timing 1 and update timing 2 is prepared. The shaded parts (A, B, C, D, E) in the timing chart are information on the number of transmission path errors accommodated in the return information memory and the generation control signal.

  In FIG. 13, the error count information (update timing 1) indicates that the return information is updated simultaneously with the frame update signal. At this time, it is assumed that the return control signal generation timing is close to the reception timing as shown in the figure. It is assumed that update timing 1 is used for creating remote reception failure information. First, in S131, the reception timing is slightly before the generation timing in S132, but in S133, the reception timing is slightly later than the generation timing due to a slight fluctuation in the arrival time of the reception period signal. Therefore, “E” is read twice as the generated return information. Similarly, in S135, skipping of “C” occurs.

  On the other hand, the control signal processing circuit selects to output the return information memory 127 having other timing by the update prohibition signal. Since update timing 1 is close to the generation timing, the above error has been caused. However, if update timing 2 is selected next time, the remote reception failure information of the generation control signal is read twice (S134). Skipping can be prevented (S136).

  In the sixth embodiment, the error information selection signal is the failure information update prohibition signal. However, the return memory 127 having a plurality of phases may be switched as the failure information update signal. Furthermore, although the frame update signal is selected as the update timing of the return information memory 127, the present invention can also be applied when any periodic timing such as the reception timing of the control signal indicating the number of errors or failure information is used.

  As described above, according to the sixth embodiment, the generation timing of the return information is currently selected when the failure and error count change timing transmitted by the opposite node is approaching and fluctuates. By selecting the return information memory 127 whose timing is different from that of the return information memory 127, multiple counts and slips can be prevented when returning the number of errors to the opposite node, and a highly reliable communication device and optical transceiver Can be configured.

  In addition, when the control signal generation timing and the control signal reception timing completely overlap with each other, there is an effect of preventing the recognition as an erroneous number in the transient state of the update of the multi-bit information such as the erroneous number.

Embodiment 7 FIG.
In the seventh embodiment, the optical transceiver 70 of the third embodiment receives maintenance switching information for automatically switching a route when a network failure occurs in the generation circuit and the termination circuit of the optical transceiver. It has a function.
FIG. 14 is a block diagram illustrating a configuration of an optical transmission / reception system 140 including the optical transceiver 141 and the optical transceiver 142 according to the seventh embodiment. The same reference numerals as those in FIG. 7 represent the same components. In FIG. 14, it is assumed that maintenance switching information is transmitted from the optical transceiver 141 toward the optical transceiver 142.

  As shown in the figure, the optical transceivers 141 and 142 are different from those in the third embodiment in the configuration of the generation circuit 149 of the transmission unit and the termination circuit 1410 of the reception unit. The generation circuit 149 includes an information writing unit 143, an information holding circuit (first information holding circuit) 144, and a control circuit (third control circuit) 145. The termination circuit 1410 includes a control circuit (fourth control circuit) 146, an information holding circuit (second information holding circuit) 147, and an information reading unit 148.

  The information writing unit 143 writes the maintenance switching information written from the outside into the information holding circuit 144. The information holding circuit 144 holds the maintenance switching information, and the control circuit 145 receives the control signal insertion enable signal from the control signal insertion circuit 717 and causes the information holding circuit 144 to receive the control signal in the encoding circuit 716. , Send. The control circuit 146 that has received the control signal including the maintenance switching information in the optical transceiver 142 as the downstream node processes the maintenance switching information according to a flowchart shown in FIG. The information holding circuit 147 holds maintenance switching information when conditions such as receiving the same signal within N consecutive frames match, and the information reading unit 148 holds the maintenance switching information held outside. Output.

FIG. 15 is a flowchart showing the operation of the optical transmission / reception system 140 according to the seventh embodiment.
First, the protection counter is cleared by initialization (step ST151). Next, when maintenance switching information is received in step ST152, it is checked in step ST153 whether the protection switching signal indicated by the maintenance switching information is different from the previously received value. If it is determined in step ST153 that the value is different from the previously received value, the process proceeds to step ST154, and the protection counter is incremented by one. If it is determined in step ST153 that the value is equal to the value received last time, the process proceeds to step ST155, and it is determined whether the count number is equal to the protection stage number N set by the protection counter. If it is determined in step ST155 that the number is equal to the protection stage number N, the process returns to step ST152 and waits for a maintenance switching signal. If it is determined in step ST155 that it is not equal to the protection stage number N, the protection counter is incremented in step ST156, and the protection count number is determined again in step ST157. If it is determined in step ST157 that the protection count number is not equal to the protection stage number N, the process returns to step ST152 to enter a state of waiting for a maintenance switching signal. When it is determined that the protection count number is equal to the protection stage number N, the process proceeds to step ST158, where the maintenance switching information to be held is updated, and notification that the update has been made to the outside is made (step ST159). Furthermore, after continuing for a fixed time, the update notification is stopped (step ST160).

  As described above, according to the seventh embodiment, the information periodically transmitted for maintenance switching is held, and when there is a change in the maintenance switching information, it is notified to the outside. With a simple configuration, a maintenance switching protocol can be realized with a small number of signal lines, and a compact optical transceiver can be provided.

It is a block diagram which shows the structure of the frame synchronizer by Embodiment 1 of this invention. It is a timing chart explaining operation | movement of the frame synchronizer by Embodiment 1 of this invention. It is a timing chart explaining operation | movement of a frame synchronizer when the receiving period of the periodic signal by Embodiment 1 of this invention is not stabilized. It is a figure which shows the structure of the frame synchronizer by Embodiment 2 of this invention. It is a timing chart explaining operation | movement of the frame synchronizer by Embodiment 2 of this invention. It is a timing chart explaining operation | movement of a frame synchronizer when the receiving period of the periodic signal by Embodiment 2 of this invention is not stabilized. It is a block diagram which shows the structure of the optical transmitter / receiver by Embodiment 3 of this invention. It is a block diagram which shows the structure of the relay circuit of the optical transmitter / receiver by Embodiment 4 of this invention. It is a flowchart of operation | movement of the relay circuit by Embodiment 4 of this invention. It is a block diagram which shows the structure of the optical transmission / reception system by Embodiment 5 of this invention. It is a flowchart of operation | movement of the control circuit by Embodiment 5 of this invention. It is a block diagram which shows the structure of the optical transmitter / receiver by Embodiment 6 of this invention. It is a timing chart explaining the relationship between the return information memory by Embodiment 6 of this invention, and the control signal with the remote reception failure information produced | generated. It is a block diagram which shows the structure of the optical transmission / reception system by Embodiment 7 of this invention. It is a flowchart of operation | movement of the optical transmission / reception system by Embodiment 7 of this invention.

Explanation of symbols

  10 frame synchronization device, 11 timer (first timer), 12 timer (second timer), 13 timing generation circuit (first timing generation circuit), 14 timing generation circuit (second timing generation circuit), 15 Gate circuit (first gate circuit), 16 gate circuit (second gate circuit), 41 protection counter (protection circuit), 42 protection gate circuit (protection circuit), 43 count counter, 44 frame state signal generation circuit, 70 Optical transceiver, 71 Optical / electrical converter, 72 Main signal input processing unit (reception side main signal input processing unit), 73 Control signal separation circuit (reception side control signal separation circuit), 74 Code identification circuit (reception side code identification) Circuit), 75 frame synchronization device (reception side frame synchronization unit), 76 termination circuit (reception side termination circuit), 77 relay circuit (reception side relay circuit) ), 78 Coding circuit (Reception side coding circuit), 79 Control signal insertion circuit (Reception side control signal insertion circuit), 80 Relay circuit (Reception side relay circuit, Transmission side relay circuit), 81-1 to 81-n Count counter (control signal count counter), 82-1 to 82-n Pass count determination circuit, 83 gate circuit (control signal gate circuit), 84 relay processing circuit, 100 optical transmission / reception system, 101, 107 optical transceiver, 102 generation Circuit (transmission side generation circuit), 103 frequency divider circuit (first frequency divider circuit), 104 storage circuit (first storage circuit), 105 control circuit (first control circuit), 106 reference clock, 108 termination circuit (Reception side termination circuit), 109 frequency division circuit (second frequency division circuit), 121 optical transceiver, 122 termination circuit (reception side termination circuit), 123 generation circuit (transmission side generation circuit) , 125 fault information holding circuit, 126 remote fault information generation timing circuit, 127-1, 127-2 return information memory, 128 delay circuit, 129 phase comparison circuit, 140 optical transceiver system, 141, 142 optical transceiver, 143 information book 144, information holding circuit (first information holding circuit), 145 control circuit (third control circuit), 146 control circuit (fourth control circuit), 147 information holding circuit (second information holding circuit) 148 Information reading unit, 149 generation circuit (reception side generation circuit), 701 reception unit, 702 transmission unit, 710 main signal output processing unit (reception side main signal output processing unit), 711 main signal input processing unit (transmission side main circuit) Signal input processing unit), 712 control signal separation circuit (transmission side control signal separation circuit), 713 code identification circuit (transmission side code identification circuit), 714 Frame synchronization device (transmission side frame synchronization unit), 715 relay circuit (transmission side relay circuit), 716 encoding circuit (transmission side encoding circuit), 717 control signal insertion circuit (transmission side control signal insertion circuit), 719 main signal Output processing unit (transmission side main signal output processing unit), 720 generation circuit (transmission side generation circuit), 721 electrical / optical converter, 722 termination circuit (transmission side termination circuit), 723 generation circuit (reception side generation circuit), 1010 control circuit (second control circuit), 1011 storage circuit (second storage circuit), 1012 clock recovery circuit, 1210 selection circuit, 1211 reception unit, 1212 transmission unit, 1410 termination circuit (transmission side termination circuit).

Claims (12)

In a frame synchronization apparatus that is provided in a communication apparatus and generates processing timing in the communication apparatus based on the reception timing of a periodic signal,
A first timer that is initialized in response to the input of the periodic signal;
A first timing generation circuit for generating and outputting a first gate signal indicating whether or not to pass the periodic signal based on the first timer value;
A first gate circuit for passing or stopping the periodic signal based on the first gate signal;
A second timer that is initialized by receiving an input of a periodic signal that has passed through the first gate circuit;
Based on the second timer value, a second gate signal indicating whether or not to pass the periodic signal that has passed through the first gate circuit, and a reproduction periodic signal that is used when the periodic signal disappears are generated. A second timing generation circuit for outputting,
A frame synchronization apparatus comprising: a second gate circuit that passes or stops a periodic signal that has passed through the first gate circuit based on the second gate signal. A protection circuit that generates and outputs a protection release signal when a periodic signal is received a certain number of times while the first gate signal indicates permission to pass;
The first gate circuit is characterized in that when the first gate signal indicates permission to pass and the protection release signal is output, the periodic signal is allowed to pass; otherwise, the first gate signal is stopped. The frame synchronization apparatus according to claim 1. A count counter that generates and outputs an out-of-frame signal when the periodic signal that has passed through the first gate circuit is not received for a certain number of times while the second gate signal indicates permission to pass;
3. The frame synchronization according to claim 1, further comprising a frame state signal generation circuit that generates and outputs a frame state signal based on the out-of-frame signal and the periodic signal that has passed through the first gate circuit. apparatus. An optical / electrical converter for converting a received optical signal into a received electrical signal;
A receiving main signal input processing unit for reproducing a received data string from the received electrical signal;
A receiving unit having a receiving main signal output processing unit for generating an output electric signal from the received data sequence;
A transmission-side main signal input processing unit that reproduces a transmission data string from the input electrical signal;
A transmission-side main signal output processing unit that generates a transmission electrical signal from the transmission data sequence;
In an optical transceiver comprising a transmitter having an electrical / optical converter for converting the transmission electrical signal into a transmission optical signal,
The receiver is
A receiving-side control signal separation circuit that extracts and outputs a control signal from the received data sequence;
The type of the control signal is determined, the receiving side code identification circuit that distributes and outputs the periodic signal and other control signals,
Receiving the periodic signal, performing frame synchronization processing, generating and outputting a frame update signal and a reproduction periodic signal; and a receiving-side frame synchronization unit;
A receiving-side termination circuit that receives the other control signals and the frame update signal and performs termination processing;
A receiving side relay circuit that receives the other control signal and the frame update signal and outputs a relay control signal;
A reception side encoding circuit that receives and encodes the relay control signal and the reproduction period signal and outputs an encoding control signal;
A reception-side control signal insertion circuit that periodically inserts the encoded control signal into the received data sequence;
The transmitter is
A transmission-side control signal separation circuit that extracts and outputs a control signal from the transmission data sequence;
Determining the type of the control signal, and distributing and outputting the periodic signal and other control signals; and
A frame synchronizer that receives the periodic signal and performs frame synchronization processing, and generates and outputs a frame update signal and a reproduction periodic signal; and
A transmission-side relay circuit that receives the other control signal and the frame update signal and outputs a relay control signal;
A transmission side generation circuit that generates a generation control signal including failure information;
A transmission side encoding circuit that receives and encodes the relay control signal, the reproduction cycle signal, and the generation control signal, and outputs an encoding control signal;
An optical transceiver comprising a transmission-side control signal insertion circuit that periodically inserts the encoded control signal code into the transmission data string.   5. The optical transceiver according to claim 4, wherein the reception unit includes a reception side generation circuit that generates a generation control signal and transmits the generation control signal to the reception side encoding circuit.   5. The light according to claim 4, wherein the transmission unit includes a transmission side termination circuit that receives the control signal from the transmission side code identification circuit and the frame update signal from the transmission side frame synchronization unit and performs termination processing. Transceiver.   The frame synchronization device according to any one of claims 1 to 3, wherein the reception side frame synchronization unit and the transmission side frame synchronization unit are any one of claims 4 to 6. The optical transceiver according to claim 1. The reception side relay circuit and the transmission side relay circuit are a control signal counter that records the number of control signals received from the reception side code identification circuit or the transmission side code identification circuit within a period delimited by the frame update signal,
Based on the value of the control signal counting counter, a passage number determination circuit that generates a gate signal that determines whether or not the control signal can be received; and
A control signal gate circuit for passing or stopping the control signal according to the gate signal;
8. The optical transceiver according to claim 4, further comprising: a relay processing circuit that outputs a relay control signal for the control signal that has passed through the control signal gate circuit. The transmission side generation circuit includes a first frequency dividing circuit that divides and outputs a reference clock;
A first storage circuit that holds management communication data that is input according to the frequency-divided clock generated by the first frequency dividing circuit, and that outputs a holding notification when the management communication data is held;
When the control signal insertion enable notification indicating that the control signal can be inserted into the transmission data is received from the transmission-side control signal insertion circuit and the holding notification is received from the first storage circuit, the first storage circuit Including a first control circuit for outputting an insertion notification,
When the first storage circuit receives the insertion notification, the first storage circuit transmits the management communication data to the transmission side encoding circuit,
A receiving side termination circuit that extracts and stores management communication data from the control signal received from the receiving side code identification circuit;
A second frequency dividing circuit for frequency-dividing the clock regenerated by the clock regenerating circuit from the received data string and outputting it as a frequency-divided clock indicating a data delimiter;
When the management communication data stored in the second storage circuit reaches a certain amount, the management communication data is output to the outside in accordance with the divided clock provided by the second frequency dividing circuit, and the stored management communication data And a second control circuit for discarding the management communication data held at that time when the amount of data exceeds a maximum data amount that can be stored in the second storage circuit. The optical transceiver according to any one of claims 4 to 7.   10. The second control circuit according to claim 9, wherein when the management communication data stored in the second storage circuit is exhausted, the second control circuit stops the frequency-divided clock output from the second frequency-dividing circuit. Optical transceiver. The transmission side generation circuit includes a remote failure information generation timing circuit that outputs a signal instructing generation of remote failure information,
The reception-side termination circuit includes a failure information holding circuit that holds network monitoring information included in the control signal output from the reception-side code identification circuit;
A plurality of return information memories that hold fault information output from the fault information holding circuit and output remote fault information;
A delay circuit for changing the update timing of each of the return information memories based on a frame update signal received from the reception-side frame synchronization unit and outputting a return information memory update signal;
A phase comparison circuit for comparing the phase of the return information memory update signal and the update inhibition signal output from the remote fault information generation timing circuit;
8. The light according to claim 4, further comprising a selection circuit that selects a return information memory that outputs remote fault information based on a comparison result of the phase comparison circuit. 9. Transceiver. The reception-side generation circuit includes a first information holding circuit that holds maintenance switching information input from the outside,
An information writing unit for writing the maintenance switching information in the first information holding circuit;
A third control circuit for instructing the transmission side encoding circuit to transmit the maintenance switching information held in the first information holding circuit;
The transmission side termination circuit determines whether or not the maintenance switching information received in the period delimited by the frame update signal matches the maintenance switching information received in the immediately preceding period. A fourth control circuit that outputs a change notification in the event of a failure,
When the change notification is output, a second information holding circuit that holds the maintenance switching information;
The optical transceiver according to any one of claims 4 to 7, further comprising an information reading unit for outputting the maintenance switching information to the outside.

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