JP2009516318A - Reverse coupling effect by timing information - Google Patents

Abstract

  It is possible that the apparent charge stored in the floating gate (or other charge storage element) of the non-volatile memory cell may shift, but this is not the case with the adjacent floating gate (or other adjacent charge storage). This is because the electric field is coupled by the charge accumulated in the device. This problem is most noticeable between adjacent sets of memory cells programmed at different times. To compensate for this coupling, if the read process for a given memory cell is programmed after the given memory cell, the read process will take into account the programmed state of the neighboring memory cell. Execute. Disclosed is a technique for determining whether an adjacent memory cell is programmed after or before a given memory cell.

Description

  The present invention relates to a nonvolatile memory.

  Semiconductor memory is increasingly used in various electronic devices. For example, non-volatile semiconductor memory is used in cell phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable programmable read only memory (EEPROM) and flash memory are the most popular non-volatile semiconductor memories.

  Both conventional EEPROM and flash memory utilize floating gates that are located above the channel region in the semiconductor substrate and insulated from the channel region. This floating gate is located between the source region and the drain region. A control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum voltage that must be applied to the control gate to turn on the transistor for the purpose of conducting between the source and drain is controlled by the level of charge on the floating gate.

  When programming a flash memory device, such as an EEPROM device or a NAND flash memory device, typically a program voltage is applied to the control gate to ground the bit line. Electrons from the channel are injected into the floating gate. As electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised, thereby placing the memory cell in a programmed state. Further information on programming can be found in US Pat. No. 6,859,397 entitled “Detecting Over Programmed Memory”, both incorporated herein by reference in their entirety, and “Detecting Over” filed on July 29, 2003. It can be found in US patent application Ser. No. 10 / 629,068 entitled “Programmed Memory”.

  Some EEPROM and flash memory devices have floating gates that are used to store two ranges of charge. Thus, it is possible to program / erase a memory cell as one of two states: an erased state and a programmed state. Such flash memory is sometimes referred to as a binary flash memory device.

  Multi-state flash memory devices are implemented by specifying a plurality of different allowed / valid program threshold voltage ranges separated by forbidden ranges. Each of these different threshold voltage ranges corresponds to a predetermined value of the set of data bits encoded in the memory device.

  It is possible that the apparent charge stored in the floating gate is shifted, because the electric field is coupled by the charge stored in the adjacent or neighboring floating gate. This coupling phenomenon between floating gates is described in US Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. Floating gates that can cause coupling to the target floating gate include floating gates on the same bit line, floating gates on the same word line, and other bit lines and other word lines. There is a floating gate opposite the floating gate.

  The coupling phenomenon between floating gates is most noticeable between a set of memory cells programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate corresponding to a data set. Next, one or more adjacent memory cells are programmed to add a level of charge to their floating gates corresponding to the second data set. After programming this one or more neighboring memory cells, the charge level read from the first memory cell will appear to be different from the programmed level, which is connected to the first memory cell. This is because the electric charge affects the adjacent memory cell. Coupling from the adjacent memory cell changes the apparent level of the read charge so that the stored data reading is misleading.

  The effect of coupling between floating gates is a more troublesome problem with multi-state devices because the threshold voltage tolerance and prohibition ranges are narrower for binary states than for binary devices.

  As the size of the memory cell decreases, the natural programming distribution and erase distribution of the threshold voltage will increase. This is due to the effect of shortening the channel, increasing oxide film thickness / bonding ratio variation, and increasing channel dopant variation. Therefore, it is considered that the available area that separates adjacent states decreases. This effect is more severe in the case of multi-state memories than in memories that use only two states (binary memory). Further, the coupling between adjacent floating gates is increased by reducing the space between the word lines and the space between the bit lines.

  In order to compensate for coupling between adjacent floating gates, if the next cell is programmed next to this memory cell during the read process for a given memory cell, the programming state of this adjacent memory cell is taken into account. To do. Techniques for determining whether adjacent memory cells are programmed before or after a given memory cell are disclosed below.

  One embodiment accesses customized timing information for a set of data stored in one or more non-volatile storage elements and reads the data set from the one or more non-volatile storage elements Has steps. The step of reading data selectively compensates for one or more potential errors present in the data set based on the timing information.

  One embodiment includes a plurality of non-volatile storage elements, a set of word lines connected to the non-volatile storage elements, and one or more management circuits in communication with the non-volatile storage elements. . The one or more management circuits program data in the non-volatile storage elements in the order of the word lines rather than in a predetermined order. When programming in this way, the timing information of this data is stored. The one or more management circuits read data from the non-volatile storage system. At this time, the stored timing information is received from the non-volatile storage element in which the adjacent non-volatile storage element stores the data. If it indicates that it may be programmed later, it compensates for coupling between non-volatile storage elements.

  One example of a non-volatile memory system suitable for implementing the present invention uses a NAND flash memory structure. In the NAND flash memory structure, a plurality of transistors are arranged in series between two select gates. The transistor in series and the select gate are called a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 in series, and is sandwiched between a first selection gate 120 and a second selection gate 122. Select gate 120 connects the NAND string to bit line contact 126. Select gate 122 connects the NAND string to source line contact 128. Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. Select gate 122 is controlled by applying an appropriate voltage to control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 includes a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. In one embodiment, each of transistors 100, 102, 104, 106 is a memory cell. In other embodiments, the memory cell may include a plurality of transistors and may differ from the configuration shown in FIGS. Select gate 120 is connected to select line SGD, and select gate 122 is connected to select line SGS.

  FIG. 3 shows a cross-sectional view of the NAND string described above. As shown in FIG. 3, the NAND string transistor is formed in the p-well region 140. Each transistor has a stack gate structure including a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The floating gate is formed on the surface of the p-well on the oxide film or other dielectric film. The control gate is located on the floating gate, and the control gate and the floating gate are separated by an interpolysilicon dielectric layer. The control gates of the memory cells (100, 102, 104, 106) form a word line. N + doped layers 130, 132, 134, 136, 138 are shared between adjacent cells, whereby the cells are connected in series with each other to form a NAND string. These N + doped layers form the source and drain of each cell. For example, N + doped layer 130 serves as the drain of transistor 122 and the source of transistor 106. The N + doped layer 132 serves as the drain of the transistor 106 and the source of the transistor 104. N + doped layer 134 serves as the drain of transistor 104 and the source of transistor 102. N + doped layer 136 serves as the drain of transistor 102 and the source of transistor 100. N + doped layer 138 serves as the drain of transistor 100 and the source of transistor 120. The N + doped layer 126 is connected to the bit line of the NAND string, and the N + doped layer 128 is connected to the common source line of the plurality of NAND strings.

  1-3, four memory cells are shown in the NAND string, but it should be noted that the configuration using four transistors is an example. NAND strings used by the techniques described herein may have less than four memory cells, or may have more than four memory cells. For example, some NAND strings can include 8, 16, 32, 64, or more memory cells. The description herein does not limit the number of memory cells in a NAND string to a specific number.

  Each memory cell can store data represented in analog or digital form. When storing 1-bit digital data, the range of possible threshold voltages of the memory cell is divided into two ranges to which logical data “1” and “0” are assigned. In an example of the NAND flash memory, the threshold voltage after the memory cell is erased becomes negative and is defined as logic “1”. The threshold voltage after the program operation is positive and is defined as logic “0”. If a read is attempted by applying 0V to the control gate with a negative threshold voltage, the memory cell is turned on, indicating a logic 1 is being stored. If a read operation is attempted by applying 0V to the control gate with the threshold voltage being positive, the memory cell is not turned on, indicating that a logic “0” is stored.

  In addition, the memory cell can store a plurality of states, and for example, can store digital data of a plurality of bits. When storing data of a plurality of states, the threshold voltage range is divided into the number of states to be stored. For example, when information of four states is used, there are four threshold voltage ranges, and data values “11”, “10”, “01”, and “00” are assigned to each. In an example of the NAND memory, the threshold voltage after the erase operation is negative and is defined as “11”. A positive threshold voltage is used for states of “10”, “01”, “00”. In some embodiments (such as those illustrated above), these data values (eg, logic states) are assigned to threshold ranges using the Gray code assignment method, which causes the floating gate threshold voltage to be incorrect. Even if it shifts to the adjacent physical state, only one logical bit is affected. The specific relationship between the data programmed into the memory cell and the threshold voltage range of this cell depends on the data encoding scheme employed for the memory cell. For example, US Pat. No. 6,222,762 entitled “Tracking Cells For A Memory System” filed Jun. 13, 2003 and US patent application Ser. No. 10 filed Jun. 13, 2003, both of which are incorporated herein by reference in their entirety. / 461,244 describes various data encoding schemes for multi-state flash memory cells.

  Examples related to NAND flash memories and their operation are provided in the following US patents / patent applications, each of which is incorporated herein by reference in its entirety. U.S. Patent 5,570,315, U.S. Patent 5,774,397, U.S. Patent 6,046,935, U.S. Patent 5,386,422, U.S. Patent 6,456,528, And US patent application Ser. No. 09 / 893,277 (publication number US2003 / 0002348). In addition to NAND flash memory, other types of non-volatile flash memory may also be used with the present invention.

  Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described by Chang et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device” in EDL-8, Volume 3 of IEEE Electron Device Letter, published in March 1987. It is described in pages 93-95 of the article. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the conductive control gate and the surface of the semiconductive substrate on the channel of the memory cell. . The cell is programmed by injecting electrons from the cell channel into the nitrogen where they are trapped and stored in a limited area. This accumulated charge then changes the threshold voltage of a portion of the cell's channel, but this change is detectable. This cell is erased by injecting hot holes into the nitrogen. Also, read pages 497-501 of “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disc Application” by Nozaki et al., Volume 26, Issue 4 of the IEEE Journal on Solid State Circuits published in April 1991. For example, a similar cell of an isolated gate structure has been described in which a doped polycrystalline silicon gate extends over a portion of a memory cell channel to form select transistors that are isolated from each other. The entirety of the above two articles is incorporated herein by reference. "Nonvolatile Semiconductor Memory Technology 1.2" edited by William D. Brown and Joe E. Brewer of the 1998 IEEE Press, incorporated herein by reference. The programming techniques mentioned in the chapter are also described in this chapter as being applicable to dielectric charge trapping devices. The memory cells described in this paragraph are also coupled between adjacent memory cells. Accordingly, the techniques described herein also apply to coupling between dielectric regions of different memory cells.

  Another method of storing two bits in each cell is described by Eitan et al., Volume 21, Issue 11 of the IEEE Electron Device Letter, published in November 2000, “NROM: A Novel Localized “Trapping, 2-Bit Nonvolatile Memory Cell”, pages 543-545. An ONO dielectric layer extends over the channel between the source and drain doped layers. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is stored by separately reading the binary states of the spatially separated charge storage regions inside the dielectric. The memory cells described in this paragraph can also be used in the present invention.

  FIG. 4 is a block diagram of one embodiment of a flash memory system. In this system, the memory cell array 202 is controlled by a column control circuit 204, a row control circuit 206, a C-source control circuit 210, and a p-well control circuit 208. The column control circuit 204 facilitates programming or inhibits programming by reading data stored in the memory cells, determining the state of the memory cells during a program operation, and controlling the potential level of the bit lines. In order to do this, it is connected to the bit line of the memory cell array 202. The row control circuit 206 is connected to the word line to select any of the word lines, apply a read voltage, apply a program voltage, and apply an erase voltage. For example, the program voltage level used in EPROM and flash memory circuits is higher than the voltage used in normal memory circuits. These are often higher than the voltage supplied to the circuit. These high voltages are preferably generated by a charge pump in the row control circuit 206 (or elsewhere). The row control circuit 206, in one example, essentially charges the capacitive word line and raises the voltage. The charge pump receives the input at the voltage Vin, gradually increases the input voltage in the process of voltage amplification, and outputs a higher voltage Vout. The output voltage is supplied to a load, for example, a word line of an EPROM memory circuit. In some embodiments, a feedback signal is sent from the load to the charge pump. Prior art pumps stop in response to a signal indicating that the load has reached a predetermined voltage. Also, when the load reaches a predetermined voltage, a shunt is used to prevent overcharge. However, this consumes more power and is not desirable when applying low voltages. Detailed information regarding the charge pump is described in US Pat. No. 6,734,718, which is hereby incorporated by reference in its entirety.

  The C-source control circuit 210 controls a common source line (shown as “C-source” in FIG. 5) connected to the memory cell. The P-well control circuit 208 controls the p-well voltage.

  Data stored in the memory cell is read by the column control circuit 204 and output to the external I / O line via the data input / output buffer 212. Program data stored in the memory cell is input to the data input / output buffer 212 via the external I / O line and transferred to the column control circuit 204. The external I / O line is connected to the controller 218.

  Command data for controlling the flash memory device is input to the controller 218. The command data notifies the flash memory of what operation is requested. Input commands are forwarded to state machine 216 that controls column control circuit 204, row control circuit 206, C-source control 210, p-well control circuit 208, and data input / output buffer 212. The state machine 216 may further output flash memory status data such as ready / busy (BUSY) or pass / fail (FAIL). In some embodiments, the state machine 216 is responsible for managing a programming process, a verification process, and a read process, including the steps depicted in the flowcharts described below.

  The controller 218 is connected to or connectable to a host system such as a personal computer, a digital camera, or a personal digital assistant. Controller 218 receives commands and data from the host and communicates with the host to provide data and status information to the host. Controller 218 converts commands from the host into command signals that can be decoded and executed by command circuit 214 in communication with state machine 216. The controller 218 typically has a buffer memory for user data that is written to or read from the memory array. In some embodiments, the programming process can be managed by this controller.

  An example memory system includes one integrated circuit that includes a controller 218 and one or more integrated circuit chips, each including a memory array and associated control, input / output, and state machine circuits. Memory arrays and system controller circuits tend to be integrated together on one or more integrated circuit chips. The memory system may be incorporated as part of the host system or may be included in a memory card (or other package) that is removably inserted into the host system. Such removable cards may include the entire memory system (eg, including a controller) or may include only the memory array and associated peripheral circuitry (the controller is embedded within the host). ). In this way, the controller (or control function) can be embedded in the host or included in a removable memory system.

  In some embodiments, some of the components of FIG. 4 can be combined. In various designs, one or more of the components of FIG. 4 (single or combined) other than the memory cell array 202 can be considered a control circuit. For example, the one or more control circuits may be any one or a combination of a command circuit, a state machine, a row control circuit, a column control circuit, a well control circuit, a source control circuit, and a data input / output circuit. May be included.

  An example of the structure of the memory cell array 202 will be described with reference to FIG. As an example, a NAND type flash EEPROM divided into 1,024 blocks will be described. Data stored in each block is simultaneously erased. In one embodiment, a block is the smallest unit of cells that are simultaneously erased. In this embodiment, each block has 8,512 columns and is divided into even and odd columns. The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo). FIG. 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, the number of cells used may be four or more or four or less. One terminal of the NAND string is connected to the corresponding bit line via the selection transistor SGD, and the other terminal is connected to the C-source line via the second selection transistor SGS.

  During one embodiment of read and programming operations, 4,256 memory cells are simultaneously selected. The selected memory cells have the same word line and the same type of bit line (for example, even bit line or odd bit line). Thus, 532 bytes of data can be read or programmed simultaneously. 532 bytes of data form a logical page and can be read or programmed simultaneously. Thus, one block can store at least 8 logical pages (4 word lines, each with odd and even pages). In the case of multi-state memory cells, each memory cell stores 2 bits of data (eg, a multi-state memory cell), and if these 2 bits are stored on different pages, one block stores 16 logical pages. To do. Other sized blocks and pages may also be used with the present invention. Furthermore, structures other than those shown in FIGS. 4 and 5 can be used to practice the present invention. For example, in one embodiment, the bit lines are not divided into odd and even lines so that all bit lines are programmed and read simultaneously (or non-simultaneously).

  The memory cell is erased by raising the p-well to an erase voltage (for example, 20 volts) and grounding the word line of the selected block. The source and bit lines are floating. Erasing can be performed on the entire memory array, an independent block, or another unit of cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative.

  In read and verify operations, select gates (SGD and SGS) and unselected word lines (eg, WL0, WL2, and WL3) are connected to a read pass voltage (eg, 4.5 volts) to operate the transistors as pass gates. ). The selected word (eg, line WL1) is connected to a specified level voltage for each read and verify operation, and whether the threshold voltage of the associated memory cell is above or below the specified level voltage. Is determined. For example, in the read operation of the two-level type memory cell, the selected word line WL1 may be grounded, thereby detecting whether or not the threshold voltage is higher than 0V. In the verification operation of the two-level memory cell, the selected word line WL1 is connected to, for example, 0.8V, thereby verifying whether the threshold voltage has reached at least 0.8V. The source and p-well are 0 volts. The selected bit line (BLe) is precharged to a level of 0.7V, for example. If the threshold voltage is higher than the read or verify level on the word line, the potential level of the bit line (BLe) associated with the cell in question is maintained at a high level due to the non-conductive memory cell. On the other hand, when the threshold voltage is lower than the read or verify level, the potential level of the associated bit line (BLe) drops to a low level, for example, less than 0.5 V, because conductive memory cells discharge the bit line. To do. Thereby, the state of the memory cell is detected by a voltage comparator sense amplifier connected to the bit line.

  The erase, read and verify operations described above are performed according to techniques known in the art. Accordingly, many of the details described can be varied by one skilled in the art. Other erase, read and verify techniques known in the art can also be used.

  As described above, each block can be divided into many pages. In one embodiment, one page is a unit of programming. In some embodiments, individual pages may be divided into segments, and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. Generally, data for one page or more is stored in one row of memory cells. It is possible to store more than one sector per page. One sector includes user data and overhead data. The overhead data includes an error correction code (ECC) calculated from user data in the sector. A portion of the controller calculates an ECC while data is being programmed into the array, and also uses this ECC to check while data is being read from the array. In the alternative, ECC and / or other overhead data is stored in a different page than the user data to which it belongs, and in a different block. In other embodiments, other portions of the memory device (eg, a state machine) can calculate the ECC.

  The sector containing user data is generally 512 bytes corresponding to the size of the sector in the magnetic disk drive. Overhead data is typically an additional 16-20 bytes. Many pages form one block, and the numerical value is, for example, any value between 8 pages, 32 pages, 64 pages, and more.

  FIG. 6 shows the threshold voltage distribution of the memory cell array when each memory cell stores 2-bit data. FIG. 6 shows a first threshold voltage distribution E of erased memory cells. A, B, and C show three threshold voltage distributions of the programmed memory cell. In one design, the threshold voltage in distribution E is negative and the threshold voltage in distributions A, B, and C is positive.

  Each of the different threshold voltage ranges in FIG. 6 corresponds to a predetermined value of the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of this cell depends on the data encoding scheme employed for the cell. In one example, “11” is assigned to the threshold voltage range E (state E), “10” is assigned to the threshold voltage range A (state A), “00” is assigned to the threshold voltage range B (state B), “01” is assigned to the threshold voltage range C (state C). However, some embodiments use other schemes.

  FIG. 6 also shows three reference voltages Vra, Vrb, and Vrc for reading data from the memory cell. By testing whether the threshold voltage of a given memory cell is greater or less than Vra, Vrb and Vrc, the system can determine which state the memory cell is in. FIG. 6 also shows three verification reference voltages Vva, Vvb, and Vvc. When programming memory cells to state A, the system tests whether the threshold voltage of these memory cells is greater than or equal to Vva. When programming memory cells to state B, the system tests whether the threshold voltage of these memory cells is greater than or equal to Vvb. When programming memory cells to state C, the system tests whether the threshold voltage of these memory cells is greater than or equal to Vvc.

  In one embodiment, known as full sequence programming, the memory cell is programmed directly from erased state E to any of programmed states A, B, or C (shown by curved arrows). Is possible. For example, the population of memory cells to be programmed is first erased, so that all memory cells in this population are in erased state E. While some memory cells are programmed from state E to state A, other memory cells are programmed from state E to state B and / or from state E to state C.

  FIG. 7 illustrates an example of a two-pass technique for programming a multi-state memory cell that stores data for two different pages, ie, a lower page and an upper page. Four states are shown: state E (11), state A (10), state B (00), and state C (01). In the state E, both pages store “1”. In the state A, the lower page stores “0”, and the upper page stores “1”. In the state B, both pages store “0”. In the state C, the lower page stores “1” and the upper page stores “0”. Here, a specific bit pattern is assigned to each state, but another bit pattern may be assigned. In the first programming pass, the threshold voltage level of the cell is set according to the bits programmed into the lower logical page. If this bit is a logic "1", this threshold voltage is not changed because it is in the proper state as a result of being previously erased. However, if this programmed bit is a logic “0”, the threshold voltage of this cell is raised to state A as indicated by arrow 230. This completes the first programming pass.

  In the second programming pass, the cell's threshold voltage level is set according to the bits programmed into the upper logical page. If this upper logical page bit stores a logic “1”, no programming is performed. This is because the cell is in one of states E or A, depending on the programming of the lower page bits, both having the upper page bit of “1”. If the upper page bit is logic “0”, the threshold voltage is shifted. If, as a result of the first pass, the cell remains in the erased state E, in the second phase, the cell is programmed so that the threshold voltage moves into state C as indicated by arrow 234. If this cell is programmed to state A as a result of the first programming pass, the memory cell is further programmed in the second pass so that the threshold voltage moves into state B as indicated by arrow 232. . As a result of the second pass, the cell is programmed to the state designated to store the logic “0” of the upper page without changing the data of the lower page.

  In one embodiment, the system can be set up to perform a full sequence write when enough data has been written to fill the entire page. If not enough data has been written to fill the entire page, the programming process can program the lower page with the received data. If further data is received thereafter, the system programs the upper page. In another embodiment, the system starts writing in a mode that programs the lower page, and then full if enough data is subsequently received to fill all (or most) of the memory cells on the word line. It is possible to convert to sequence programming mode. More details of such an embodiment will be discussed on December 14, 2004, by inventors Serge Anatrivic Gorobets and Yan Li, which are hereby incorporated by reference in their entirety. No. 11 / 013,125, entitled “Pipelined Programming of Non-Volatile Memories Using Early Data”.

  8A-8C disclose another process for programming a non-volatile memory that reduces coupling between floating gates. This process performs a write operation on a specific memory cell for a specific page after writing to a memory cell adjacent to the previous page. In one embodiment, each of the non-volatile memory cells stores two bits of data using four data states. For example, assume a state in which states A, B, and C are programmed with state E erased. State E stores data 11. State A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-Gray coding since both bits change between adjacent states A and B. Other methods of encoding data into the physical state of the data can also be used. Each memory cell stores two pages of data. For reference purposes, the data on these pages is called the upper page and the lower page, but different labels can be attached. Referring to state A for the processes of FIGS. 8A-8C, the upper page stores bit 0 and the lower page stores bit 1. Referring to state B, the upper page stores bit 1 and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

  The programming process of FIGS. 8A-8C is a two step process. In the first step, the lower page is programmed. If this lower page is to remain in the data 1 state, the state of the memory cell remains in state E. If this data is to be programmed to 0, the threshold voltage of the memory cell is raised so that the memory cell is programmed to state B '. Accordingly, FIG. 8A shows how a memory cell is programmed from state E to state B '. The state B ′ shown in FIG. 8A is an intermediate state B ′. Therefore, the verification point is indicated as Vvb 'lower than Vvb.

  In one form, when a memory cell is programmed from state E to state B ', its adjacent memory cell on the adjacent word line is programmed for its lower page. After programming that adjacent memory cell, the apparent threshold voltage of the memory cell under consideration in state B 'is raised by the coupling action between the floating gates. As a result, the width of the threshold voltage distribution in the state B ′ is expanded to the distribution shown as the threshold voltage distribution 250 in FIG. 8B. This apparent expansion of the threshold voltage distribution is corrected when programming the upper page.

  FIG. 8C shows the process of programming the upper page. If the memory cell is in erased state E and the upper page remains at 1, this memory cell remains in state E. If the memory cell is in state E and its upper page data is to be programmed to 0, the threshold voltage of this memory cell is raised so that the memory cell is in state A. If the memory cell is in the intermediate threshold voltage distribution 250 and the upper page data is to remain at 1, this memory cell is programmed to the final state B. If the memory cell is in the intermediate threshold voltage distribution 250 and the upper page data is to be data 0, the threshold voltage of this memory cell is raised so that the memory cell enters state C.

  The process shown in FIGS. 8A-8C reduces the coupling effect between floating gates, because the apparent threshold voltage of a given memory cell is only affected when the upper page of an adjacent memory cell is programmed. It is because it is not influenced. Another example of coding in the state is moving from the threshold voltage distribution 250 to the state C when the upper page data is 1, and moving to the state B when the upper page data is 0. 8A-8C show examples of four data states and two pages of data, the concepts taught by FIGS. 8A-8C are based on other embodiments that have more or less than four states or not two pages. Is also applicable. Further details regarding various programming schemes and coupling between floating gates are incorporated herein by reference in their entirety, “Compensating For Coupled Reading Operation Operations Non-Volatile Memory” published April 5, 2005. In US patent application Ser. No. 11 / 099,133 and US Pat. No. 6,657,891 published Dec. 2, 2003 to Shibata et al.

  As described above, coupling is caused by neighboring memory cells, which can affect the apparent threshold voltage of the memory cells. Adjacent memory cells may be on adjacent word lines, on adjacent bit lines, or on adjacent but not adjacent bit lines. The system first determines whether a memory cell (or floating gate) being read is programmed prior to an adjacent memory cell (or floating gate) in the program to cause coupling. Thus, the coupling between adjacent floating memory cells is selectively compensated. If the memory cell being read is programmed prior to the adjacent memory cell, a process can be used that compensates for coupling based on the level of programming of the adjacent memory cell.

  FIG. 9 is a flow chart describing one embodiment of a high level process of programming utilizing timing information. FIG. 10 is a flow chart describing one embodiment of a process of reading and selectively compensating based on it that uses programmed timing information to determine if a coupling may occur. is there.

  In step 300 of FIG. 9, a data write request is received. This request may be received at the controller, state machine or another device. In response to this request, data (information of one or more bits) is written to the flash memory array at step 302. In addition, timing information is stored at step 304. This timing information is customized for the data written in step 302. In one embodiment, the timing information is stored along with the data stored at step 302. In some embodiments, the timing information is stored separately. Steps 302 and 304 may be performed simultaneously or separately. It should be noted that in all flowcharts included with this document, the order of the steps shown in the flowcharts is not necessarily a requirement and in many cases other suitable orders may be performed.

  There are many examples of timing information available. In one embodiment, a time stamp is used. This time stamp may be an absolute time stamp read from the system clock for the host device. In some embodiments, the memory system includes an internal battery and stores its own clock. Some embodiments may use relative time stamps. For example, the system can maintain a cycle count. This cycle count numbers each programming cycle. The cycle count can be maintained by a state machine, controller or another device. The cycle count can be stored as timing information at step 304. If the cycle count of the first data set is greater than the second data set, the first data set is programmed after the second data set. Another embodiment of timing information includes an indication of whether the data was programmed before or after the adjacent memory cell.

  FIG. 10 shows a flowchart for explaining the process of reading data. In step 340, a data read request is received by a controller, state machine, or other device. At step 342, timing information for this data is accessed. This is the timing information stored in step 304. At step 344, it is determined based on this accessed timing information whether a binding may have occurred. In one embodiment, the system determines whether the timing information indicates that the memory cell storing the data associated with the read request has been programmed before the adjacent memory cell. If so, coupling may occur between the memory cells. If the memory cell storing the data associated with the read request is programmed after the adjacent memory cell, there is little possibility of coupling. Even if it is determined in step 344 that a bond may occur, the bond will not actually occur unless the level of programming of the adjacent cell causes the bond. If there is no possibility that a bond will occur (step 346), the read process is performed at step 348 without considering the bond. Note that the read process determines the information stored in the non-volatile memory and notifies this information. If it is determined that a bond is likely to occur (step 346), a read process is performed at step 350 that takes into account the possibility of a bond occurring. In one embodiment, step 350 compensates for coupling if necessary. There are various ways to compensate for coupling between memory cells. Any suitable method can be used as long as it can be used in the technique described in this document.

  FIG. 11 is a book diagram illustrating one embodiment of a page of data. The data page includes a header 380, timing information 382, user data 384, and error correction code (ECC) 386. The header information can include any collection of data known in the art used in the header. In some cases, the header information includes address information, bit and / or sector mapping related information, a count of the number of writes to the sector, and the like. Other information can also be stored in the header. Timing information 382 is the timing information stored in step 304. User data 384 includes the data written in step 302. The ECC 386 includes error correction codes that are well known in the art. Note that some write requests require writing to multiple pages. In this case, more than one set of timing information can be used.

  FIG. 12 is a flowchart illustrating one embodiment of a process for writing data. The process of FIG. 12 is one embodiment that performs steps 302 and 304 of FIG. In step 402 of FIG. 12, in response to receiving the data write request, the system selects an appropriate portion of memory to be programmed. In this operation, a block and / or page and / or sector as a write destination is selected. In one embodiment, data is written to a page in the process of FIG. 12, but this writing causes data to be written to memory cells connected to a common word line. At step 404, the selected memory portion is preprogrammed to prepare for flash memory wear. All memory cells in the selected sector or page are programmed to the same threshold voltage range. Step 404 is optional. In step 406, the programmed memory cell is erased. For example, step 406 may include an operation of moving an old memory cell to state E (see FIGS. 6-8). In some embodiments, step 406 also includes an operation of performing a soft programming process. During this erase process, the threshold voltage of some memory cells may drop to a value lower than the distribution E (see FIGS. 6-8). In the soft programming process, a program voltage pulse is applied to the memory cells so that the threshold voltages of these memory cells rise to within the threshold voltage distribution E.

  In step 408, the system obtains a time stamp. This timestamp can be an absolute time. For example, the memory system may request the date / time from the host via the controller. In the alternative, the memory system includes a battery and an internal clock, which allows the memory system to provide its own time stamp. In some embodiments, the memory system maintains a cycle count. Each time the page is programmed, the cycle count is incremented. The time stamp obtained in step 408 is the current cycle count value. If the cycle count is not an absolute time, it is a relative time. The cycle count can determine which of the two or more pages are programmed first.

  In step 410, the data to be programmed is stored in the appropriate latch / register. In one embodiment, a page of data is programmed using the process of FIG. All of the programmed memory cells are on the same word line. Each memory cell has its own bit line and a set of latches associated with the bit line. These latches store an indication of program schedule data for the associated memory cell. Step 410 also stores time stamp data in the latch associated with the bit line for the memory cell storing the time stamp. In step 412, the magnitude of the first program pulse is set. In the embodiment, the voltage applied to the word line is a set of program pulses, and the magnitude of each pulse is increased by one step size (for example, 0.2 to 0.4 V) from the previous pulse. is there. In step 414, the program count PC is initially set to zero.

  In step 416, a program pulse is applied to the appropriate word line. In step 418, it is verified whether the memory cells on the word line have reached the target threshold voltage level. If all memory cells have reached the target threshold voltage level (step 420), then at step 422, the programming process has been properly completed (status = pass). If the verified memory is not exhaustive, step 424 determines whether the program count PC is less than 20 (or other suitable value). If the program count is not less than 20, the programming process has failed (step 426). If the program count is less than 20, in step 428, the value of the program voltage signal Vpgm of the next pulse is incremented by the step size (eg, 0.3V), and the program count PC is incremented. Note that memory cells that have reached the target threshold voltage are excluded from being programmed for the remainder of the current programming cycle. After step 428, the process of FIG. 12 continues to step 416, where the next program pulse is applied.

  FIG. 13 shows an example of a process for reading data written according to the process of FIG. 12 or according to another process. FIG. 13 is an embodiment of the process of FIG. In step 500 of FIG. 13, a request to read data is received. In step 502, a read process is performed on the requested page. In one embodiment, this process includes reading data from a collection of memory cells connected to the same word line. In some embodiments, there are two word lines adjacent to each word line (eg, one word line above and below, and one word line on the right and left). In step 504, one of the adjacent word lines is read. In step 506, the other adjacent word line is read. In embodiments where only one word line stores the data of interest, step 506 can be skipped. Note that steps 502, 504, and 506 include operations in which relevant timing information is read in addition to user data. That is, the entire page shown in FIG. 11 is read, and this page includes timing information 382. In the embodiment of FIG. 13, the timing information assumes a time stamp of a type such as absolute time or relative time (eg cycle count). At step 508, a determination is made as to whether a join can occur based on a comparison of various time stamps. For example, if the time stamp of the word line being read is after the time stamps of two adjacent word lines, the word line being read is programmed after these two adjacent word lines, and therefore the floating gate It is presumed that there is no possibility of inter-bonding. If the time stamp of the word line being read is before the time stamp of one of the two adjacent word lines, coupling may have occurred. If there is no possibility that coupling has occurred (step 510), the data read in step 502 is stored and reported to the user without compensation for coupling. If it is determined that coupling may occur (510), then at step 514, an additional read process is performed that compensates for coupling at step 514.

  FIG. 14 is a flowchart describing one embodiment of a process for performing a read operation on a page of data (see step 502 in FIG. 13). The embodiment of FIG. 14 relates to the operation of reading a data page from a set of memory cells connected to a common word line. Specifically, the embodiment of FIG. 14 is associated with a multi-state memory that includes four states, such as states E, A, B, and C of FIGS. The technique of FIG. 14 can be applied to other configurations. At step 540, read reference voltage Vra is applied to the appropriate word line associated with this page. In step 542, the bit line associated with this page is sensed to determine whether the addressed memory cell is conducting by applying Vra to its control gate. The conduction of the bit line indicates that the memory cells are turned on, that is, the threshold voltage of these memory cells is less than Vra (for example, state E). In step 544, the bit line detection results are stored in the appropriate latches of these bit lines. At step 546, read reference voltage Vrb is applied to the word line associated with the page being read. At step 548, the bit line is detected as described above. At step 550, the result is stored in the appropriate latch of this bit line. At step 552, read reference voltage Vrc is applied to the word line associated with this page. At step 554, the bit line is detected as described above to determine which memory cell is conducting. In step 556, the result of this sensing step is stored in the appropriate latch of this bit line. In step 558, the data value for each bit line is determined. For example, if a memory cell becomes conductive at Vra, this memory cell is in state E. A memory cell is in state A if it is conducting at Vrb and Vrc but not at Vra. If the memory cell is conducting at Vrc but not conducting at Vra and Vlab, the memory cell is in state B. If the memory cell is not conducting at Vra, Vlab, or Vrc, the memory cell is in state C. In one embodiment, the data value is determined by a processing unit associated with the sense amplifier. In step 560, the determined value is stored in an appropriate latch or other location for each bit line for use by the state machine, controller or other device. In some embodiments, the order of detecting the various levels (Vra, Vlab, Vrc) is different.

  FIG. 15A is a flowchart describing one embodiment of a process for performing an additional read process that compensates for potential coupling. That is, FIG. 15A illustrates one embodiment of step 514 of FIG. In the embodiment of FIG. 15A, it is assumed that there is a possibility of coupling from two adjacent word lines. In step 600, an offset is determined based on one of these adjacent word lines. There are various types of offsets and offset values available. In one embodiment, if the neighboring memory cell is programmed to state A (see FIG. 6), the offset is 0.1 volts, and if the neighboring memory cell is programmed to state B, the offset Is 0.2 volts, and if the adjacent memory cell is programmed to state C, the offset is 0.3 volts. There are also embodiments in which other values and schemes can be used. The system has already read the value stored in the adjacent word line in steps 504 and 506, so it can determine which offset should be used. Determine the set of offsets for each adjacent word line and then sum the two offsets. In this scheme, there are six possible offsets.

  For example, assume that a given memory cell has two neighbors. Program the first neighbor to state B. Program the second neighbor to state C. The offset from the first neighbor is then 0.2 volts, and the offset from the second neighbor is 0.3 volts. The total offset for this particular memory cell is 0.5 volts.

  In some embodiments, the number of potential offsets may be more or less than six. In some embodiments, there is zero volts as an offset. For example, if the adjacent memory cell remains in state E, a zero volt offset can be used.

  In step 602 of FIG. 15A, the memory cell that does not receive the offset stores the data read before step 502. For example, if the cell next to a certain memory cell is in state E, the offset is not used (0V offset). In step 604, the read process is performed using the first offset at the read point. For example, the process of FIG. 14 can be performed. However, instead of using Vra, Vrb and Vrc as read comparison points, the read process uses Vra + first offset, Vrb + first offset and Vrc + first offset. At step 606, data for the bit line associated with the first offset is stored. That is, a memory cell with one neighbor in state E and another neighbor in state A stores the data from step 604. In step 608, the read process is performed using the second offset set at the read comparison point. For example, the process of FIG. 14 is performed with Vra + second offset, Vrb + second offset, and Vrc + second offset relative to the read comparison point. At step 610, the bit line associated with the second offset stores the data from step 608. For example, a memory cell in which one neighbor is in state E and another neighbor is in state B, or both neighbors are in state A, stores data from step 608. In step 612, the read process is performed using the third offset at the read compare point. At step 614, the data for the bit line associated with the third offset is stored. In step 616, the read process is performed using the fourth offset at the read compare point. At step 618, the data from step 616 is stored for the bit line associated with the fourth offset. In step 620, the read process is performed using the fifth offset at the read compare point. At step 622, the data for the bit line associated with the fifth offset is stored. At step 624, a read process is performed using the sixth offset at the read compare point. At step 626, the data from step 624 for the bit line associated with the sixth offset is stored. In one example, the first offset is 0.1 volts, the second offset is 0.2 volts, the third offset is 0.3 volts, and the fourth offset is 0.4 volts. And the fifth offset is 0.5 volts and the sixth offset is 0.6 volts. Further information on compensation for binding was found on April 5, 2005, entitled “Compensating for Coupling During Read Operations on Non-Volatile Memory,” by Jian Chen, which is incorporated herein by reference in its entirety. It can be found in filed US patent application Ser. No. 11 / 099,133.

  The process of FIG. 15A is performed when there is a possibility that a join will occur from two neighbors. If it is determined in step 508 that a join can only occur from one neighbor, the process of FIG. 15B is performed in step 514. In step 630, an offset is determined based on one neighbor. In step 632, the data that has already been read for the bit line with no associated offset is stored in step 632. In step 634, the read process is performed using the first offset at the read compare point. At step 636, the data for the bit line associated with the first offset is stored. In step 638, the read process is performed using the second offset at the read compare point. At step 640, the data for the bit line associated with the second offset is stored. In step 642, the read process is performed using the third offset at the read / compare point. At step 644, the data for the bit line associated with the third offset is stored.

  In another embodiment, rather than storing a time stamp, timing information indicating whether a particular page was programmed after the data on the adjacent word line (or other adjacent) or was previously programmed. Remember. The reason this information only indicates whether this page may have been written before is that this page was written when the neighbor was erased, and the neighbor was never written It is possible.

  FIG. 16 shows another example of the data page. The page shown here includes a header 650, timing information 652, user data 654, timing information 656, and ECC 658. The timing information 652 provides a history related to the previous word line (previous word line history-HPWL). The timing information 656 provides a history related to the next word line (next word line history-HNWL). Regarding the timing information 652 and 656, the use of the terms “previous” and “next” is not intended to represent time or order. Rather, terms such as “previous” and “next” are used to identify each of the two neighbors. For example, referring to FIG. 5, the word line WL2 has at least two neighbors, that is, WL3 and WL1. For the purpose of notation, the adjacent word line closest to the source is called the previous word line, and the adjacent word line closest to the drain is called the next word line. Thus, for WL1, the previous word line is WL1 and the next word line is WL2. The techniques described in this document that determine the likelihood of coupling occurring and, where appropriate, compensate for it can be used with many programming schemes, including programming schemes that program data in a non-predetermined order. That is, in some embodiments, word lines are programmed in the order of WL0 to WL3. In other embodiments, the system randomly selects word lines and programs these word lines in any order. The techniques described in this document can be effective in either embodiment.

  FIG. 17 is a chart for explaining data values that can be stored in the HPWL 652 and the HNWL 656. In one embodiment, the stored data includes 2 bits 11, 10, and 00. If HPWL 652 or HNWL 656 stores 11, the page, sector or word line storing the history is erased. If HPWL 652 or HNWL 656 stores 10, the word line storing the history value is programmed before each adjacent word line. If HPWL 652 or HNWL 656 stores 00, each adjacent word line is programmed before the word line storing the history.

  FIG. 18 is a flow chart describing one embodiment of a process for programming the page shown in FIG. Steps 402 to 406 in FIG. 18 are the same as those in FIG. Step 680 includes an operation of reading the history of the previous word line and determining HPWL. For example, if word line WL2 of FIG. 5 is programmed, the previous word line is WL1. Step 680 includes checking HNWL 656 for WL1 to check if WL1 is erased (HNWL = 11) or programmed (eg, HNWL = 10). Based on HNWL for WL1, HPWL652 for WL2 is determined. In step 682, the history for the next word line is read to determine HNWL. For example, when writing to WL2 in FIG. 5, the system first reads the HPWL of word line WL3, and based on this, determines the value to store as HNWL for word line WL2. In step 684, data for programming header 650, HPWL 652, user data 654, HNWL 656 and EC 658 is stored in the appropriate latch corresponding to each bit line. Steps 412 to 428 in FIG. 17 are the same as those in FIG.

  FIG. 19 is a flow chart describing one embodiment of a process for reading history information from the next or previous word line to determine the appropriate HPWL or HNWL. For example, FIG. 19 provides one embodiment of step 680 or 682. In step 700, the read process is performed by applying a voltage Vra to the appropriate word line. In step 702, the bit line is detected to determine whether the memory cell is turned on or off. Step 702 need only be performed for memory cells that store a history value (HPWL or HNWL). In other embodiments, step 702 may be performed on all memory cells (or other larger sets) connected to the word line. Note that if the history value is 11 (state E), the memory cell is turned on. If not 11, the memory cell storing the history is not turned on for Vra. When the memory cell storing the history is turned on, the memory cell connected to the adjacent word line is erased, so that the memory cell currently programmed is programmed to the adjacent word line. Is presumed to be programmed before If the memory cell storing the history is not turned on, the memory cell on the adjacent word line is already programmed, and the current word line is presumed to be programmed after the adjacent word line is programmed. Is done. The result of step 702 is stored at step 704. Based on whether the memory cell storing history information is turned on or off (step 706), an appropriate value is stored in the history for the current word line. If the neighbor history is 11, step 710 stores the value 10 in the appropriate history value for the current word line, indicating that the current word line has been programmed before the neighbor. If the neighbor history value is 10, the value 00 is stored in the history for the current word line, indicating that the current word line is programmed after the neighbor.

  FIG. 20 is a flow chart describing one embodiment of a read process for reading data programmed according to the process of FIG. Note that FIG. 20 is an alternative embodiment to the process of FIG. In step 800 of FIG. 20, a data read request is received. In step 802, a read process is performed on the word lines without using an offset. For example, the process of FIG. 14 is executed. In step 804, the history for the word line being read is accessed. Note that in one embodiment, at step 802, historical data is read as part of the full page read process. In step 804, this data is accessed by a processor, state machine, or the like. In other embodiments, historical data may be accessed before or after step 802. If HNWL or HPWL is 11 (step 806), it is assumed that the data is erased from the page and that the erased data is reported at step 808. If both HNWL and HPWL are 00, it is assumed that the current page being read is programmed after both neighbors. Thus, in step 810, data is reported without compensating for coupling. If HNWL = 00 and HPWL = 10 (step 812), an additional read operation is performed at step 814 to compensate for coupling from the previous neighbor. If HNWL = 10 and HPWL = 10, then at step 818, an additional read operation is performed to compensate for coupling from both sides. If HNWL = 10 and HPWL = 00, then at step 816, an additional read operation is performed to compensate for the next adjacent coupling.

  FIG. 21 is a flow chart describing one embodiment of a process for performing an additional read operation that compensates for coupling from one neighbor. For example, the process of FIG. 21 can be performed as part of step 814 or step 816 of FIG. In step 904, data is read from the adjacent word line using the read comparison point Vra given to the control gate or word line. In step 906, it is determined whether the entire word line or page has been erased. If all memory cells are in state E, all memory cells are turned on in response to Vra. If all memory cells have been erased (step 906), data is reported in step 908 without performing compensation for coupling from adjacent word lines. If the adjacent word line has not been erased (step 906), the read process is continued, and in step 910, a read operation using the read comparison point Vrb and a read operation using the comparison point Vrc are executed. Based on these three read operations, it is possible to determine the data stored next to it (see discussion of FIG. 14). After step 910, an additional read process is performed that compensates for possible coupling against the data stored next to it. For example, the process of FIG. 15B can be performed.

  FIG. 22 is a flowchart describing one embodiment of a process for performing an additional read operation that takes into account the coupling from two neighbors. For example, the process of FIG. 22 may be performed as part of step 818 of FIG. In step 930, the adjacent word lines are read using the read comparison point Vra. If it is determined that both neighbors have been erased (step 932), data is reported at step 914 without compensating for coupling. If it is determined that one of both neighbors is erased (for example, in response to Vra, all the memory cells of one neighbor word line or page are turned on, and all the memory cells of the other neighbor memory cell are not turned on. ), At step 950, one of the neighbors is subject to a read process performed using read comparison points Vrb and Vrc (similar to step 910 in FIG. 21). In step 952, an additional read process is performed that compensates for the coupling that may occur in step 952 (similar to step 912 in FIG. 21). If it is determined in step 932 that neither neighbor is erased, then in step 936 a read operation is performed on both neighbors using the read comparison points Vrb and Vrc. In step 938, an additional read process that compensates for potential coupling from both word lines is performed and the data is reported. In one embodiment, step 938 includes an act of performing the process of FIG. 15A.

  The technique described in this document that detects the possibility of coupling and compensates for this coupling is applicable to a method that (optionally) compensates for this type of error by detecting the possibility of other types of errors. is there.

  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above disclosure. The described embodiments are best described in terms of the principles of the invention and its practical application, so that others skilled in the art will be able to implement various embodiments suitable for the particular application envisaged, as well as various The present invention has been selected so that the present invention can be used with various modifications. The scope of the present invention is intended to be defined by the appended claims.

It is a top view of a NAND string. It is an equivalent circuit diagram of a NAND string. It is sectional drawing of a NAND string. 1 is a block diagram of a nonvolatile memory system. It is a block diagram of a non-volatile memory array. It is a figure which shows the example of the set of threshold voltage distribution. It is a figure which shows the example of the set of threshold voltage distribution. FIG. 6 illustrates various threshold voltage distributions and illustrates a process for programming a non-volatile memory. FIG. 6 illustrates various threshold voltage distributions and illustrates a process for programming a non-volatile memory. FIG. 6 illustrates various threshold voltage distributions and illustrates a process for programming a non-volatile memory. 6 is a flowchart illustrating one embodiment of a process for programming non-volatile memory. 3 is a flowchart illustrating one embodiment of a process for reading non-volatile memory. It is a block diagram which shows 1 page (or another unit) of data. 6 is a flowchart illustrating one embodiment of a process for programming non-volatile memory. 3 is a flowchart illustrating one embodiment of a process for reading non-volatile memory. 6 is a flow chart describing one embodiment of a process for reading a memory cell on a word line without using an offset to compensate for coupling. 6 is a flow chart describing one embodiment of a process for reading a memory cell on a word line using an offset that compensates for coupling. 6 is a flow chart describing one embodiment of a process for reading a memory cell on a word line using an offset that compensates for coupling. It is a block diagram which shows 1 page (or another unit) of data. It is a chart explaining historical data. 6 is a flowchart illustrating one embodiment of a process for programming non-volatile memory. 6 is a flowchart illustrating one embodiment of a process for determining historical data. 3 is a flowchart illustrating one embodiment of a process for reading non-volatile memory. 6 is a flowchart illustrating one embodiment of a process for performing a read operation that takes into account coupling from adjacent memory cells. 6 is a flowchart illustrating one embodiment of a process for performing a read operation that takes into account coupling from adjacent memory cells.

Claims (37)

A method of operating a non-volatile storage device, comprising:
Accessing access timing information customized for a collection of data stored in one or more non-volatile storage elements;
Performing a step of selectively compensating for one or more potential errors in the data set based on the timing information and reading the data set from the one or more non-volatile storage elements;
Having a method.   2. The one or more potential errors are due to potential coupling that occurs between the one or more non-volatile storage elements and one or more neighboring non-volatile storage elements. The method described. The access step and the read step include
Reading first time data for a word line included in the timing information and associated with the one or more non-volatile storage elements;
Reading second time data for a word line associated with an adjacent non-volatile storage element;
Comparing the first time data with the second time data;
Determining whether an error may occur based on the comparison;
The method of claim 1, comprising: Selectively compensating for the one or more potential errors comprises:
Detecting a non-volatile storage element adjacent to the one or more non-volatile storage elements;
Determining an offset of a read voltage based on the one or more non-volatile storage elements based on information detected from the adjacent non-volatile storage element;
Using the offset to read the one or more non-volatile storage elements;
The method of claim 1, comprising: A memory element includes the one or more non-volatile storage elements and an additional non-volatile storage element storing the timing information;
The timing information includes a first value and a second value;
The first value indicates a programming timing of the one or more non-volatile storage elements for an adjacent first set;
The second value indicates a programming timing of the one or more non-volatile storage elements for an adjacent second set;
The access step and the read step include
Reading data from the memory element connected to a first word line;
The first value indicates that the one or more non-volatile storage elements are programmed after the first adjacent set, and the second value is the one or more non-volatile storages Reporting the data without compensating for one or more potential errors when indicating that an element is programmed after the second neighbor set;
The first value indicates that the one or more non-volatile storage elements may be programmed prior to the first neighboring set, or the second value is the The data may be stored after compensating for one or more potential errors, indicating that one or more non-volatile storage elements may be programmed prior to the second neighbor set. Reporting steps,
The method of claim 1, comprising:   The method of claim 1, further comprising a step of programming the timing information and further programming the data into the one or more non-volatile storage elements. The programming step comprises:
Reading adjacent timing information associated with a set of adjacent non-volatile storage elements;
Determining the timing information customized for the data set based on the neighboring timing information;
The method of claim 6, comprising: The one or more nonvolatile memory elements are multi-state nonvolatile memory elements;
Reading the adjacent timing information includes performing a read operation at one reference voltage level;
The method of claim 7, wherein the step of determining the timing information is based entirely on the read operation at one reference voltage level. The programming step comprises:
Reading first neighboring timing information associated with a first set of neighboring non-volatile storage elements;
Determining a first timing value based on the first neighboring timing information;
Reading second neighboring timing information associated with a second set of neighboring non-volatile storage elements;
Determining a second timing value based on the second neighboring timing information;
Have
The method of claim 6, wherein the timing information associated with the set of adjacent non-volatile storage elements includes the first timing value and the second timing value. The first set of adjacent non-volatile storage elements is connected to a first word line;
The one or more non-volatile storage elements are connected to a second word line adjacent to the first word line;
The second set of adjacent non-volatile storage elements is connected to a third word line adjacent to the second word line;
The one or more potential errors may be a combination of the one or more non-volatile storage elements with the first set of adjacent non-volatile storage elements, and the one or more non-volatile storage elements with an adjacent non-volatile 10. The method of claim 9, wherein the method is caused by coupling with the second set of sexual memory elements. The selectively compensating step comprises:
The one or more non-volatile storage elements when the timing information indicates that the one or more non-volatile storage elements are programmed prior to programming the one or more adjacent non-volatile storage elements; Performing a first compensation process for coupling between a storage element and the one or more neighboring non-volatile storage elements;
Performing a first compensation process when the timing information indicates that the one or more non-volatile storage elements are not programmed prior to programming the one or more adjacent non-volatile storage elements Step without reading,
The method of claim 1, comprising:   The method of claim 1, wherein the selectively compensating comprises selecting whether to use a voltage offset based on the timing information.   The method of claim 1, wherein the timing information includes an absolute time.   The method of claim 1, wherein the timing information includes a cycle count time.   The method of claim 1, wherein the timing information includes programming order information between the one or more non-volatile storage elements and an adjacent non-volatile storage element.   The timing information may be data from which a set of data has been erased, programmed data after programming the adjacent word line, or programmed prior to programming the adjacent word line The method according to claim 1, further comprising a two-bit code indicating whether the data is correct. The data set includes a page of data;
The one or more non-volatile storage elements are connected to a first word line;
The one or more potential errors are one or more non-volatile connected to one or more cells of the one or more non-volatile storage elements and a word line adjacent to the first word line. The method according to claim 1, wherein the method is due to a coupling that occurs with the volatile memory element.   The method of claim 1, wherein the timing information is accessed while reading the data set.   The method of claim 1, wherein the timing information is accessed prior to reading the data set.   The method of claim 1, further comprising receiving a request to read the data set.   The method of claim 1, wherein the one or more non-volatile storage elements are NAND flash memory elements.   The method of claim 1, wherein the one or more non-volatile storage elements are multi-state flash memory elements. A non-volatile storage system,
A plurality of nonvolatile memory elements;
Having one or more management circuits in communication with the non-volatile storage element;
The one or more management circuits;
Accessing timing information customized for a set of data stored in the plurality of non-volatile storage elements;
Performing a step of selectively compensating for one or more potential errors in the data set based on the timing information and reading the data set from the plurality of non-volatile storage elements;
A non-volatile storage system characterized in that   24. The one or more potential errors are due to potential coupling that occurs between the one or more non-volatile storage elements and one or more neighboring non-volatile storage elements. The non-volatile storage system described. The data set is stored in a subset of the plurality of non-volatile storage elements, the subset having an adjacent non-volatile storage element;
The one or more management circuits;
Reading first time data for a word line associated with the subset;
Reading second time data for a word line associated with the adjacent non-volatile storage element;
The one or more management circuits comparing the first time data with the second time data and determining whether an error may occur based on the comparison;
The non-volatile storage system according to claim 23, wherein:   The selectively compensating step includes the step of selecting whether or not to use a voltage offset and the magnitude of the voltage offset to be used during a read process based on the adjacent non-volatile storage element. The non-volatile storage system according to claim 23. The data set is stored in a subset of the plurality of non-volatile storage elements;
The subset has a first neighbor set and a second neighbor set;
A memory element includes an additional non-volatile storage element storing the subset and the timing information;
The timing information includes a first value and a second value;
The first value indicates a programming timing of the subset with respect to an adjacent first set;
The second value indicates the programming timing of the subset relative to an adjacent second set;
The one or more management circuits read data from a memory element connected to a first word line;
The one or more management circuits indicate that the first value indicates that the subset is programmed after the first neighboring set, and the second value indicates that the subset is the Performing the step of reporting the data without compensating for one or more potential errors, if indicated to be programmed after the second neighbor set;
The one or more management circuits indicate that the first value indicates that the subset may be programmed before the first neighboring set, or the second Reporting the data after compensating for one or more potential errors if a value indicates that the subset may be programmed prior to the second neighboring set Run the
The non-volatile storage system according to claim 23. Programming for programming the data set by executing a programming step for programming the data set into a subset of the plurality of non-volatile storage elements, the one or more management circuits performing the step of programming the timing information 24. The step includes reading adjacent timing information and determining the timing information customized for the data set based on the adjacent timing information. The non-volatile storage system described in 1. The one or more nonvolatile memory elements are multi-state nonvolatile memory elements;
The step of reading adjacent timing information comprises performing a read operation at one reference voltage level;
The non-volatile storage system of claim 28, wherein the step of determining the timing information is based on the read operation at one reference voltage level. The data set is stored in a subset of the plurality of non-volatile storage elements, the subset having a non-volatile storage element next thereto;
The step of selectively compensating,
If the timing information indicates that the subset is programmed prior to programming the adjacent non-volatile storage element, the coupling between the subset and the adjacent non-volatile storage element Performing a first compensation process;
Reading without performing a first compensation process if the timing information indicates that the subset has not been programmed prior to programming the neighboring non-volatile storage element;
24. The nonvolatile storage system according to claim 23, comprising:   The non-volatile storage system according to claim 23, wherein the timing information includes any one of absolute time, relative time, and programming order information. The data set includes a page of data;
The data set stored in a subset of the plurality of non-volatile storage elements is connected to a first word line;
The one or more potential errors are due to coupling between the subset and one or more non-volatile storage elements connected to a word line adjacent to the first word line; The non-volatile storage system according to claim 23, wherein:   24. The non-volatile storage system of claim 23, wherein the timing information is accessed while reading the data set.   The non-volatile storage system of claim 23, wherein the one or more management circuits include one or more of a state machine, a decoder, a detection circuit, and a controller.   24. The nonvolatile memory system according to claim 23, wherein the plurality of nonvolatile memory elements are NAND flash memory elements.   24. The nonvolatile memory system according to claim 23, wherein the plurality of nonvolatile memory elements are multi-state flash memory cells.   24. The nonvolatile memory system according to claim 23, wherein the plurality of nonvolatile memory elements have floating gates.

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