JP2010157588A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein, in a conventional MIS transistor having an air gap and a method of manufacturing the same, the air gap is formed around a gate electrode, and thereby a stress insulation film can not be formed adjacently to the gate electrode. <P>SOLUTION: This semiconductor device includes: a gate insulation film 13, a gate electrode 14, a source-drain region 19, a contact plug 22, and a stress insulation film 23. A cavity 24 is formed only in a region located between the gate electrode 14 and the contact plug 22 within the side of the gate electrode 14, and the stress insulation layer 23 is formed on a semiconductor substrate 10 to cover the gate electrode 14, and generates stress to a channel region located immediately below the gate electrode 14 in the semiconductor substrate 10. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a MIS (Metal Insulator Semiconductor) transistor capable of reducing parasitic capacitance and improving driving capability and a manufacturing method thereof.

  In order to improve the operation speed of the semiconductor integrated circuit, it is necessary to reduce parasitic resistance and parasitic capacitance existing in the transistor and the wiring. In particular, in a circuit that performs a complex logic operation, a signal output from one logic gate such as NAND or NOR is often used as an input to a plurality of other logic gates.

The number of input terminals of the next stage logic gate connected to the output side of one logic gate is called fan-out (F / O: fan-out). The load on the output side of the gate increases, and the change rate of the output voltage of the logic gate becomes slower.
The deterioration of the change speed of the output voltage of the logic gate means that the operation speed of the logic circuit becomes slow. To perform a high-speed and complicated operation, the operation of the logic gate when the F / O becomes large It is necessary not to cause speed degradation.

  Most of the load increase due to the increase in F / O is a parasitic capacitance related to the gate electrode of the MIS transistor. The parasitic capacitance related to the gate electrode is the parasitic capacitance between the gate electrode and the substrate and the gate electrode-diffusion region (source / drain region). ) Between the parasitic capacitances.

  However, the parasitic capacitance between the gate electrode and the substrate is the gate insulating film capacitance itself of the MIS transistor, and reducing this parasitic capacitance causes a reduction in the output current of the transistor. Can not be reduced.

  For this reason, it is necessary to reduce the parasitic capacitance between the gate electrode and the diffusion region so that the operation speed of the circuit does not deteriorate even when F / O increases.

  However, the parasitic capacitance between the gate electrode and the diffusion region tends to increase as the distance between the contact plug connected to the source / drain region of the MIS transistor and the gate electrode is reduced with miniaturization. . In order to solve this problem, by providing an air gap with the smallest dielectric constant on the side surface of the gate electrode, the capacitance between the gate electrode and the diffusion region (contact plug) is reduced, and the F / O characteristics are improved, that is, the operation speed is increased. Have been proposed (see, for example, Patent Document 1).

  Hereinafter, a conventional semiconductor device focused on reducing parasitic capacitance between a gate electrode and a diffusion region (contact plug) will be described with reference to FIG. FIG. 7 is a cross-sectional view of a principal part showing the structure of a conventional semiconductor device.

As shown in FIG. 7, an active region 110A surrounded by an element isolation region 111 in a semiconductor substrate 110, a p-type well region 112 formed in the semiconductor substrate 110, and a gate insulating film 113 formed on the active region 110A. A gate electrode 114 formed on the gate insulating film 113, an n-type extension region 115 formed in a region below the gate electrode 114 in the active region 110A, and an n-type extension region 115 in the active region 110A. An n-type source / drain region 116 formed in the outer region, a first interlayer insulating film 117 formed on the n-type source / drain region 116 separated from the side surface of the gate electrode 114, and the gate electrode 114 and the first interlayer insulating film And a second interlayer insulating film 118 formed on 117. An air gap 119 is formed between the gate electrode 114 and the first interlayer insulating film 117.
JP 2000-124454 A

  However, in the conventional MIS transistor having an air gap and the manufacturing method thereof, the air gap is formed so as to surround the entire periphery of the gate electrode. In this configuration, in order to improve carrier mobility, it is technically difficult to apply a so-called strain technique in which a stress insulating film having stress is formed on a semiconductor substrate and stress is applied to the channel region. This is because, in order to effectively apply the stress from the stress insulating film to the channel region, it is necessary to form the stress insulating film in the vicinity of the gate electrode, but the conventional configuration (configuration described in Patent Document 1). Then, since an air gap is provided around the gate electrode, there is a problem that a stress insulating film cannot be formed in the vicinity of the gate electrode.

  In view of the above, an object of the present invention is to provide a semiconductor device including a MIS transistor capable of reducing the parasitic capacitance between the gate electrode and the diffusion region and improving the carrier mobility using a stress insulating film, and a method for manufacturing the semiconductor device. Is to provide.

  A semiconductor device of the present invention includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a source / drain region formed on the side of the gate electrode in the semiconductor substrate, and a source A contact plug is formed on a part of the drain region so as to face a part of the gate electrode, and a stress insulating film is formed on the semiconductor substrate so as to cover the gate electrode. In this semiconductor device, a cavity is provided only in a region located between the gate electrode and the contact plug on the side of the gate electrode, and the stress insulating film is a channel located immediately below the gate electrode in the semiconductor substrate. Stress is applied to the area.

  In such a semiconductor device, since a cavity is provided between the gate electrode and the contact plug on the side of the gate electrode, the parasitic capacitance between the gate electrode and the contact plug can be reduced.

  The cavity is provided only in a region located between the gate electrode and the contact plug on the side of the gate electrode. Accordingly, a stress insulating film can be provided in a region other than the region where the cavity is formed on the side of the gate electrode, so that carrier mobility can be improved.

  The semiconductor device of the present invention may include a metal silicide layer formed on the source / drain region, and the contact plug may be connected to the metal silicide layer.

  In the semiconductor device of the present invention, the contact plug is preferably provided so as to penetrate the stress insulating film.

  In a preferred embodiment described later, the semiconductor device is formed in contact with the sidewall so as to cover the gate electrode on the semiconductor substrate and the sidewall having an L-shaped cross section formed on the side surface of the gate electrode. And a base insulating film. The stress insulating film is formed in contact with the base insulating film, and the cavity is formed between the base insulating film formed on the side surface of the gate electrode via the sidewall and the contact plug. . In this case, the cavity is surrounded by the stress insulating film, and the dimension of the cavity in the gate width direction is the same as or smaller than the dimension of the contact plug in the gate width direction.

  In another preferred embodiment described later, the semiconductor device includes a sidewall having an L-shaped cross section formed on the side surface of the gate electrode. The stress insulating film is formed in contact with the sidewall except for the region where the cavity is formed, and the cavity is formed between the sidewall formed on the side surface of the gate electrode and the stress insulating film. ing.

  In the semiconductor device of the present invention, the source / drain region is preferably an n-type diffusion region, and the stress insulating film preferably generates a tensile stress in the channel length direction in the channel region.

  The first method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a gate electrode on the gate insulating film, and a gate electrode in the semiconductor substrate. A step (c) of forming a source / drain region under the side of the gate electrode, a step (d) of forming a contact plug on a part of the source / drain region so as to face a part of the gate electrode, and a step (d) And (e) forming a stress insulating film on the semiconductor substrate. Step (e) includes a step of forming a stress insulating film and providing a cavity only in a region located between the gate electrode and the contact plug on the side of the gate electrode. The stress insulating film generates stress on a channel region located immediately below the gate electrode in the semiconductor substrate.

  In such a manufacturing method, the stress insulating film is provided on the semiconductor substrate in the step (e). Therefore, carrier mobility can be improved.

  In the step (f), since a cavity is provided between the gate electrode and the contact plug, it is possible to reduce the parasitic capacitance between the gate electrode and the contact plug.

  Further, since the cavity is provided only between the gate electrode and the contact plug on the side of the gate electrode, the gate electrode and the contact plug are hardly affected by the tensile stress applied to the channel region by the stress insulating film. The parasitic capacitance between the two can be reduced.

  In the first method for fabricating a semiconductor device of the present invention, the step (d) includes a step (d1) of forming a protective film on the semiconductor substrate and a contact hole provided through the protective film on the source / drain region. It is preferable to include a step (d2) of forming a contact plug therein and a step (d3) of removing the protective film after the step (d2).

  In the first method for manufacturing a semiconductor device of the present invention, after the step (b), before the step (d), a step of forming a sidewall having an L-shaped cross section on the side surface of the gate electrode (f And a step (g) of forming a base insulating film so as to cover the gate electrode on the semiconductor substrate and to be in contact with the sidewall after the step (f). Then, it is preferable to form a stress insulating film in contact with the base insulating film.

  The second method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a gate electrode on the gate insulating film, and a gate electrode in the semiconductor substrate. A step (c) of forming a source / drain region under the side of the step, a step (d) of forming a protective sidewall having thermal decomposition characteristics on the side surface of the gate electrode after the step (c), and a step (d) ) After the step (e) of forming a stress insulating film on the semiconductor substrate, and after the step (e), the contact plug that penetrates the stress insulating film on a part of the source / drain region and faces a part of the gate electrode The step (f) of forming a cavity and the step (g) of forming a cavity by thermally decomposing the protective sidewall by heat treatment after the step (f) are provided. Step (d) includes a step of forming a protective sidewall only in a region located between the gate electrode and the contact plug. In the step (g), a cavity is provided only in a region located between the gate electrode and the contact plug on the side of the gate electrode, and the stress insulating film is a channel region located immediately below the gate electrode in the semiconductor substrate. Produces stress.

  In such a manufacturing method, the same effect as that obtained by the first method for manufacturing a semiconductor device of the present invention can be obtained.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, a cavity is provided only in a region located between the contact plugs connected to the gate electrode and the source / drain region on the side of the gate electrode, and the cavity is formed in the other region. A stress insulating film is formed without intervention. According to this configuration, the parasitic capacitance between the contact plugs connected to the gate electrode and the source / drain region by the cavity can be reduced, and the carrier mobility can be improved by the stress insulating film.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. 1A to 1C are diagrams showing a semiconductor device according to a first embodiment of the present invention, where FIG. 1A is a plan view, and FIG. 1B is a line IB-IB ′ in FIG. (C) is sectional drawing in the IC-IC 'line | wire in (a).

  As shown in FIGS. 1B and 1C, the semiconductor device according to the present embodiment includes an active region 10A surrounded by an element isolation region 11 in the semiconductor substrate 10 and a semiconductor substrate 10 including the active region 10A. A p-type well region 12 formed to a position deeper than the isolation region 11, a gate insulating film 13 formed on the active region 10A, and a gate electrode 14 made of a polysilicon film formed on the gate insulating film 13; An offset spacer 15 having an I-shaped cross section formed on the side surface of the gate electrode 14, an n-type extension region 16 formed in a region below the side of the gate electrode 14 in the active region 10A, and the gate electrode 14 The inner side wall 17a having an L-shaped cross section formed on the side surface of the active region 10A via the offset spacer 15 and the inner side wall in the active region 10A. An n-type source / drain region 19 formed in a region on the outer lower side of the ruler 17a, and a base insulating film 20 formed on the semiconductor substrate 10 so as to cover the gate electrode 14 and to be in contact with the inner sidewall 17a A stress insulating film 23 formed on the base insulating film 20 and an interlayer insulating film 25 formed on the stress insulating film 23 are formed so as to cover the active region 10A. Then, as shown in FIGS. 1A and 1B, a contact hole 18 provided on the n-type source / drain region 19 through the stress insulating film 23 and the base insulating film 20, and in the contact hole 18 And a contact plug 22 made of a conductive material that is buried and electrically connected to the n-type source / drain region 19. Then, in the side of the gate electrode 14, the region where the gate electrode 14 and the contact plug 22 face each other, that is, between the base insulating film 20 formed on the side surface of the gate electrode 14 and the contact plug 22. As shown in FIGS. 1A and 1B, the stress insulating film 23 is not completely filled in the region to be formed, and a cavity 24 surrounded by the stress insulating film 23 is formed. . On the other hand, in the region of the side of the gate electrode 14 where the gate electrode 14 and the contact plug 22 do not face each other, that is, in the region where the contact plug 22 is not formed on the side of the gate electrode 14, FIG. ), The cavity 24 is not formed, and the stress insulating film 23 is formed on the side surface of the gate electrode 14 in contact with the base insulating film 20 formed via the inner side wall 17a. The stress insulating film 23 generates a tensile stress in the gate length direction (channel length direction) in the channel region. The dimension of the cavity 24 in the gate width direction is the same as or smaller than the dimension of the contact plug 22 in the gate width direction.

  According to the semiconductor device of the first embodiment, since the cavity 24 is formed between the gate electrode 14 and the contact plug 22, the parasitic capacitance between the gate electrode 14 and the contact plug 22 can be reduced. Can do. Further, since the stress insulating film 23 is formed on the active region 10A so as to cover the gate electrode 14 on the semiconductor substrate 10, the gate length direction of the channel region located immediately below the gate electrode 14 in the active region 10A Since a tensile stress is applied to the electron mobility, the electron mobility can be improved and the driving force of the n-type MIS transistor can be increased. At this time, since the cavity 24 is formed only between the gate electrode 14 and the contact plug 22, it hardly affects the application of tensile stress to the channel region by the stress insulating film 23.

  2 (a) to (c), FIGS. 3 (a) to (c) and FIGS. 4 (a1) to (c1) and (a2) to (c2) are semiconductors according to the first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of an apparatus. 2 (a) to (c), FIGS. 3 (a) to (c) and FIGS. 4 (a1) to (c1) are cross-sectional views taken along line IB-IB ′ in FIG. 1 (a). (A2)-(c2) is sectional drawing in IC-IC 'line in Fig.1 (a).

  First, as shown in FIG. 2A, in the trench, for example, by STI (Shallow Trench Isolation) method, an upper portion of a semiconductor substrate 10 made of silicon (Si) having a main surface with a (100) plane orientation is formed in the trench. An element isolation region 11 in which an insulating film is buried is selectively formed. Thereafter, a p-type well region 12 is formed by injecting a p-type impurity such as B (boron) into the semiconductor substrate 10 by lithography and ion implantation. Thereafter, for example, a silicon oxynitride film having a thickness of 2 nm and a polysilicon film having a thickness of 100 nm are formed on the entire surface of the semiconductor substrate 10. Thereafter, the polysilicon film and the silicon oxynitride film are sequentially patterned by photolithography and dry etching, and the silicon oxynitride film is formed on the active region 10A formed of the semiconductor substrate 10 surrounded by the element isolation region 11. A gate electrode 14 made of a gate insulating film 13 and a polysilicon film is formed (step (a) and step (b)).

Next, after a silicon oxide film having a thickness of 5 nm is formed on the entire surface of the semiconductor substrate 10, the silicon oxide film is etched back to thereby form an offset spacer having an I-shaped cross section on the side surface of the gate electrode 14. 15 is formed. Thereafter, phosphorus, which is an n-type impurity, is implanted into the active region 10A with a dose of 4 × 10 ¹⁴ ions / cm ^{2 using} the gate electrode 14 and the offset spacer 15 as a mask to form the n-type extension region 16.

  Next, for example, a silicon oxide film having a thickness of 5 nm and a silicon nitride film having a thickness of 30 nm are sequentially deposited on the entire surface of the semiconductor substrate 10 by, for example, a CVD (Chemical Vapor Deposition) method. By etching back the laminated film made of the nitride film, the sidewall 17 is formed on the side surface of the gate electrode 14 via the offset spacer 15. The sidewall 17 includes an inner sidewall 17a having an L-shaped cross section made of a silicon oxide film, and an outer sidewall 17b made of a silicon nitride film formed on the inner sidewall 17a (step ( f)).

Thereafter, using the gate electrode 14, the offset spacer 15 and the sidewall 17 as a mask, phosphorus, which is an n-type impurity, is ion-implanted into the active region 10A at a dose amount of 4 × 10 ¹⁵ ions / cm ² , and then heat treatment is performed. A type source / drain region 19 is formed (step (c)).

  Next, as shown in FIG. 2 (b), the outer side wall 17b of the side walls 17 is selectively removed, leaving only the inner side wall 17a.

  Next, as shown in FIG. 2C, a base insulating film 20 made of a silicon nitride film having a thickness of 2 nm to 5 nm is formed on the entire surface of the semiconductor substrate 10 (step (g)), and then the base insulating film A protective film 21 made of a silicon oxide film is formed on 20 (step (d1)). Thereafter, the upper surface of the protective film 21 is planarized by CMP (Chemical Mechanical Polishing).

  Next, as shown in FIG. 3A, a contact hole 18 that penetrates the base insulating film 20 and the protective film 21 and reaches the n-type source / drain region 19 is formed in the base insulating film 20 and the protective film 21.

  Next, as shown in FIG. 3B, a conductive material is formed on the protective film 21 including the contact hole 18, and then unnecessary conductive material on the protective film 21 is removed by CMP to thereby remove the contact hole. A contact plug 22 is formed in 18 (step (d2)). The contact plug 22 has a configuration in which a conductive film made of tungsten is formed on a barrier film made of TiN, for example.

  Next, as shown in FIG. 3C, the protective film 21 is selectively removed using the base insulating film 20 as an etching stopper (step (d3)). As a result, the contact plug 22 remains on the n-type source / drain region 19 in a protruding structure. Here, if a PSG (phosphorus doped silicon glass) film, for example, is used as the protective film 21, it can be selectively removed from the base insulating film 20 and the contact plug 22 by wet etching with a diluted hydrofluoric acid solution. At this time, the element isolation region 11 is not etched because it is covered with the base insulating film 20.

  Next, as shown in FIGS. 4A1 and 4A2, a stress insulating film 23 made of a silicon nitride film and having a thickness of about 50 nm is formed on the entire surface of the semiconductor substrate 10 (step (e)). At this time, since the gap between the gate electrode 14 and the contact plug 22 is narrow, the region between the gate electrode 14 and the contact plug 22 is not completely filled with the stress insulating film 23, and a cavity 24 is formed. The distance between the gate electrode 14 and the contact plug 22 is preferably 50 nm or less in order to form the cavity 24. Further, the stress insulating film 23 can be formed, for example, by forming a silicon nitride film containing hydrogen and then performing a UV curing process, and releases the hydrogen in the silicon nitride film to contract the silicon nitride film itself. As a result, a tensile stress is generated in the channel region in the gate length direction. Here, the stress insulating film 23 may have a thickness of about 50 nm by repeating a process of forming a silicon nitride film having a thickness of 5 nm and a UV curing process, for example.

  Next, as shown in FIGS. 4B1 and 4B2, an interlayer insulating film 25 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 10 on which the stress insulating film 23 is formed. Thereafter, the upper surface of the interlayer insulating film 25 is planarized by CMP.

  Next, as shown in FIGS. 4C1 and 4C2, the interlayer insulating film 25 and the stress insulating film 23 formed on the contact plug 22 are polished and removed by CMP to remove the upper surface of the contact plug 22. To expose. At this time, the polishing removal by the CMP method is preferably performed under the condition that the polishing rate of the interlayer insulating film 25 and the polishing rate of the stress insulating film 23 are approximately the same.

  The semiconductor device having the N-type MIS transistor according to this embodiment can be manufactured through the above steps.

  In this embodiment, the metal silicide film is not formed, but a metal silicide film may be formed on the gate electrode 14 and the n-type source / drain region 19 as necessary. For example, in FIG. 2A, after forming the n-type source / drain region 19, a metal film made of nickel (Ni), cobalt (Co), platinum (Pt) or the like is deposited on the semiconductor substrate 10, A metal silicide layer may be formed on each of the gate electrode 14 and the n-type source / drain region 19 by annealing the deposited metal film. In this case, the n-type source / drain region 19 and the contact plug 22 are connected via a metal silicide layer.

  According to the manufacturing method of the semiconductor device of the first embodiment, the cavity 24 is formed in a self-aligned manner only between the gate electrode 14 and the contact plug 22, and on the active region 10 </ b> A so as to cover the gate electrode 14. A stress insulating film 23 can be formed. Thereby, the parasitic capacitance between the gate electrode 14 and the contact plug 22 can be reduced, and a tensile stress is applied to the channel length direction of the channel region located immediately below the gate electrode 14 in the active region 10A. A stress insulating film 23 that can be formed can be formed.

  Further, according to the manufacturing method of the semiconductor device of the first embodiment, since the distance between the gate electrode 14 and the contact plug 22 is narrow, specifically, the distance is 50 nm or less, so that the gate electrode 14 and the contact are contacted. A cavity 24 can be formed in a self-aligning manner with the plug 22. Therefore, the parasitic capacitance between the gate electrode and the contact plug can be reduced by a relatively simple method with almost no influence on the application of tensile stress to the channel region by the stress insulating film. Furthermore, it can contribute to miniaturization of the semiconductor device.

(Second Embodiment)
A semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. 5A to 5C are views showing a semiconductor device according to the second embodiment of the present invention, where FIG. 5A is a plan view and FIG. 5B is a VB-VB ′ line in FIG. (C) is sectional drawing in the VC-VC 'line in (a).

  As shown in FIGS. 5B and 5C, the semiconductor device according to the present embodiment includes an active region 10 </ b> A surrounded by the element isolation region 11 in the semiconductor substrate 10, and an element on the semiconductor substrate 10 including the active region 10 </ b> A. A p-type well region 12 formed to a position deeper than the isolation region 11, a gate insulating film 13 formed on the active region 10A, and a gate electrode 14 made of a polysilicon film formed on the gate insulating film 13; An offset spacer 15 having an I-shaped cross section formed on the side surface of the gate electrode 14, an n-type extension region 16 formed in a region below the side of the gate electrode 14 in the active region 10A, and the gate electrode 14 The inner side wall 17a having an L-shaped cross section formed on the side surface of the active region 10A via the offset spacer 15 and the inner side wall in the active region 10A. An n-type source / drain region 19 formed in a region on the outer lower side of the tool 17a, a stress insulating film 23 formed on the active region 10A so as to cover the gate electrode 14, and a stress insulating film 23. An interlayer insulating film 25 is formed. 5A and 5B, a contact hole 18 provided on the n-type source / drain region 19 through the stress insulating film 23 and the interlayer insulating film 25, and in the contact hole 18 And a contact plug 22 made of a conductive material that is buried and electrically connected to the n-type source / drain region 19. In the side of the gate electrode 14, the region where the gate electrode 14 and the contact plug 22 face each other, that is, the region located between the gate electrode 14 and the contact plug 22, has an inner sidewall 17 a and stress. A cavity 31 sandwiched between the insulating films 23 is formed. On the other hand, a cavity 31 is formed in a region of the side of the gate electrode 14 where the gate electrode 14 and the contact plug 22 do not face each other, that is, in a region where the contact plug 22 is not formed on the side of the gate electrode 14. The stress insulating film 23 is formed in contact with the inner side wall 17a. The stress insulating film 23 generates a tensile stress in the gate length direction in the channel region. The cavity 31 is a cavity formed by thermally decomposing a polymer having thermal decomposition characteristics.

  According to the semiconductor device of the second embodiment, since the cavity 31 is formed between the gate electrode 14 and the contact plug 22, the parasitic capacitance between the gate electrode 14 and the contact plug 22 can be reduced. Can do. Further, since the stress insulating film 23 is formed on the active region 10A so as to cover the gate electrode 14 on the semiconductor substrate 10, the gate length direction of the channel region located immediately below the gate electrode 14 in the active region 10A Since a tensile stress is applied to the electron mobility, the electron mobility can be improved and the driving force of the n-type MIS transistor can be increased. At this time, since the cavity 31 is formed only between the gate electrode 14 and the contact plug 22, it hardly affects the application of tensile stress to the channel region by the stress insulating film 23.

  6A1 to 6D1 and 6A2 to 6D2 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 6A1 to 6D1 are cross-sectional views taken along the line VB-VB 'in FIG. 5A, and FIGS. 6A2 to 6D2 are VC-VC' lines in FIG. 5A. FIG.

  First, the structure as shown in FIG. 2B is formed by the same steps as those in FIGS. 2A and 2B.

  Next, as shown in FIGS. 6A1 and 6A2, a protective material having thermal decomposition characteristics, for example, a polymer film that is thermally decomposed by heat treatment at about 400 ° C. is formed on the entire surface of the semiconductor substrate 10. Thereafter, anisotropic etching of the polymer film is performed to form a protective sidewall 30 made of the polymer film on the side surface of the gate electrode 14 via the inner sidewall 17a (step (d)).

  Next, as shown in FIGS. 6B1 and 6B2, the portion located between the contact plug 22 and the gate electrode 14 formed in a later step, that is, as shown in FIG. 5A. The protective sidewall 30 is left in the part where the cavity 31 is formed in the process, and the protective sidewall 30 in the other part is removed. For example, an unnecessary protective sidewall is removed by covering the portion where the protective sidewall 30 remains with a resist. Thereafter, a stress insulating film 23 made of a silicon nitride film and having a thickness of about 50 nm is formed on the entire surface of the semiconductor substrate 10 (step (e)). At this time, the stress insulating film 23 can be formed by, for example, forming a silicon nitride film containing hydrogen and then performing a UV curing process, and the silicon nitride film itself is contracted by releasing hydrogen in the silicon nitride film. As a result, a tensile stress is generated in the channel length direction in the channel region. Thereafter, an interlayer insulating film 25 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 10 on which the stress insulating film 23 is formed, and then the upper surface of the interlayer insulating film 25 is planarized by CMP. As a result, the stress insulating film 23 is formed on the side surface of the gate electrode 14 via the protective sidewall 30 as shown in FIG. A portion where the wall 30 is not formed is in contact with the inner side wall 17a formed on the side surface of the gate electrode 14 as shown in FIG.

  Next, as shown in FIGS. 6C1 and 6C2, the contact reaching the n-type source / drain region 19 through the stress insulating film 23 and the interlayer insulating film 25 through the stress insulating film 23 and the interlayer insulating film 25. Hole 18 is formed. Thereafter, a conductive material is formed on the interlayer insulating film 25 including the contact hole 18, and then an unnecessary conductive material on the interlayer insulating film 25 is removed by CMP to form a contact plug 22 in the contact hole 18. (Step (f)). The contact plug 22 has a configuration in which a conductive film made of tungsten is formed on a barrier film made of TiN, for example.

  Next, as shown in FIGS. 6 (d1) and (d2), the semiconductor substrate 10 is heat-treated at about 450 ° C. (step (g)), so that the protective sidewall 30 having thermal decomposition characteristics is heated. The cavity 31 is formed by being decomposed.

  The semiconductor device having the N-type MIS transistor according to this embodiment can be manufactured through the above steps.

  In this embodiment, no metal silicide film is formed. However, as in the first embodiment, a metal silicide film is formed on the gate electrode 14 and the n-type source / drain region 19 as necessary. Also good.

  According to the method of manufacturing the semiconductor device of the second embodiment, after forming the protective sidewall 30 having thermal decomposition characteristics only between the gate electrode 14 and the contact plug 22, the active region is covered so as to cover the gate electrode 14. The stress insulating film 23 is formed on 10A, and then the protective sidewall 30 can be pyrolyzed to form the cavity 31. Thereby, the parasitic capacitance between the gate electrode 14 and the contact plug 22 can be reduced, and a tensile stress is applied to the channel length direction of the channel region located immediately below the gate electrode 14 in the active region 10A. A stress insulating film 23 that can be formed can be formed.

  In the first and second embodiments, the description has been given using the n-type MIS transistor. However, even if the p-type MIS transistor is used, the same effect can be obtained by using a film having compressive stress as the stress insulating film. I can do it.

  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device including a MIS transistor that requires reduction of parasitic capacitance and improvement of driving capability, and its manufacture.

(A)-(c) shows the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the IB-IB 'line in (a), (c) ) Is a cross-sectional view taken along line IC-IC ′ in FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A1)-(c1) and (a2)-(c2) are sectional drawings which show the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in order of a process, (a1)-(c1) is FIG. It is sectional drawing in the IB-IB 'line in (a), (a2)-(c2) is sectional drawing in the IC-IC' line in Fig.1 (a). (A)-(c) shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the VB-VB 'line | wire in (a), (c) ) Is a cross-sectional view taken along the line VC-VC ′ in FIG. (A1) to (d1) and (a2) to (d2) are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps, and (a1) to (d1) are FIGS. It is sectional drawing in the VB-VB 'line in (a), (a2)-(d2) is sectional drawing in the VC-VC' line in Fig.5 (a). It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

10 Semiconductor substrate
10A active region
11 Device isolation region
12 p-type well region
13 Gate insulation film
14 Gate electrode
15 Offset spacer
16 n-type extension region
17 sidewall
17a Inside sidewall
17b Outer side wall
18 Contact hole
19 n-type source / drain region
20 Underlying insulating film
21 Protective film
22 Contact plug
23 Stress insulation film
24 cavity
25 Interlayer insulation film
30 Protective sidewall
31 cavity

Claims (12)

A gate insulating film formed on a semiconductor substrate;
A gate electrode formed on the gate insulating film;
A source / drain region formed under the side of the gate electrode in the semiconductor substrate;
A contact plug formed on a portion of the source / drain region so as to face a portion of the gate electrode;
A stress insulating film formed on the semiconductor substrate so as to cover the gate electrode;
Of the sides of the gate electrode, a cavity is provided only in a region located between the gate electrode and the contact plug,
The stress insulating film is a semiconductor device in which stress is generated in a channel region located immediately below the gate electrode in the semiconductor substrate. The semiconductor device according to claim 1,
A metal silicide layer formed on the source / drain region;
The semiconductor device, wherein the contact plug is connected to the metal silicide layer. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the contact plug is provided through the stress insulating film. The semiconductor device according to any one of claims 1 to 3,
A sidewall having an L-shaped cross-section formed on the side surface of the gate electrode;
A base insulating film formed on and in contact with the sidewall so as to cover the gate electrode on the semiconductor substrate;
The stress insulating film is formed in contact with the base insulating film,
The semiconductor device, wherein the cavity is formed between the base insulating film formed on the side surface of the gate electrode via the sidewall and the contact plug. The semiconductor device of any one of Claims 1-4 WHEREIN:
The semiconductor device, wherein the cavity is surrounded by the stress insulating film. The semiconductor device according to any one of claims 1 to 5,
The dimension of the cavity in the gate width direction is the same as or smaller than the dimension of the contact plug in the gate width direction. The semiconductor device according to any one of claims 1 to 3,
A cross-sectional shape formed on a side surface of the gate electrode and an L-shaped side wall;
The stress insulating film is formed in contact with the sidewall except the region where the cavity is formed,
The cavity is a semiconductor device formed between the sidewall formed on a side surface of the gate electrode and the stress insulating film. The semiconductor device according to any one of claims 1 to 7,
The source / drain region comprises an n-type diffusion region,
The stress insulating film generates a tensile stress in the channel length direction in the channel region. A step (a) of forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film (b);
Forming a source / drain region under the side of the gate electrode in the semiconductor substrate (c);
Forming a contact plug on a portion of the source / drain region so as to face a portion of the gate electrode;
A step (e) of forming a stress insulating film on the semiconductor substrate after the step (d);
The step (e) includes a step of forming the stress insulating film and providing a cavity only in a region located between the gate electrode and the contact plug on the side of the gate electrode,
The method of manufacturing a semiconductor device, wherein the stress insulating film generates stress on a channel region located immediately below the gate electrode in the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 9,
The step (d) includes a step (d1) of forming a protective film on the semiconductor substrate, and a step of forming the contact plug in a contact hole provided through the protective film on the source / drain region. (D2) The manufacturing method of a semiconductor device provided with the process (d3) which removes the said protective film after the said process (d2). In the manufacturing method of the semiconductor device according to claim 9 or 10,
After the step (b), before the step (d), a step (f) of forming a sidewall having an L-shaped cross section on the side surface of the gate electrode, and after the step (f) And (g) forming a base insulating film on the semiconductor substrate so as to cover the gate electrode and to be in contact with the sidewall,
In the step (e), the stress insulating film is formed on and in contact with the base insulating film. A step (a) of forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film (b);
Forming a source / drain region under the side of the gate electrode in the semiconductor substrate (c);
After the step (c), a step (d) of forming a protective sidewall having thermal decomposition characteristics on the side surface of the gate electrode;
A step (e) of forming a stress insulating film on the semiconductor substrate after the step (d);
After the step (e), forming a contact plug that penetrates the stress insulating film on a part of the source / drain region and faces a part of the gate electrode;
After the step (f), a step (g) of forming a cavity by thermally decomposing the protective sidewall by heat treatment,
The step (d) includes a step of forming the protective sidewall only in a region located between the gate electrode and the contact plug,
In the step (g), a cavity is provided only in a region located between the gate electrode and the contact plug on the side of the gate electrode,
The method of manufacturing a semiconductor device, wherein the stress insulating film generates stress on a channel region located immediately below the gate electrode in the semiconductor substrate.

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