JP2016072532A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a distance to an end of a control electrode far from a pull-up electrode is short and which causes less non-uniform operation in a plane of a semiconductor substrate.SOLUTION: A MOSFET comprises: a control electrode in a groove; an auxiliary electrode connected to a source electrode in the groove; a first upper electrode connected to one of the control electrode and the auxiliary electrode on a semiconductor substrate; and a second upper electrode connected to the other of the control electrode and the auxiliary electrode on the semiconductor substrate. In plan view of the MOSFET: the groove extends from one end to the other end of the semiconductor substrate; and the first upper electrode is provided to extend in a direction crossing a direction where the groove extends so as to cross the groove; and the second upper electrode is provided to extend in a direction crossing the direction where the groove extends so as to sandwich the first upper electrode.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation.

  As a switching element (power semiconductor element) that performs a switching operation with a large current, a trench gate type power MOSFET is widely used.

  A trench gate type power MOSFET generally includes a first conductivity type drain region, a first conductivity type drift region formed on the first conductivity type drain region, and a first conductivity type drift region. A second conductive type base region selectively formed on the first conductive type, a first conductive type source region selectively formed on the second conductive type base region, and drift from the source region through the base region A trench reaching the region, a gate electrode formed on the sidewall of the trench facing the base region via an insulating film, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region Is provided. However, such a trench gate type power MOSFET has a large area between the gate electrode and the drift region, so that the capacitance between the gate and the drain increases. As a result, there is a problem that the mirror charging period at the on / off time becomes long, and high-speed switching characteristics cannot be obtained. Therefore, in order to reduce the gate-drain capacitance, the gate electrodes in the trench are arranged on the left and right sides, the area where the drift region and the control electrode are opposed to each other is reduced, and the region below the control electrode facing the drift region in the trench is Patent Document 1 discloses an example in which an auxiliary electrode electrically connected to a source electrode is provided in a region. Further, Patent Document 2 discloses an example in which an auxiliary electrode electrically connected to a source electrode is disposed so as to protrude downward from the control electrode.

  According to the structure disclosed in Patent Document 2, the area where the drift region and the gate electrode face each other is reduced, and the auxiliary electrode electrically connected to the source electrode between the left and right gate electrodes arranged in the trench is gated. By projecting downward from the electrode, a depletion layer in the drift region by the auxiliary electrode can be generated in a wide range. Further, the impurity concentration in the drift region can be increased, and the on-resistance of the semiconductor element can be reduced.

JP 2002-083963 A JP 2007-165380 A

  Since the semiconductor devices of Patent Documents 1 and 2 have an auxiliary electrode connected to the source electrode in addition to the gate electrode in the trench, compared to a general trench gate type power MOSFET, the gate electrode and the auxiliary electrode The problem is how to lift For example, in the technique described in Patent Document 1, an example is shown in which an auxiliary electrode and a gate electrode are lifted on a semiconductor substrate and connected to an upper electrode. Here, the auxiliary electrode is lifted on the semiconductor substrate from one end side of the semiconductor substrate and connected to the upper electrode, while the gate electrode is lifted on the semiconductor substrate from the other end side of the semiconductor substrate and is connected to the upper electrode. Connected. In such a case, there is a problem in that the distance from the upper electrode to the end of the gate electrode becomes long, and uneven operation occurs in the plane of the semiconductor substrate. Furthermore, there is a problem that the resistance value of the gate electrode increases.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
A semiconductor device of the present invention includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region disposed on the first semiconductor region, and a first conductivity disposed on the second semiconductor region. A semiconductor substrate including a third semiconductor region of the mold, a groove reaching the first semiconductor region from the third semiconductor region through the second semiconductor region, and a control electrode disposed on the side surface of the groove via an insulating film An auxiliary electrode disposed in the groove via a control electrode and an insulating film, a first upper electrode electrically connected to one of the control electrode and the auxiliary electrode, disposed on the semiconductor substrate, and a control electrode Or a second upper electrode electrically connected to the other of the auxiliary electrodes and disposed on the semiconductor substrate, and in a plan view, the groove extends from one end of the semiconductor substrate to the other end. The first upper electrode extends in the direction intersecting with the direction in which the groove extends and intersects with the groove. The second upper electrode is provided so as to extend in a direction intersecting with a direction in which the groove extends and to sandwich the first upper electrode.

  Since this invention is comprised as mentioned above, the resistance of a control electrode can be reduced and the nonuniform operation in the surface of a semiconductor substrate can be suppressed.

1 is a cross-sectional view of a semiconductor device 1. 1 is a plan view of a semiconductor device 1. FIG. It is sectional drawing cut | disconnected by II-II of the semiconductor device 1 of FIG. FIG. 3 is a cross-sectional view taken along III-III of the semiconductor device 1 of FIG. 2. It is sectional drawing cut | disconnected by IV-IV of the semiconductor device 1 of FIG. FIG. 4 is a cross-sectional view of the semiconductor device 1 of FIG. 2 cut along VV.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.

FIG. 1 is a sectional view of the semiconductor device (MOSFET) 1 shown in FIG. The semiconductor device 1 is a trench gate type element formed in a semiconductor substrate 2 made of silicon. In this semiconductor substrate 2, an n ⁻ layer 20 serving as a drift region and a p ⁻ layer 30 serving as a base region are sequentially formed on an N ⁺ layer 10 serving as a drain region. On the surface side of the semiconductor substrate 2, a groove (trench) 100 penetrating the p ⁻ layer 30 is formed. A plurality of grooves 100 are formed in parallel with each other so as to extend in a direction perpendicular to the paper surface in FIG. 1. In FIG. 1, only a part of the cross-sectional view of the semiconductor device 1 is shown with one groove 100 as a center. .

On the surface side of the semiconductor substrate 2, n ⁺ layers 40 serving as source regions are formed on both sides of the trench 100. An insulating film 71 is formed on the inner surface (side surface and bottom surface) of the groove 100.

First, the gate electrode 60 is provided along the left and right side walls of the groove 100 facing the p ⁻ layer 30. However, each of the left and right gate electrodes 60 is connected by a first upper electrode (bus line) described later. The gate electrode 60 is made of, for example, conductive polycrystalline silicon doped at a high concentration.

On the other hand, between the left and right gate electrodes 60 in each groove 100, the auxiliary electrode 50 separated (insulated) from the left and right gate electrodes 60 is formed to extend below the gate electrode 60. Since the insulating film 71 is also formed on the bottom surface of the groove 100, the auxiliary electrode 50 is also insulated from the underlying n ⁻ layer 20. In this state, an interlayer insulating film 70 is formed in the trench 100 so as to cover the left and right gate electrodes 60 and to separate the auxiliary electrode 50 from the gate electrodes 60 on both sides thereof.

In this state, a source electrode (first main electrode) 90 is formed on the surfaces of the semiconductor substrate 2 and the interlayer insulating film 70. With the above configuration, the source electrode 90 is connected to the p ⁻ layer 30 and the n ⁺ layer 40 on the surface of the semiconductor substrate 2. The source electrode 90 and the gate electrode 60 are insulated by the interlayer insulating film 70. On the other hand, a drain electrode (second main electrode) 80 electrically connected to the N ⁺ layer (drain region) 10 is formed on the entire back surface of the semiconductor substrate 2.

  In this structure, the gate electrode 60 is not formed on the bottom surface side of the groove 100 but is divided on both sides of the groove 100. Furthermore, since the auxiliary electrode 50 has the same potential (ground potential) as the source electrode 90, the gate-drain capacitance Cgd (feedback capacitance) is reduced.

  Further, since the auxiliary electrode 50 is disposed so as to extend deeper than the gate electrode 60, the depletion layer on the bottom side of the groove 100 can be well spread and the breakdown voltage can be improved.

FIG. 2 is a plan view of the semiconductor device 1. 1 is a cross-sectional view taken along the line II of FIG. As shown in the plan view of the semiconductor device 1 in FIG. 2, a plurality of grooves 100 extending from one end 2 a side of the semiconductor substrate 2 toward the other end 2 b side are provided. The end portions of the plurality of grooves 100 include connection grooves 101 that connect the end portions of the plurality of adjacent grooves 100. On the central side sandwiched between one end and the other end of the semiconductor substrate 2, it intersects with the groove 100 and extends from the groove 100 toward the adjacent groove 100 over the plurality of grooves 100. A first upper electrode (bus line) 300 is disposed. The first upper electrode 300 is electrically connected to the gate electrode 60. A region between the first upper electrode 300 and the one end 2a side of the semiconductor substrate 2 so as to be separated from the first upper electrode 300 and sandwich the first upper electrode 300, and from the first upper electrode 300 A second upper electrode 200 is disposed in each of the regions between the other end 2b side of the semiconductor substrate 2. The second upper electrode is connected to the auxiliary electrode 50 on the connection groove 101 or on the semiconductor substrate 2 closer to the end of the semiconductor substrate 2 than the connection groove 101. Further, each of the second upper electrodes 200 is electrically connected to the source electrode 90 described above, but the second upper electrode 200 and the source electrode 90 may be integrated. The second upper electrode 200 includes the connection groove 101 and extends to the end side of the semiconductor substrate 2 from the connection groove 101 in the extending direction of the groove 100.

The n ⁺ layer 40 is formed on the left and right sides along the groove 100 in the region between the first upper electrode 300 and the connection groove 101. Note that the gate electrode 60 is not provided in the connection groove 101 and in the groove 100 immediately below the first upper electrode 300. Further, the n ⁺ layer 40 is not provided in the vicinity of the opening of the connection groove 101 and in the vicinity of the opening of the groove 100 immediately below the first upper electrode 300. As a result, an inactive region immediately below the first upper electrode 300 becomes an inactive region, and the one upper end 2a side of the semiconductor substrate 2 and the other end of the semiconductor substrate 2 are sandwiched so as to sandwich the first upper electrode 300 in plan view. An active region is formed on the end 2b side. According to the semiconductor device 1, since only one upper electrode 300 is provided on the center side of the semiconductor substrate 2, a semiconductor device with a small number of inactive regions can be provided. Therefore, a semiconductor device with low on-resistance can be provided. Furthermore, since the distance between the end of the gate electrode extending to the one end 2a side and the other end 2b side of the semiconductor substrate 2 and the first upper electrode 300 is short, the gate resistance can be reduced, Uneven operations can be suppressed in the plane of the semiconductor substrate.

The trench 100 has a gate electrode 60 and an auxiliary electrode 50. The gate electrode 60 is provided in a region from the first upper electrode 300 to the connection groove 101, and is not provided in the connection groove 101. Thereby, the width of the connection groove 101 can be reduced, and the semiconductor device can be miniaturized. The groove width refers to the dimension of the groove perpendicular to the length direction of the groove in which the groove extends. Further, it is desirable that the gate electrode 60 extends closer to the first upper electrode 300 than the n ⁺ layer 40.

On the other hand, the auxiliary electrode 50 extends in the groove 100, and also extends in the connection groove 101 on the one end 2 a side and the other end 2 b of the semiconductor substrate 2. Therefore, the auxiliary electrode 50 has a T shape at the connection portion between the groove 100 and the connection groove 101. Since the auxiliary electrode 50 is also provided in the connection groove 101, the auxiliary electrode 50 in the adjacent groove 100 is electrically connected. Therefore, the auxiliary electrode 50 does not have to be pulled up to the semiconductor substrate 2 with respect to each groove 100.

2, a cross section taken along II-II including the first upper electrode 300 is shown in FIG. 3, and a cross section taken along III-III is shown in FIG. According to the cross section of the semiconductor element 1 shown in FIGS. 3 and 4, the p ⁻ layer 30 and the n ⁺ layer 40 are not disposed under the first upper electrode 300. Furthermore, as shown in FIG. 3, the left and right gate electrodes 60 in each groove 100 are connected to each other so as to straddle the auxiliary electrode 50 above the groove 100 and are pulled up on the semiconductor substrate 2. Further, the left and right gate electrodes 60 are connected to the first upper electrode 300 on the interlayer insulating film 70 through holes provided in the interlayer insulating film 70 on the semiconductor substrate 2.

FIG. 4 is a cross section cut along the extending direction of the auxiliary electrode 50. In FIG. 4, the p ⁻ layer 30 and the gate electrode 60 are not visible on the cross sectional view because of the cross section cut along the auxiliary electrode 50 of the groove 100, but for the sake of explanation, the p ⁻ layer 30 is indicated by a one-dot broken line. The electrode 60 is indicated by a wavy line. As shown in FIG. 4, the end of the p ⁻ layer 30 extends to the first upper electrode 300 side of the gate electrode 60 in the trench 100. Further, the p ⁻ layer 30 gradually becomes shallow under the first upper electrode 300, and the p ⁻ layer 30 is not provided at least in a partial region under the first upper electrode 300, so The n− region 20 is exposed on the upper surface. The auxiliary electrode 50 extends from one connection groove 101 to the other connection groove 101, and is also disposed under the first upper electrode 300.

The gate electrode 60 is not provided under the first upper electrode 300, and the first portion of the region between the first upper electrode 300 and one end 2 a of the semiconductor substrate 2, and the first upper electrode It is divided and arranged in a second portion of the region between the electrode 300 and the other end 2 b of the semiconductor substrate 2. In the gate electrode 60, the first portion of the gate electrode 60 and the second portion of the gate electrode 60 are pulled up on the surface of the semiconductor substrate 2 via an insulating film immediately below or near the outside of the first upper electrode 300. Further, the first portion of the gate electrode 60 and the second portion of the gate electrode 60 lifted on the surface of the semiconductor substrate 2 are interlayer-insulated through holes provided in the interlayer insulating film 70 on the surface of the semiconductor substrate 2. The first upper electrode 300 on the film 70 is connected.

The connection between the auxiliary electrode 50 and the second upper electrode 200 will be described. A cross-sectional view of the semiconductor device 1 including the auxiliary electrode 50 in the connection groove 101 and cut along IV-IV along the extending direction of the auxiliary electrode 50 is shown in FIG. 5, and the auxiliary electrode 50 extending from the groove 100 to the connection groove 101 is shown in FIG. FIG. 6 shows a cross-sectional view of the semiconductor device 1 cut along VV along the extending direction. 5 and 6 are cross-sectional views on the other end 2b side of the semiconductor substrate 2, but the cross-sectional view on the one end 2a side of the semiconductor substrate 2 is bilaterally symmetric with respect to FIGS. There is a similar structure.
As shown in FIGS. 5 and 6, the n ⁻ layer 20 is provided on the N ⁺ layer 10, and the auxiliary electrode 50 is provided in the connection groove 101 reaching the n ⁻ layer 20 via the insulating film 71. The auxiliary electrode 50 is lifted on the semiconductor substrate 2 via an insulating film, and the lifted electrode is connected to the second upper electrode 200 via a hole provided in the interlayer insulating film 70. As shown in the sectional view of FIG. 6, the second upper electrode 200 includes the connection groove 101, and the second upper electrode 200 is wider than the connection groove 101 in the extending direction of the groove 100. Furthermore, the second upper electrode 200 is formed to the end (2a, 2b) side of the semiconductor substrate 2 with respect to the connection groove 101 or the groove 100 in the extending direction of the groove 100. Thus, the second upper electrode 200 functions as a field plate, and the breakdown voltage on the end side of the semiconductor device can be improved. Although the p ⁻ layer 30 is not shown outside the connection groove 101 in FIG. 6, the p ⁻ layer 30 extends to the outside of the connection groove 101 (on the end (2a, 2b) side of the semiconductor substrate 2). It may be formed.

Further, since the auxiliary electrode 50 is also provided in the connection groove 101, the auxiliary electrode 50 in the adjacent groove 100 is electrically connected. Accordingly, the auxiliary electrode 50 does not have to be lifted up to the semiconductor substrate 2 with respect to each groove 100, and may be lifted only at one location with respect to the plurality of grooves 100.
Further, the connection groove 101 may not be provided. In this case, the lifting of the gate electrode 60 is the same as in the above embodiment, but the auxiliary electrode 50 is pulled up on the semiconductor substrate 2 at the end of the semiconductor substrate 2 or at the end of the semiconductor substrate 2 relative to the end of the groove 100. The upper electrode 200 is connected.

In addition, in the trench 100, the auxiliary electrode 50 is provided between the left and right gate electrodes 60, and the auxiliary electrode 50 is shown as an example of a trench gate type power MOSFET extending below the gate electrode 60. A similar structure can be used in a trench gate type power MOSFET having a gate electrode 60 insulated in the groove 100 and an auxiliary electrode 50 insulated between the gate electrode 60 and the bottom surface of the groove 100. It is clear that the effects of
In the above description, the semiconductor device is a trench gate type power MOSFET. However, a similar structure can be used for a trench gate type element such as an IGBT. That is, a groove is formed on the surface of the semiconductor substrate, a gate electrode and an auxiliary electrode that are in contact with the oxide film formed on the inner surface thereof are provided, and the first main electrode formed on the surface side of the semiconductor substrate and the back surface side are formed. The same structure can be adopted as long as the operating current flowing between the second main electrode and the second main electrode is controlled by the voltage applied to the gate electrode. it is obvious.

  In addition, an example in which the second upper electrode 200 is connected to the auxiliary electrode 50 and the first upper electrode 300 is connected to the gate electrode 60 has been shown, but the second upper electrode 200 is connected to the gate electrode 60, One upper electrode 300 may be connected to the auxiliary electrode 50.

In addition, each of the above configurations is an n-channel element, but it is apparent that a p-channel element can be similarly obtained by reversing the conductivity type (p-type and n-type). In this case, the acceptor concentration shown in FIG. 1 is the donor concentration in the n ⁻ layer corresponding to the p ⁻ layer 23. In addition, it is obvious that the above-described structure and manufacturing method can be realized without depending on the material constituting the semiconductor substrate, the gate electrode, and the like, and the same effect can be obtained.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 10 N ⁺ layer 20 n ⁻ layer 30 p ⁻ layer 40 n ⁺ layer 50 Auxiliary electrode 60 Gate electrode 70 Interlayer insulating film 80 Source electrode (first main electrode)
90 Drain electrode (second main electrode)
100 groove 101 connection groove 200 second upper electrode 300 first upper electrode

Claims (8)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region;
A third semiconductor region of a first conductivity type disposed on the second semiconductor region;
A semiconductor substrate comprising:
A trench reaching from the third semiconductor region to the first semiconductor region through the second semiconductor region;
A control electrode disposed on the side surface of the groove via an insulating film;
An auxiliary electrode disposed in the groove via the control electrode and an insulating film;
A first upper electrode electrically connected to one of the control electrode or the auxiliary electrode and disposed on the semiconductor substrate;
A second upper electrode electrically connected to the other of the control electrode or the auxiliary electrode and disposed on the semiconductor substrate;
With
In plan view,
The groove extends from one end of the semiconductor substrate to the other end,
The first upper electrode extends in a direction intersecting with the direction in which the groove extends, and is provided so as to intersect with the groove.
The second upper electrode extends in a direction intersecting with the direction in which the groove extends, and is provided so as to sandwich the first upper electrode. The first upper electrode is connected to the control electrode;
The semiconductor device according to claim 1, wherein the second upper electrode is connected to the auxiliary electrode. In plan view,
3. The semiconductor device according to claim 1, wherein the third semiconductor region is not formed immediately below the first upper electrode. In plan view,
The second semiconductor region is not formed in at least a part immediately below the first upper electrode, and at least a part of the upper surface of the semiconductor substrate is the upper surface of the first semiconductor region. The semiconductor device according to claim 1. In plan view,
5. The semiconductor device according to claim 1, wherein the first upper electrode is provided between the active region and the active region.   The end portion of the second upper electrode in the direction in which the groove extends extends closer to the end portion side of the semiconductor substrate than the end portion of the groove. Semiconductor device. The ends of the adjacent grooves are connected by connecting grooves,
The semiconductor device according to claim 1, wherein the auxiliary electrodes in the adjacent grooves are connected via auxiliary electrodes in the connection grooves.   The semiconductor device according to claim 7, wherein a width of the connection groove is narrower than a width of the groove.

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