JP2868118B1 - Liquid crystal display - Google Patents

Abstract

A circuit for inputting a signal divided by a sample-and-hold circuit to a source driver, the input level of an input video signal VINA between pixels whose division is switched,
A large potential difference is not caused by wiring resistance. [Configuration] Assume that the frequency division number is 8. Switch 7 (k), capacitor 8 (k), output buffer 9 (k) (k = 1, 2,
, 8) constitute a sample and hold circuit. In synchronization with VINA, the switches are set to 7 (1), 7
(3), 7 (5), 7 (7), 7 (8), 7 (6), 7
Perform sample hold by operating in the order of (4) and 7 (2). Thereby, from the sample hold circuit, 1,
The output signals VO are output in the order of 8, 2, 7, 3, 6, 4, and 5. This order is returned to the original order by the order changing means 10 and then output to the source driver.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having an active matrix type liquid crystal display panel, and more particularly to a liquid crystal display device having a sample and hold circuit for sampling and holding an analog signal and outputting after dividing the frequency.

[0002]

2. Description of the Related Art As a conventional example of a liquid crystal display device having an active matrix type liquid crystal display panel, FIG. As shown in FIG. 5, in the liquid crystal display panel 1, the maximum number of pixels in the horizontal direction is X and the maximum number of pixels in the vertical direction is Y with respect to the number of pixels which is the minimum unit of image display. A pixel at a specific position (x, y) is represented by D (x, y). FIG.
5 is an equivalent circuit diagram schematically showing the liquid crystal display panel 1 in FIG. 5, where a liquid crystal capacitance in a specific pixel D (x, y) is C (x, y), and a switching transistor is M
(X, y).

In FIG. 6, SD (m) (where m =
.., X) are source lines for supplying output data to a specific pixel D (x, y), GD (n) (where n =
.., Y) are gate lines for controlling the switching transistor M (x, y) of the specific pixel D (x, y). In such a liquid crystal display panel 1, the arrangement of pixels in the horizontal direction is collectively called a line.

In FIG. 5, an operation clock (CLK), a horizontal synchronizing signal (HS), a vertical synchronizing signal (VS) and the like are supplied to a controller 2 for generating display timing of the entire liquid crystal display panel as an external image signal. Are supplied, and the shift register 3, the source driver 4, the gate driver 5
And outputs the CLK and control signals T1 to T3 shown in FIG. The shift register 3 receives the CL from the controller 2.
A frequency division operation is performed by K and T1. Assuming that the frequency division number is n, the shift register 3 sequentially generates pulses SW1 to SWn for causing the sample and hold circuit to perform the frequency division operation (see FIG. 7). The source driver 4 has a function of sequentially holding the output data VO1 to VOn divided by n,
It has a function of converting this into a voltage level applied to the liquid crystal. The gate driver 5 includes gate lines GD (1) to GD (G).
It has a function of sequentially driving D (Y) and a function of converting CLK to a voltage level at which the switching transistor of the liquid crystal display panel can be turned on and off.

[0005] The analog video signal VIN input to the liquid crystal display device is γ-converted via the conversion circuit 6 and converted to VIN.
A is output to a sample and hold circuit having a control switch 7, a hold capacitor 8, and an output buffer 9 as A. Control signal SW sequentially output from shift register 3
1 to SWn, the control switches 7 (1) to 7 (n)
, And the analog video signal VINA is held by the hold capacitors 8 (1) to 8 (n), and output as output signals VO1 to VOn via buffers 9 (1) to 9 (n) forming an operational amplifier. This output signal VO1
.About.VOn is output to the source driver 4. However, the number of frequency divisions is limited to about 2 to 32 due to problems such as chip size. In a liquid crystal display panel, usually (640 to 128
0) × RGB three color source driver signal lines, and the above operation is repeated until all data for one line is completely stored in the source driver 4 by the control signal T2 from the controller 2.

When the data of one line has been held, the gate driver 5 is turned on by the control signal T3 output from the controller 2, and M (1) in FIG.
To X, y) are turned on, the voltage of the analog video signal is applied to the pixels D (1 to X, y) of the desired line y, and the liquid crystal capacitance C shown in FIG.
(1 to X, y) are held. Hereinafter, by repeating the same operation for each line, the liquid crystal display panel 1
Is displayed.

[0007]

However, when the data thus divided is sampled and held and the data is held in the source driver, a voltage drop occurs due to wiring resistance or the like, so that the adjacent driver is not connected. There is a problem that a portion where the deviation of the voltage drop is large between pixels is generated, and display quality is deteriorated. FIG. 8 is a circuit diagram of a sample-and-hold portion when the frequency division number is n = 8, for specifically explaining such a problem. Here, the input of the adjacent control switches 7 (1) to 7 (8) in the adjacent sample and hold blocks 1 to 8 is caused by the resistance component of the wiring or the like.
Assuming that a potential difference of V occurs, in the example of FIG. 8, the input voltage becomes 7 between (1) and (8) of the sample and hold block.
A potential difference of ΔV is generated. Here, considering a case where the input data is simply a constant voltage, FIG.
As shown in the figure, the voltage value held in the source driver 4 has a potential difference of ΔV between the blocks, and VO1 and VO8
Between them, a potential difference of 7 ° V occurs. As a result, the data to be held in the source driver 4 does not have a constant voltage, and a potential difference of ΔV occurs between adjacent pixels.

For example, in a liquid crystal display device, as shown in FIG. 9, when a frequency dividing operation is repeated to hold one line of data, this potential difference becomes between VO1 and VO8 at the time of frequency division writing switching. Is the largest potential difference of 7 △ V and is held in the source driver. When this line writing operation is repeated for one screen, it appears as a bright line or a dark line in the vertical direction. Is significantly impaired. An object of the present invention is to solve the above-mentioned problems of the conventional example, and an object of the present invention is to provide a liquid crystal display panel with a gray scale voltage in which a potential difference caused by a resistance drop between adjacent pixels is reduced. Thus, high quality image display can be performed.

[0009]

According to the present invention, there is provided a liquid crystal display device comprising the steps of: applying an input image signal corresponding to each pixel to a corresponding pixel as a pixel signal voltage; A liquid crystal display device for driving the display device includes a data driver for driving a display data line while holding an input image signal for one horizontal line, and a signal input line, and one end of the signal input line for n pixels. A sample and hold circuit that receives a continuous input image signal and samples and holds n input image signals corresponding to each pixel by n hold means; and the n input image signals input to the sample and hold circuit But one from the end,
control means for driving the sample-and-hold circuit so as to be arranged in the order of n, 2, (n-1), 3, (n-2), and the output signal of the sample-and-hold circuit is 1, 2, 3,.
And an output order rearranging means for rearranging the data in the normal order and outputting the data to the data driver.

Further, according to the present invention, in a liquid crystal display device for driving liquid crystal by applying an input image signal input corresponding to each pixel to a corresponding pixel as a pixel signal voltage, one horizontal line corresponds to one pixel. A data driver for holding the input image signal and driving the display data line, and a signal input line.
A sample-and-hold circuit that receives continuous input image signals for pixels and samples and holds n input image signals corresponding to each pixel by n-hold means; and the n input signals to be input to the sample-and-hold circuit The samples are arranged such that the image signals are arranged in the order of 1, 2, 3,... From the center toward one end, and in the order of n, n-1, n-2,. Control means for driving a hold circuit, and an output signal of the sample and hold circuit,
A liquid crystal display device, comprising: an output order changing means for rearranging the data driver in the order of 1, 2, 3,.

[0011]

FIG. 1 is a block diagram for explaining an embodiment of the present invention. In FIG. 1, the same parts as those of the conventional example shown in FIG. 5 are denoted by the same reference symbols, and the duplicate description will be omitted. The difference of the liquid crystal display device according to the present invention from the conventional example is that the shift register 3
The output signals VO1 to VO8 output by the sample and hold blocks (1) to (8) are provided between the point that the order of the control switches controlled by the pulses generated from This means that the order changing means 10 for changing the order of the VO8 is inserted.

The analog video signal V output from the conversion circuit 6
When INA is input to one end of the signal input line of the sample and hold circuit as shown in FIG.
, SW1, SW3, SW5,..., SWn-1, SWn, and S, as shown in FIG.
Wn-2,..., SW2 (where n is an even number, and if n is an odd number,
SW1, SW3, SW5, ..., SWn-2, SWn, S
Wn-1,..., SW2). As a result, the video signals held by each sample and hold block are VO1, VOn, VO2, VO from the upper part of FIG.
(N-1), VO3, VO (n-2), ..., VOk (k
When k is an even number, k = n / 2 + 1, and when n is an odd number, k = (n + 1) / 2). This order is
By the order changing means 10, the order of the output signals S1, S2, S3,..., Sn to the source driver 4 and the original analog video signal VINA is returned. As shown in FIG. 1, the potential difference between the signals input between the control switches 7 (1) and 7 (2) is 2ΔV corresponding to the resistance voltage drop at the signal input line (signals having the same voltage are input). As is).
Similarly, between the control switches 7 (2) -7 (3),
The potential difference between (n) -7 (n-1) is also 2 [Delta] V, and the potential difference between 7 (n) -7 (1) during frequency switching is [Delta] V.
V. That is, with the circuit configuration shown in FIG. 1, the potential difference between adjacent pixels can be suppressed to a maximum of 2 V. Thereby, it is possible to prevent a bright line or a dark line from being vertically formed on the display screen due to a voltage drop due to wiring resistance.

When the analog video signal VINA is input to the middle point of the signal input line of the sample-and-hold circuit (see FIG. 4), the output order of the control signal of the pulse output from the shift register 3 to the control switch 7 is as follows. , N are even numbers, SWn / 2, SW (n / 2-1),..., SW1, SWn, SW (n−1),.
2 + 1). That is, the first pulse is input to the n / 2-th control switch, and the n-th pulse is (n / 2 +
1) It is input to the control switch. When n is an odd number, SW {(n + 1) / 2},..., SW1, SWn, SW (n−1),.
+1) / 2 + 1} in this order. When the order of the input destinations of the output pulses of the shift register 3 is set in this manner, the video signal input to the control switch 7 moves from the center of the sample and hold circuit toward one end in the order of 1, 2,.
3, ..., from the center toward the other end, n,
n-1, n-2,... As a result, the potential difference due to the resistance drop between adjacent pixels is at most ΔV,
This is further improved over the example of FIG.

When the analog video signal VINA is input to the middle point of the signal input line of the sample and hold circuit, the output order of the control signal of the pulse output from the shift register 3 to the control switch 7 is determined by SW1, SW2, SW3, ..., SW (n-1), SW
(In this case, the setting of the shift register 3 is the same as that shown in FIG. 5). in this way,
Even when the output destination of the shift register is set, the potential difference between adjacent pixels is at most ΔV. In this case, it is not necessary to provide a means for changing the order between the sample and hold circuit and the source driver.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. In this embodiment, the frequency division number is set to 8
Then, the output order of the control signal of the output pulse of the shift register 3 to the control switch 7 in FIG. 1 is SW1, SW3, SW5, SW7, SW8, SW6, S
W4 and SW2. Thus, the control switch 7 (1) has the first, 7 (2) has the eighth, 7 (3) has the second, 7
(4) 7th, 7 (5) 3rd, 7 (6)
6th, 7 (7) fourth, 7 (8) 5th
The third video signal is input. Accordingly, the output signals VO1 to VO8 shown in FIG. 2 are output from the output buffers 9 (1) to 9 (8), respectively. As shown in FIG. 2, the output signals VO1 to VO8 are permuted in the permutation unit 10 and output to the source driver as output signals S1 to S8. FIG.
7 is a graph showing voltage waveforms of output signals VO1 to VO8 from the sample and hold circuit in the first embodiment. As shown in FIG. 3, the potential difference between the transition from VO4 to VO5 and the transition from VO8 to VO1 is ΔV
However, the potential difference between other adjacent pixels is 2 △
V. That is, the conventional example shown in FIG.
The potential difference between the existing pixels can be reduced to 2 V at the maximum. The order changing means 10 can be provided in a layout on a chip on which a sample-hold circuit is mounted, can be provided on a wiring path to a source driver, or can be provided in a source driver. Similar effects can be obtained.

Second Embodiment A second embodiment of the present invention will be described with reference to FIG. In this embodiment, the analog video signal VINA is input to the middle point of the input line of the sample and hold circuit. Also in the present embodiment, the frequency division number is n = 8. In the case of the present embodiment, the input order of the output pulse of the shift register 3 to the control switch 7 in FIG. 1 is SW4, SW3, SW2, SW1, SW8, S
W7, SW6, and SW5. As a result, the control switch 7 (1) has the fourth switch, and the control switch 7 (2) has the third switch 7 (7).
(3) second, 7 (4) first, 7 (5)
8th, 7 (6) 7th, 7 (7) 6
The fifth video signal is input to the seventh, 7 (8). Accordingly, the output signals VO1 to VO8 shown in FIG. 4 are output from the output buffers 9 (1) to 9 (8), respectively.
Is output. As shown in FIG. 4, the output signals VO1 to VO8 are permuted by the permutation unit 10 and output to the source driver as output signals S1 to S8. According to the present embodiment, VO4 to VO5
When moving to VO8 and when moving from VO8 to VO1,
The potential difference becomes 0, and the potential difference between other adjacent pixels becomes ΔV. That is, according to the present embodiment, the maximum potential difference between the pixels can be reduced to ΔV. Further, according to the present embodiment, not only the potential difference between pixels can be suppressed low, but also the absolute value of the voltage drop due to the wiring resistance can be reduced to about 3ΔV, so that the display quality can be further improved. it can.

[0017]

As described above, in the liquid crystal display device of the present invention, in a circuit for performing frequency division by sampling and holding, by changing the input order in the input circuit, the voltage drop due to the wiring resistance between adjacent pixels can be achieved. The output order is changed so that the output order is returned to the initial state in the output circuit, so that the output between adjacent outputs at the time of frequency division switching due to wiring resistance or the like is performed. The relative output error can be kept small, and the display quality of the liquid crystal display device can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for describing an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a first embodiment of the present invention.

FIG. 3 is a waveform diagram of a voltage held in a source driver 4 by the circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional liquid crystal display device.

6 is an equivalent circuit diagram of the liquid crystal display panel 1 shown in FIG.

FIG. 7 is a timing chart of a control signal when the frequency division number is n.

FIG. 8 is a circuit diagram for explaining a problem of the conventional example.

FIG. 9 is a waveform diagram of a voltage held in a source driver 4 by a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Controller 3 Shift register 4 Source driver 5 Gate driver 6 Conversion circuit 7 Control switch 8 Hold capacitor 9 Output buffer 10 Order changing means

Claims (2)

(57) [Claims] 1. A liquid crystal display device that drives a liquid crystal by applying an input image signal input corresponding to each pixel to a corresponding pixel as a pixel signal voltage to hold an input image signal for one horizontal line. A data driver for driving the display data line, and a signal input line,
A sample and hold circuit for receiving a continuous input image signal of n pixels at one end of the signal input line, and sampling and holding n input image signals corresponding to each pixel by n hold means; The n input image signals input to the hold circuit are 1, n, 2,.
Control means for driving the sample-and-hold circuit so as to be arranged in the order of (n-1), 3, and (n-2), and output signals of the sample-and-hold circuit are arranged in the order of 1, 2, 3,. A liquid crystal display device comprising: an output order changing means for changing the output order to the data driver. 2. A liquid crystal display device that drives a liquid crystal by applying an input image signal input corresponding to each pixel to a corresponding pixel as a pixel signal voltage to hold an input image signal for one horizontal line. A data driver for driving the display data line, and a signal input line,
A sample-and-hold circuit for receiving a continuous input image signal of n pixels at a center point of the signal input line, and sampling and holding n input image signals corresponding to each pixel by n hold means; The n input image signals input to the hold circuit are arranged in the order of 1, 2, 3,... From the center toward one end, and n, n−1, n− from the center toward the other end. Control means for driving the sample and hold circuit so as to be arranged in the order of 2,..., And output order permutation for rearranging the output signals of the sample and hold circuit in the forward order of 1, 2, 3,. A liquid crystal display device comprising: