JP2835254B2 - Display device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a matrix type display device such as a liquid crystal display device, an electroluminescence display, a plasma display, etc., and more particularly to a signal electrode driving circuit.

[0002]

2. Description of the Related Art First, an equivalent circuit diagram of a display panel 8 in an active matrix type liquid crystal display device 4 and a block diagram of a driving circuit around the display panel 8 will be described with reference to FIG.

Active matrix type liquid crystal display device 4
Is a technique in which an active element such as a thin film transistor 9 is provided at each intersection of a matrix to control a voltage applied to a liquid crystal to perform a display. A moving image (hereinafter, referred to as an “AV image”) on a small color television or a notebook is displayed. It is applied as a display element for displaying a still image (hereinafter, referred to as an “OA image”) on a book personal computer.

The display panel 8 has a structure in which a liquid crystal is sandwiched between two sheets of glass. An XY matrix electrode is formed on one glass and a common electrode is formed on the other glass. A plurality of signal electrodes 10 are arranged in parallel as conducting electrodes arranged in the vertical direction. Similarly, a plurality of scanning electrodes 11 are arranged in parallel as conducting electrodes arranged in the horizontal direction.

The thin film transistor 9 is provided at the intersection of each signal electrode 10 and each scanning electrode 11, and its gate g
Are connected to the scanning electrode 11, and the source s thereof is connected to the signal electrode 10. Each pixel electrode 12 is connected to the drain d of the thin film transistor 9. The signal input to the gate g from the scanning electrode 11 is “Hi”
When the level becomes gh "level, the source s and the drain d are brought into a conductive state, a voltage based on a video signal input from the signal electrode 10 to the source s is applied to the pixel electrode 12, and the light transmittance of the liquid crystal layer changes. The image is displayed.

The scan electrode drive circuit 5 outputs a "High" level signal to one scan electrode 11 during one horizontal scan period, and outputs a "Low" level signal to the other scan electrodes 11. The scanning electrode 11 that outputs a “High” level signal is switched sequentially from above at regular intervals. Thin film transistor 9 connected to one and the same scan electrode 11
High levels are simultaneously input to the gates g of the thin film transistors 9 simultaneously, and the source s and the drain d of the thin film transistors 9 are conducted.

[0007] The signal electrode drive circuit 6 supplies a video pixel signal having a voltage amplitude corresponding to the shading of display of each pixel to the signal electrode 10 connected to each pixel. Control circuit 7
Controls the operation of the scan electrode drive circuit 5 and the signal electrode drive circuit 6.

FIG. 5 is a circuit diagram of a conventional signal electrode drive circuit 6.
And the driving waveform is shown in FIG. The signal electrode drive circuit 6 shown in FIG. 5 is for full gradation display. Therefore, as shown in FIG. 6, the video signal V input to the signal electrode drive circuit 6 has a continuous value.

The sample-and-hold circuit section 1 is composed of a plurality of sample-and-hold circuits provided one by one for each signal electrode 10. i-th (i is a natural number less than or equal to n. The following subscript i is assumed to be equal to i)
Is comprised of a sampling switch Ai, a sampling capacitor Ci, a hold switch Bi, and a hold capacitor Di.

In a sampling switch Ai or a hold switch Bi formed by a MOS transistor, a pixel sampling pulse Si and a line switch signal T are respectively input to the gate g, and the pixel sampling pulse Si and the line switch signal T are set to "High".
These switches Ai and Bi are turned on when the level becomes "h", and turned off when the pixel sampling pulse Si and the line switch signal T become "Low".

The shift register circuit 2 receives a shift pulse CK shown in FIG.
By sequentially shifting the horizontal synchronizing pulse S supplied from the terminal t1 as shown in FIG.
The pixel sampling pulses S 1, S 2, S 3,..., Sn shown in FIGS. A1, A2, A3, ..., An
To the gate g.

The video signal V input via the terminal t5
Are the video pixel signals V1 and V2 as shown in FIG.
, V3,..., Vn (n is the number of pixels on one scanning line. The following subscript n is assumed to be equal to n). It is supplied to the source s of the switch Ai.

The drain d of the sampling switch Ai is connected to the source s of the hold switch Bi. One electrode of the sampling capacitor Ci is connected to the connection between the sampling switch Ai and the hold switch Bi, and the other electrode is grounded. The drain d of the hold switch Bi is connected to the input electrode of the output buffer circuit Ei. One electrode of the hold capacitor Di is connected to a connection between the hold switch Bi and the output buffer circuit Ei, and the other electrode is grounded.

When the i-th pixel sampling pulse Si goes to the "High" level in order, only the sampling switch Ai is turned on for a certain period, so that the video signal V in that period is used as the video pixel signal V'i as the sampling capacitor Ci. Is stored in In this manner, the video signal V for one scanning line is time-divided, and the video pixel signal V′1
, V'2, V'3,..., V'n are stored in the sampling capacitors C1, C2, C3,.

Thereafter, the terminals L1, L2, L3,..., Ln
, The line switch signal T, which is normally at the "Low" level, changes to the "High" level for a certain period, and all the hold switches B1, B2, B3,..., Bn are simultaneously turned on for a certain period, and the sampling capacitor C1 ,
The video pixel signals V'1, V'2, V'3, ..., V'n stored in C2, C3, ..., Cn are simultaneously transferred to and held by the hold capacitors D1, D2, D3, ..., Dn. You.

Each of the output buffer circuits E1, E2, E3,
, En are the video pixel signals V'1, V'2, V'3, ..., V'n held in the hold capacitors D1, D2, D3, ..., Dn of the sample and hold circuit unit 1, respectively.
Are efficiently transmitted to the signal electrode 10 as video pixel signals V1, V2, V3,..., Vn.

With the above circuit, the video pixel signals V1, V2,... Having the amplitude corresponding to the shading of the display of each pixel.
V3,..., Vn are applied to the signal electrode 10.

In the above-described display device for full gradation display, when one character is displayed in two colors by a video signal V output from a computer or the like, the character is represented by several dots. Specifically, the dots constituting the character portion are represented as “white” by the pixels having high luminance, and the dots constituting the background portion are represented as “black” by the pixels having the low luminance. The voltage VH at the "High" level is applied to the pixel electrode 12 of the pixel forming the character, and the video signal has a waveform like the video signal Va shown in FIG.

When the video signal Va is "High" for a certain period of time.
Signal level VH at time Ti rising to
Is input only to the specified i-th pixel, the i-th signal electrode 10 for supplying the video signal Va to the pixel electrode 12 of that pixel is accurately specified.
The rising time Ti of the pixel sampling pulse Si supplied by the shift register circuit 2 so that the sampling switch Ai of the sample-and-hold circuit unit 1 connected to the signal electrode 10 is turned on for a fixed time from the time Ti.
'Coincides with a time Ti at which the video signal Va rises to the “High” level for a certain period.

[0020]

However, no matter how the electronic circuit is assembled, there is always a delay in signal transmission, and therefore, the rising time T of the pixel sampling pulse Si is increased.
It is impossible to completely match i ′ with the time Ti when the video signal Va rises to the “High” level for a certain period. For example, if the video signal Va is delayed like the video signal Vb shown in FIG. 6 (i), the i-th and (i + 1)
At the rising times Ti ', T (i + 1)' of the pixel sampling pulses Si, S (i + 1), the video signal Vb
Is a "High" level signal voltage VH, so that a "High" level voltage VH is applied to the pixel electrodes 12 of both pixels.

In general, the video signal V always passes through an amplifier circuit, a buffer circuit and the like before being input to the signal electrode driving circuit 6, but when passing through these circuits, the video signal V after passing therethrough depends on the frequency band. The signal is distorted. For example, the video signal Va applied to the aforementioned i-th pixel electrode 12
May be distorted like the video signal Vc shown in FIG. Therefore, the rising time Ti 'of the pixel sampling pulse Si and the video signal Va are maintained for a certain period of time.
Even if it is possible to completely match the time Ti at which the signal rises to the "High" level, the i-th time and (i +
1) At the rising time Ti ', T (i + 1)' of the pixel sampling pulse Si, S (i + 1), the video signal V
Since “b” is the “High” level signal voltage VH, the “High” level voltage VH is applied to the pixel electrodes 12 of both these pixels. Therefore, when an OA image is displayed, the phenomena that the positions of the pixels constituting the characters or the like inevitably shift or the characters or the like displayed on a plurality of pixels blur.

An object of the present invention is to solve such a problem and to provide a display device having a signal electrode drive circuit capable of accurately supplying a video signal to each pixel.

[0023]

In order to achieve the above object, a driving circuit of a display device according to the present invention inputs a signal voltage corresponding to the density of display of a display pixel to each signal electrode of a matrix type display device. A plurality of sample-and-hold circuits corresponding to the number of signal electrodes having switch means and capacitors for extracting a voltage corresponding to a pixel to be displayed among input signals in which display signals of respective pixels are arranged in chronological order. ,
A first switch signal supply means for generating a first switch signal to be applied to the switch means for sequentially performing a sampling operation of the sample and hold circuit; and a first switch signal supply means for outputting a voltage held by the sample and hold circuit to a signal electrode. And an output circuit, wherein the input video signal is turned on only during a period in which a video pixel signal of a display pixel to be displayed in the input video signal is included, and is turned off in other periods by a second switch signal. A mode for selecting whether to output or inhibit the first switch signal, and a mode for turning on all switch means of the sample and hold circuit to reset the sample and hold circuit regardless of the output of the gate means. When,
And a means for passing the output of the gate means to the switch means to operate the sample and hold circuit.

[0024]

With such a configuration, the same "Low" level signal voltage can be sampled in all the capacitors of the sample and hold circuit by first turning on all the switch means of the sample and hold circuit within one horizontal scanning period. .

Further, the first switch signal is output only to the pixel to be displayed by the gate means, and the output is prohibited to the other pixels. Therefore, the capacitor of the sample and hold circuit corresponding to the pixel to be displayed is set to "High". The signal voltage of the level can be sampled, and the signal voltage of the “Low” level can be kept held in the capacitor of the sample and hold circuit corresponding to another pixel. Therefore, when an OA image is displayed, a favorable display can be obtained in which no displacement or bleeding of the displayed pixels occurs.

[0026]

FIG. 1 is a circuit diagram of a signal electrode driving circuit 6 embodying the present invention, and FIG. 2 is a driving waveform thereof. In FIG. 1, the same portions as those shown and described in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 2A shows the shift pulse C
The waveform of K is shown.

The logic gate circuit 3 includes an OR logic circuit G 1,
G2, G3,..., Gn and AND logic circuits F1, F2,.
F3,..., Fn.

AND logic circuits F1, F2, F3,.
n is the switch signal input from the two input terminals,
"Low" if at least one is at "Low" level
Level, and if both switch signals input from the two input terminals are at “High” level, “High”
Switch signals S'1, S'2, S'3,
..., S'n are output. AND logic circuits F1, F2, F
One input terminal of each of the terminals..., Fn is connected to a terminal t3. The switch signal COFF is input to the terminal t3.

The OR circuits G1, G2, G3,...
When at least one of the switch signals input from the two input terminals is at the “High” level, the level becomes “High” level, and when both of the switch signals input from the two input terminals are at the “Low” level, “Low”. Switch signals S "1, S" 2, S "3,..., S"
Print n. One input terminal of each of the OR circuits G1, G2, G3,..., Gn is connected to a terminal t4. The switch signal CON is input to the terminal t4.

The description will be made on the assumption that display is performed only on the i-th pixel within one horizontal scanning period. Based on a memory (not shown) such as a microcomputer, an external control device (not shown) performs pixel sampling shown in FIG. 2 (H) output from the shift register 2 to display only the i-th pixel. The video signal COFF as shown in FIG. 2 (E) so that the timing and the waveform coincide with the pulse Si.
Is supplied to the input terminal of each AND circuit Fi via the terminal t3.

First, as a first operation procedure, FIG.
As shown in the figure, the switch signal CON is set to "High"
Level, each pixel sampling pulse Si (i
Is a natural number of n or less. The following subscript i is assumed to be equal to this i. ), Regardless of the switch signal COFF and the switch signal S'i, all the switch signals S "i are at" High "level for a certain period by the OR circuit Gi, and the source s and the drain d of all the sampling switches Ai are conductive. At this time, if the video signal V is set to the "Low" level as shown in Fig. 2C, the "Low" level video pixel signal V'i can be held in all the sampling capacitors Ci. .

Next, as a second operation procedure, FIG.
As shown in FIG. 2, the switch signal CON is set to the "Low" level. When the horizontal synchronizing pulse S rises at the time T0 as shown in FIG. The video signal V is set to the “High” level until one horizontal scanning period ends.

The pixel sampling pulses S1, S2,.
When Si-1, Si + 1,..., Sn are inputted, as described above, the switch signal COF having the waveform shown in FIG.
F is at the “Low” level. Accordingly, the AND circuit Fi always outputs the "Low" level switch signal S'i regardless of the pixel sampling pulse Si. The OR circuit Gi outputs the switch signal CON as “Lo”.
Since the signal remains at the w "level, the switch signal S" i at the "Low" level is output. Therefore, at this time, the "Low" level video pixel signal V'i is still held in all the sampling capacitors Ci.

Conversely, during the period Ti to T (i + 1) during which the pixel sampling pulse Si is input, the switch signal COFF is at the "High" level as described above. During this period Ti to T (i + 1), as shown in FIGS. 2F, 2G and 2H, the pixel sampling pulses S1, S2, S3,
.., Sn, only the pixel sampling pulse Si is “
2 (K), only the switch signal S′i output from the AND circuit Fi shown in FIG. 2 (K) is at the “High” level, while the other AND circuits are at the “High” level. F1,..., F (i-1), F (i + 1)
, ..., Fn output switch signals S'1, ..., S '
(i-1), S '(i + 1), ..., S'n are all shown in FIG.
It becomes the “Low” level as shown in (I) and (J).

Since the switch signal CON remains at the "Low" level, the switch signal S 'at the "High" level is provided.
i, only the switch signal S "i output from the OR circuit Gi that has received the input becomes" High "level, while the other OR signals Gi
, G (i-1), G (i + 1),..., Gn output switch signals S "1,..., S" (i-1), S "(i + 1),
.., S ”n are all at the“ Low ”level.

Therefore, while only the sampling capacitor Ci corresponding to the pixel to be displayed holds the "High" level video pixel signal Vi, the other sampling capacitors C1,..., C (i-1), C (i + 1),..., Cn include “Low” level video pixel signals V ′ 1,.
Since (i−1), V ′ (i + 1),..., V′n are kept, it is possible to obtain a specific image such as an accurate and clear character without displacement or blur.

The switch signal COFF is set to "Hi" in addition to the case where the OA image is displayed by reproducing the binary video signal V shown in FIG.
GH "level and the switch signal CON is fixed to" Low "level, and the video signal V such as audio video having continuous values as shown in FIG. Can also be displayed.

Next, FIG. 3 shows a circuit diagram of the signal electrode drive circuit 6 in the case of performing full color display using three primary colors according to the present invention. In FIG. 3, the same parts as those shown and described in FIG. First,
When performing full color display only on the i-th pixel within one horizontal scanning period, the operation is performed as described above, but the following points are changed.

Since the three primary colors are separately supplied as equivalent to the video signal V in FIG. 1, the red video signal V
R, green video signal VG, and blue video signal VB are supplied via terminals t5R, t5G, and t5B, respectively.

The video signal VR, VG, VB is time-division-divided and corresponds to the switch signal COFF in FIG. 1 in order to reliably synchronize the operation of holding the video pixel signal V'i by the sampling capacitor Ci. As a thing,
The signals COFFR, COFFG, and COFFB are supplied via terminals t3R, t3G, and t3B.

The switch signals COFFR, COFFG, COFFB and the video signals VR, VG, VB are alternately AND circuits Fi, F (i + 1) 1, F (i + 2) and a sampling switch Ai, respectively.
, A (i + 1) and A '(i + 2) (i is a natural number equal to or less than n).

The shift register circuit 2 converts the pixel sampling pulse Sj into AND circuits F3j, F (3j-1) and F (3j-2).
It is simultaneously supplied to one of the input terminals.

[0043]

As described above, according to the present invention,
One display device can display both the OA image and the AV image, and the switching can be easily performed. In addition, in the case of displaying an OA image, a favorable display can be obtained without causing a displacement of a pixel to be displayed or a blur of an image, and the versatility of the display device can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signal electrode driving circuit of a liquid crystal display device embodying the present invention.

FIG. 2 is a diagram showing waveforms of respective signals in a signal electrode drive circuit of a liquid crystal display device embodying the present invention.

FIG. 3 is a circuit diagram of a signal electrode drive circuit of another liquid crystal display device embodying the present invention.

FIG. 4 is a block circuit diagram illustrating a configuration of a general liquid crystal display device.

FIG. 5 is a circuit diagram of a signal electrode drive circuit of a conventional liquid crystal display device.

FIG. 6 is a diagram showing waveforms of signals in a signal electrode drive circuit of a conventional liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Sample hold circuit part 2 Shift register circuit 3 Logic gate circuit 4 Active matrix type liquid crystal display device 5 Scan electrode drive circuit 6 Signal electrode drive circuit 7 Control circuit 8 Display panel 9 Thin film transistor 10 Signal electrode 11 Scan electrode 12 Pixel electrode t1-t5 , T3R, t3G, t3B, t5R, t5G, t5B terminals L1 to Ln terminals A1 to An sampling switches B1 to Bn hold switches C1 to Cn sampling capacitors D1 to Dn hold capacitors E1 to En output buffer circuits F1 to Fn AND circuits G1 Gn OR circuit CK Shift pulse COFF, COFFR, COFFG, COFFB signal CON signal S Horizontal synchronization pulse S1 to Sn Pixel sampling pulse S'1 to S'n Switch signal S "1 to S" n Switch signal V Video signal (VR red , VG green, VB blue) V1-Vn video Motoshingo V'1 ～V'n video pixel signal T line switch signal

Claims (1)

(57) [Claims] In order to input a signal voltage corresponding to the shading of display of a display pixel to each signal electrode of a matrix type display device, a display signal of an input signal in which display signals of each pixel are arranged in chronological order. A plurality of sample-and-hold circuits corresponding to the number of signal electrodes having a switch means for extracting a voltage corresponding to a pixel to be processed and a capacitor, and a first means to be added to the switch means for sequentially performing a sampling operation of the sample-and-hold circuit. In a drive circuit of a display device having first switch signal supply means for generating a switch signal and an output circuit for outputting a voltage held by a sample and hold circuit to a signal electrode, a display to be displayed in the input video signal A second switch for instructing to turn on only during a period including the video pixel signal of the pixel and to turn off during the other periods. Gate means for selecting whether to output or inhibit the first switch signal by a switch signal; and all switch means of the sample and hold circuit for resetting the sample and hold circuit regardless of the output of the gate means. A mode for turning on a switch, and a mode for passing the output of the gate unit to the switch unit in order to operate the sample-and-hold circuit.