JP3165751B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As input / output circuits used in conventional semiconductor integrated circuit devices, there are a CMOS type and a single channel open drain type. These types of input / output circuits will be described with reference to FIGS. 7 to 9. In the following description, it is assumed that there are two types of power supplies to be supplied to the semiconductor integrated circuit device. A higher power supply (drive power supply) is assumed to be V _DD .

FIG. 7 shows a configuration of a CMOS type input / output circuit. This input / output circuit includes a drive power supply _VDD and a ground power supply GN
D, a P-type MOS transistor 71 and an N-type MOS transistor 72 are connected in series, and a connection point of these transistors and a terminal OUT connected via a resistor R are connected to an input / output terminal for connection with the outside of the integrated circuit device. I do. 7, signals A1, A2 are each gate input of transistors 71 and 72, the signal I ₁ is a signal input to the integrated circuit device from the output terminal OUT. In the input / output circuit shown in FIG.
The level of A2 is V _DD and GND, that is, both the transistors 71 and 72 are turned off, and an arbitrary voltage is applied to the input / output terminal OUT from outside the semiconductor integrated circuit device. At this time, there is no problem as long as the voltage applied to the input / output terminal OUT is a value between the drive power supply voltage _VDD and the ground power supply voltage GND.
However, a voltage higher than the drive power supply voltage V _DD level or a voltage lower than the ground power supply voltage GND level is applied to the input / output terminal O.
If applied to the UT, PN junction D _i or D _j is the forward bias is parasitically formed as shown in FIG. For example, when a voltage equal to or higher than the V _DD level is applied to the input / output terminal OUT, as shown in FIG. 8, the P-type diffusion layer 101A connected to the terminal OUT and the N-type substrate connected to the drive power supply V _DD 111 PN junction _{D i} is formed, when applying a GND level or less of the voltage, the N-type diffusion 102A to PN junction _{D j} that is connected to the P-well layer 110 and the terminal OUT which is connected to the ground power supply GND And a forward bias is applied to each. If this bias exceeds the forward threshold value of the PN junction, a direct current flows, which may lead to element destruction.

When the levels of input signals A1 and A2 are G
When it is at the ND level, the transistor 71 is turned on and the transistor 72 is turned off, and the _VDD level is output to the terminal OUT. In this case, the GND level can be applied from the terminal OUT using the resistor R as a pull-up circuit. However, when a voltage lower than the GND level is applied to the terminal OUT, the transistor 71 connected to the power supply _VDD is applied.
If the signal I1 becomes a voltage lower than the GND level due to the voltage division ratio between the ON resistance and the input protection resistance R, the above-described problem occurs.

However, in a recent semiconductor integrated circuit device, than the drive power supply voltage V _DD for use in lower potential than the high potential or a ground power supply potential GND level, peripheral devices beyond the range of the normal power supply voltage (for example, a fluorescent It is often required to drive peripheral devices that operate with a power supply different from the power supply range of the semiconductor integrated circuit device, such as by directly driving a tube or a printer, to reduce the number of interface components outside the semiconductor integrated circuit device. However, when a voltage outside the normal power supply range is applied to the terminal OUT in FIG. 7 from the outside, the above-mentioned parasitic diode is formed, so that the CMOS type input / output circuit cannot be used.

Next, a description will be given of a single-channel open drain type input / output circuit in which a P-type or N-type MOS drain terminal is used as an external input / output terminal in order to externally input a voltage exceeding the range of the normal power supply voltage. . FIG. 9 shows an example of this type of circuit. The source terminal of the P-type MOS 91 is set to _VDD , and the drain terminal is connected to the external input / output terminal OUT. In the circuit shown in FIG.
Be applied lower than the GND level voltage to the UT, as shown in FIG. 7, PN junction D _j is not formed, the input-output terminal O
The voltage that can be applied to the UT only needs to be V _DD or less.

However, when viewed as an output circuit, a GND level is not output. That is, V _DD level and GND
The function as a CMOS output terminal for outputting the level is not satisfied.

[0008]

In recent years, the scale of the system and the number of functions of the integrated circuit device have been increased, and therefore, a reliability evaluation test circuit for shipping the integrated circuit device has been replaced with an integrated circuit device. However, the test circuit is complicated and the number of input / output terminals for performing the test is increasing.

Since an increase in the number of external connection terminals leads to an increase in the chip area, some of the original function terminals are used in a time-division manner, and during testing, they are used as input / output terminals of a test circuit. The number has been reduced.

However, when the one-channel open drain terminal described above is used as an input / output terminal of a test circuit, it can be used as an input terminal, but it is used for a test for outputting V _DD level and GND level for determination. It cannot be used as an output terminal. Particularly, in an integrated circuit device having a large number of single-channel open drain terminals, for example, a CPU or the like having a built-in fluorescent display tube driving circuit, the single-channel open drain terminal occupies 80% or more of all terminals of the integrated circuit device. Has to be added, leading to an increase in chip area and the like.

When it is desired to selectively use the one-channel open drain terminal and the CMOS output terminal according to the peripheral device, in the prior art, the output is formed as CMOS.
This is realized by a method such as separating the drain wiring of a channel element not used when one channel open drain is selected on a mask. However, in this case, there is a problem that a dedicated mask is required for separation, and two types of chips are produced, so that even if one of the stocks runs out, it cannot be covered by the other. That is, there is a problem that the user needs to use the chip properly depending on the peripheral device.

The present invention has been made in view of the above circumstances, and has a semiconductor integrated circuit having an input / output circuit capable of applying a voltage outside a normal power supply range to the terminals without increasing the number of terminals. It is intended to provide a device.

[0013]

A semiconductor integrated circuit device according to the present invention includes a clock generation circuit for generating a clock signal based on a first control signal, a first power supply, and a first power supply.
Driven by a second power supply that is lower than the potential of the power supply of the first power supply, and based on the first control signal and the clock signal, a signal of one of a potential level higher than the first power supply and a potential lower than the second power supply And a first and second MOS transistors of the first conductivity type and a third of the second conductivity type, which are connected in series between the first power supply and the second power supply. MOS transistor, and the first
The data signal is input to the gate of the MOS transistor of the first MOS transistor, and the gate of the first MOS transistor is connected to the gate of the first MOS transistor.
The second control signal is input to the gate of the third MOS transistor, and the substrate potential of the second MOS transistor is the input / output which is the inversion level of the second control signal. Circuit and a first input / output circuit of the input / output circuit.
And an input / output terminal connected to a connection point between the second MOS transistor and the second MOS transistor.

[0014]

According to the semiconductor integrated circuit device of the present invention, the first, second, and third MOS transistors are connected in series between the first power supply and the second power supply. The output signal of the first circuit is applied to the gate of the second MOS transistor, the second control signal is applied to the gate of the third MOS transistor, and the substrate potential of the second MOS transistor is set to the second control signal. Is the reversal level. Thus, in the input / output circuit according to the present invention, the generation of a parasitic forward diode can be prevented by inverting the gate input of the third MOS transistor to set the substrate potential of the second MOS transistor.
Type and single channel open drain type can be shared. Therefore, a voltage outside the normal power supply range can be applied without increasing the number of terminals.

[0015]

FIG. 1 shows the configuration of a first embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device according to this embodiment includes a clock generation circuit 1, a negative power supply generation circuit 2,
The input / output circuits 3 ₁ ,..., 3 _n and the input / output terminals OUT ₁ ,.
OUT _n . The clock generation circuit 1 generates an inverted signal / H of the control signal H based on the control signal H.
Generates a clock signal φ. This clock generating circuit 1 has, for example, a ring type as shown in FIG.
There is a CR type as shown in (b). The ring-type clock generation circuit includes a cascade-connected NOR gate 1a, inverters 1b, 1c, 1d, 1e, and an inverter 1f. The control signal H is input to one input terminal of the NOR gate 1a, and the output φ of the final-stage inverter 1e is input to the other input terminal. The control signal H is input to the input terminal of the inverter 1f. And inverter 1
The clock signal φ is output from the output terminal of e, and the inverted signal / H of the control signal H is output from the output terminal of the inverter 1f.

On the other hand, the CR type clock generation circuit comprises a cascade-connected NOR gate 1a and inverters 1b, 1b.
c, 1d, 1e, a capacitor C1, a resistor R1, and an inverter 1f. Capacitor C1 is NOR
The resistor R1 is connected in parallel with a series circuit including the gate 1a and the inverter 1b, and the resistor R1 is connected in parallel with a series circuit including the NOR gate 1a and the inverters 1b and 1c. The control signal H is input to each input terminal of the NOR gate 1a and the inverter 1f, the clock signal φ is generated from the output terminal of the inverter 1e, and the inverted signal H of the control signal H is output from the output terminal of the inverter 1f. Is output. Therefore, when the control signal H is at the V _DD level (logic "1" level), the output signal φ of the clock generation circuit 1 is at the GND level (logic "0" level). When the control signal H is at the GND level, the output signal .phi. φ is a clock signal.

Next, as shown in FIG. 4, the negative power supply generating circuit 2 outputs a signal S based on a clock signal φ and a signal H. For example, a CMOS inverter comprising a P-channel transistor and an N-channel transistor , P-channel transistors 2c, 2d, 2f, an inverter 2e, and capacitors C21, C22. The clock signal is input to the input terminal F0 of the CMOS inverter, and the output terminal F1 is connected to one end of the capacitor C21. The drive power supply voltage V _DD is applied to the source of the transistor 2a of this CMOS inverter, and the ground power supply voltage GND is applied to the source of the transistor 2b. The transistors 2c and 2d are cascaded,
The connection point F2 is connected to the other end of the capacitor C21. The ground power supply voltage GND is connected to the drain of the transistor 2c.
Is applied. The gate of the transistor 2c is connected to the drain of the transistor 2c.
The gate of d is connected to the drain of the transistor 2d. The control signal H is input to the input terminal of the inverter 2e, and the output terminal is connected to the back gate of the transistor 2d. The drive power supply voltage V _DD is applied to the source of the transistor 2f, the control signal H is applied to the gate,
The drain F3 is connected to one end of the capacitor C22. The source of the transistor 2d is connected to the drain F3 of the transistor 2f, and an output S of the negative power supply generation circuit 2 is output from the connection point F3. Note that the capacitor C22
Is applied with the ground power supply voltage GND.

The operation of the negative power supply generating circuit 2 will be described with reference to the timing chart of FIG.

First, when the control signal H is at the V _DD level, the output φ of the clock generation circuit 1 is at the GND level. Therefore, the output terminal F1 of the CMOS inverter is at the V _DD level, and the inverted signal of H is at the GND level. Therefore, the transistor 2f turns ON, and the output signal S becomes _VDD . At this time, the substrate potential of the transistor 2d is
It becomes V _DD level of output, does not forward the diode is formed.

Next, when the control signal H is at the GND level, the output φ of the clock generation circuit 1 becomes a clock signal. The case where the clock signal becomes this clock signal will be described for each region of the timing chart of FIG.

In the area (I), the signal φ becomes GND,
The output terminal F1 of the CMOS inverter is V _DD , and the initial voltage at the node F2 is a voltage higher than GND by the threshold voltage Vthp (> 0) of the transistor 2c. Note that the initial value of S is set to GND in the region I.

In the next area (II), the signal φ is V _DD , CM
The output terminal F1 of the OS inverter becomes GND, and the connection point F
2 is -V _DD + 2V thp because the potential difference is to be held in the region I according to the charge conservation law of the capacitor C21.
The output signal S is equal to the threshold voltage of the transistor 2d.
The voltage becomes −V _DD + 2V thp higher by thp.

The capacitor C22 is connected to this voltage (-V _DD + 2V
thp). Although the electric charge stored in the capacitor C22 gradually disappears due to the current consumed in the integrated circuit device, the region I and the region II are repeated by the clock signal φ, and the charge is performed at the beginning of the region II. There is no loss of charge. Where Vthp = 1V,
If V _DD = 5V, the output signal S has a potential of -3V. That is, a voltage lower than GND (= 0 V) is generated.

Next, the input / output circuit 3 _i (i = 1,..., N) will be described. These input / output circuits 3 _i (i = 1,
.., N) have the same configuration, and include, for example, as shown in FIG. 6, an AND gate 3a, P-channel transistors 3b and 3c, an N-channel transistor 3d, and an inverter 3e. Transistors 3b, 3
c and 3e are connected in series. The drive power supply voltage V _DD is applied to the source of the transistor 3b, and the transistor 3d
Are applied with the ground power supply voltage GND. AN
The data signal D is input to one input terminal of the D gate 3a, and the control signal T is input to the other input terminal. The output terminal of the AND gate 3a is connected to the gate of the transistor 3d and the input terminal of the inverter 3e, and the output terminal of the inverter 3e is connected to the back gate of the transistor 3c.
The data signal D is input to the gate of the transistor 3b, and the output S of the negative power supply generation circuit 2 is input to the gate of the transistor 3c. The output terminal OUT _i to the connection point 61 of the transistor 3b and 3c are connected.

Next, the input / output circuit 3 _i (i = 1,...,
The operation n) will be described. The input-output circuit _{3 i} becomes an output circuit of CMOS type by turning ON the transistors 3c, the input circuit of P-channel open-drain by turning OFF the transistor 3c.

First, the operation as a CMOS type output circuit will be described.

In the case of the output circuit, first, the control signal H is set to the GND level, and the output signal φ of the clock generation circuit 1 is output.
And the output signal S of the negative power supply generation circuit 2
Is supplied with a voltage lower than the GND level. Here, the control signal T is set to the V _DD level.

When the data signal D is set at V _DD , the output of the AND gate 3a becomes V _DD , whereby the transistor 3d
Is turned on, and the connection point between the transistors 3c and 3d is at the GND level. The gate input of the transistor 3c is at a voltage lower than the GND level, the substrate potential is GND, and therefore the transistor 3c is turned ON, and the GND level is output to the output terminal OUT _i (i = 1,..., N).

When the data signal D is at the GND level, the transistor 3b is turned on and the transistor 3d is turned off. Therefore, the transistor 3c turns on. However, the substrate potential of PM12 is I
It is set to V _DD by the output of NV11.

That is, since a voltage lower than the GND level is applied to the gate input of the transistor 3c and the substrate bias is controlled by the inverter 3e, the transistor 3c is turned on and a CMOS inverter circuit composed of the transistors 3b and 3d is used. The same operation is possible.

Next, the operation as a P-channel open drain type input / output circuit will be described. In the case of the P-channel open drain, the control signal H is set to the V _DD level,
The output signal φ of the clock generation circuit 1 is at the GND level, the output S of the negative power supply generation circuit 2 is that the transistor 2f is turned on,
By controlling the substrate bias of the transistor 2d, V.sub.
_DD level is output. For this reason, the transistor 3c is turned off, and becomes a P-channel open drain type regardless of whether the transistor 3d is turned on or off. If the control signal T is set to the GND level, the substrate potential of the transistor 3c becomes the _VDD level, and no forward diode is generated. That is, that the forward diode does not occur even by applying a voltage lower than the GND level to the output terminal OUT _i. Here, the same result can be obtained for the control signal T as an inverted signal of the control signal H.

The shared circuit of the CMOS type and the P-channel open drain type has been described above, but the P-type transistor and the N-type transistor are changed.
By making the negative power supply circuit 2 a power supply circuit higher than V _DD , it is easy to make it a shared circuit of the CMOS type and the N-channel open drain type.

As described above, according to the first embodiment, there is provided a semiconductor integrated circuit device which is a single-channel open drain input / output circuit and has an input / output circuit capable of outputting a CMOS type. be able to.

Therefore, a voltage outside the normal power supply range can be applied to the input / output circuit, and in an integrated circuit device requiring a large number of single-channel open drain terminals, the V _DD level and the GND level are used for testing. It is no longer necessary to increase the number of dedicated CMOS output terminals for output and determination. Therefore, there is an advantage that the number of terminals does not increase and the chip area can be the same as before.

Further, since a single chip can be used as both a CMOS circuit and an open drain circuit, there is an advantage for a user that a single chip can be purchased irrespective of a method of connecting peripheral devices. You only need to make one chip.

Next, the configuration of a second embodiment of the semiconductor integrated circuit device according to the present invention is shown in FIG. The semiconductor integrated circuit device of this embodiment in the first embodiment shown in FIG. 1, the input-output circuit 3 _1, ..., input and output circuits 4 ₁ instead of 3 _n, ..., 4
_n , each input / output circuit 4 _i (i = 1,
, N) have the same configuration, and include P-channel transistors 4a, 4b and N-channel transistor 4c.
And an inverter 4d. The transistors 4a, 4b, 4c are connected in series,
_Are applied with the drive power supply voltage V _DD , and the source of the transistor 4c is applied with the ground power supply voltage GND. The data signal D _i is connected to the gate of the transistor 4a.
Is input to the gate of the transistor 4b, and the control signal _Ei is input to the gate of the transistor 4c. The control signal _Ei is input to the input terminal of the inverter 4d, and the output terminal is connected to the back gate of the transistor 4b.

It goes without saying that the semiconductor integrated circuit device of the second embodiment also has the same effect as the first embodiment.

[0038]

According to the present invention, it is possible to obtain a semiconductor integrated circuit device having an input / output circuit capable of applying a voltage outside the normal power supply range to the terminals without increasing the number of terminals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific example of a clock generation circuit according to the present invention.

FIG. 4 is a circuit diagram showing a specific example of a negative power supply generating circuit according to the present invention.

FIG. 5 is a timing chart showing a specific example of the negative power supply generation circuit shown in FIG. 4;

FIG. 6 is a timing chart showing a specific example of an input / output circuit according to the present invention.

FIG. 7 is a circuit diagram of a conventional CMOS type input / output circuit.

FIG. 8 is a manufacturing cross-sectional view of a conventional input / output circuit.

FIG. 9 is a circuit diagram of a conventional single channel open drain type input / output circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroyuki Suwabe 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture In-house Toshiba Microelectronics Co., Ltd. No. 1 Toshiba Semiconductor System Engineering Center Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19/0175

Claims (2)

(57) [Claims] A first power supply; a first power supply; and a second power supply lower than a potential of the first power supply, wherein the first power supply is driven by a first power supply. A first circuit that outputs a signal at one of a higher potential than the first power supply and a lower potential than the second power supply based on the control signal and the clock signal; and the first power supply and the second circuit. A first conductive type first and second MOS transistor and a second conductive type third MOS transistor connected in series between the power supply and a power supply, wherein a data signal is connected to a gate of the first MOS transistor; , The output signal of the first circuit is input to the gate of the second MOS transistor, the second control signal is input to the gate of the third MOS transistor, and the second MOS transistor And output circuit is a substrate potential is inverted level of the second control signal, first MOS transistor and the second M of the input-output circuit
A semiconductor integrated circuit device comprising: an input / output terminal connected to a connection point of an OS transistor. 2. The CMOS circuit according to claim 1, wherein the first circuit is provided between the first power supply and the second power supply, and an input terminal receives an output of the clock generation circuit. A first capacitor connected to the output terminal of the CMOS inverter circuit, a first conductive type fourth, fifth and sixth type connected in series between the first power supply and the second power supply; A MOS transistor, and a second capacitor having one end connected to a connection point between the fourth MOS transistor and the fifth MOS transistor and the other end connected to the second power supply. The inverted signal of the first control signal is applied to the gate of the fifth MOS transistor, and the fifth MOS transistor and the sixth MOS transistor are connected to the gate of the fifth MOS transistor.
Potential of the connection point of the MOS transistor
Is connected to a second power supply, the other end of the first capacitor is connected to a connection point between a fifth MOS transistor and a sixth MOS transistor, and the substrate potential of the fifth MOS transistor is This is the level of the first control signal.
2. The semiconductor integrated circuit device according to claim 1, wherein a potential at a connection point with the MOS transistor is used as an output of the first circuit.