JP3263977B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (DRAM) for storing a plurality of data in a temporary register and outputting the data at high speed in synchronization with a clock.
Also, the present invention relates to a semiconductor device capable of changing the order of output data to a desired order by an external signal and outputting the same in a synchronous DRAM).

[0002]

2. Description of the Related Art In recent years, commercialization of DRAMs operating at high speed has been promoted. Among them, synchronous type (synchronous)
The DRAM stores a plurality of output data in a temporary register and continuously outputs the data at a high speed in synchronization with an externally applied clock.

Hereinafter, a semiconductor device which is a conventional data output device will be described. FIG. 3 shows a configuration diagram of a conventional semiconductor device capable of continuously outputting 4-bit data. In FIG. 3, reference numeral 21 denotes a 4-bit shift register. 4-bit data D0, D1, D2, D read from one column address in a DRAM
3 is temporarily stored in the shift register 21. First, D0 is output in synchronization with the external clock, and data D1, D2,
D3 moves to the location where D0, D1, and D2 are stored, respectively. Thereafter, similarly, 4-bit data is output in the order of D1, D2, and D3.

[0004]

However, in the above-mentioned conventional configuration, output data can be output only in a fixed order of D0, D1, D2, and D3. Therefore, for example, the burst transfer mode such as the burst transfer mode of the microprocessor i486. There is a problem that it is not possible to cope with a special data reading order.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device capable of outputting a plurality of output data stored in a data register in a desired order.

[0006]

In order to achieve this object, a semiconductor device according to the present invention stores a plurality of sets of output order,
Output data mode and output start data
Desired output from the stored output order by the data number
Read the data that specifies the order and determine the data output order.
Specifying multiple signals and each output of the counter
An address conversion circuit for selecting a specific signal from a plurality of signals for each clock ; a decoder circuit for receiving a signal from the address conversion circuit to perform a degode operation; a data register for temporarily storing a plurality of data; Input to the address conversion circuit by a signal from the circuit
The data registers in the order of data output specified by the signal;
And a data output circuit for outputting the data stored in the memory .

[0007]

[Action] This arrangement makes it possible to output a plurality of data stored in the data register by the output from the de co over da circuits in order of Tokoro <br/> Nozomu.

[0008]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a semiconductor device capable of outputting 4-bit output data in a desired order according to the first embodiment of the present invention.

In FIG. 1, 1 is a counter for sequentially turning on the switches of the address conversion circuit in synchronization with a clock, and 2 is a signal for designating the eight switches controlled by the counter 1 and the order of data output. An address conversion circuit composed of a read only memory (ROM) for outputting a signal corresponding to outputting data in a desired order by inputting a certain output data mode signal and an output head data number, and 3 is an address conversion circuit. A decoding circuit which receives output of the conversion circuit 2 and designates output data among the 4-bit data stored in the data register; 4 a data register for temporarily storing 4-bit output data which can be continuously output; 5 is for receiving the signal of the decoder circuit 3 and outputting the data stored in the data register 4 in a desired order. It is a switch.

The operation of the semiconductor device configured as described above will be described below. First, when the order of the output data is D0, D1, D2, D3, that is, when the output data mode is the serial mode and the output head data number is 0, the 8-bit output of the ROM in the address conversion circuit 2 is sequentially set to 00.
110101 (0 is low level, 1 is high level). If the output of the counter is set to 1 in order in synchronization with the clock, the 8-bit output of the ROM becomes 0th and 4th, 1st and 5th, 2nd and 6th by opening and closing a switch connected to the counter. Third
It becomes effective in the order of the 7th and 7th.

First, at the time of the first clock, both outputs of the address conversion circuit become 0, which is decoded through the decoder circuit 3, and the switch 5 outputs the data D0 stored in the data register 4.

Next, at the time of the second clock, the output of the address conversion circuit becomes 0 and 1, and the data D1 stored in the data register is output by the switch 5 via the decoder circuit as in the case of the first clock. You. Similarly, in the third clock and the fourth clock, D2, D
3 is output, so that D0 and D
Data is output in the order of 1, D2, and D3. When the output head data number is 2 in the serial mode, the 8-bit output of the ROM is sequentially set to 11000101.
, D2, D3, D
Data is output in the order of 0 and D1.

Next, the burst transfer mode of the microprocessor i486, ie, the order of D1, D0, D3, D2,
In the case of 2, D3, D0, and D1, the output data mode is designated as the i486 burst transfer mode, and the output first data number is designated as 1. The 8-bit output of the ROM in the address conversion circuit is designated in order. When the first clock is set, the output of the address conversion circuit is 0 and 1, and the switch connected to the data register D1 via the decoder circuit is turned on, and the data D1 is output. Is done. Similarly, D0 is output in the second clock, and D3 and D2 are output in the third and fourth clocks, respectively. When the output head data number is designated as 2, the 8-bit output of the ROM is sequentially set to 110001.
When the data is set to be 01, the data is output in the order of D2, D3, D0, and D1 in the same manner as when the head data is D1.

As described above, the counter 1 which operates in synchronization with the clock, the address conversion circuit 2 which emits a signal corresponding to the order of desired data output, the decoder circuit 3 which decodes a signal from the address conversion circuit, By providing a data register 4 for temporarily storing a plurality of data and a switch 5 for outputting the data stored in the data register by a signal from a decoder circuit, a plurality of data can be continuously output in a desired order in synchronization with a clock. Can be output to

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 (a),
(B) shows the case where the 4-bit output data according to the second embodiment of the present invention is converted into the serial order and the microprocessor i.
486 is a configuration diagram of a semiconductor device that outputs data in the order of the burst transfer mode. FIG.

In FIGS. 2A and 2B, reference numeral 11 denotes a data register for temporarily storing 2-bit data,
12 and 13 are counters having two outputs of 0 and 1 (0 is low level, 1 is high level),
A switch 14 receives the outputs of the counters 12 and 13 and outputs the output data stored in the data register 11. The two data registers 11 store 0th and 2nd data D0 and D2, and 1st and 3rd data D1 and D3, respectively. The output of the counter 12 is inverted when the output of the counter 13 that outputs data different from the respective data is 1, and the output of the counter 13 is inverted in synchronization with the clock.

The operation of the semiconductor device configured as described above will be described below. First, in the case where the output data mode is the serial mode and the first output data number is the second D2, when the first clock for outputting data is input as shown in FIG. 1, D0 and D3 are set to 0. The output of the counter 13 on the D2 side is set to 1. Therefore, when the first clock is input, the switch 14 is turned on only in the output path of the second data D2,
D2 is output. Further, the output of the counter 12 connected to D1 and D3 after receiving the output 1 of the counter 13 becomes D1
The side is inverted to 0 and the D3 side is inverted to 1.

When the second clock is input, the output of the counter 13 is inverted.
The switch 14 is turned on only in the output path of No. 3 and D3
Is output. At this time, the output of the counter 12 connected to D0 and D2 after receiving the output 1 of the counter 13 becomes D
The 0 side is 1 and the D2 side is 0. Similarly, when the third clock is input, only the output path of the data D0 turns on the switch 14, and D0 is output. In this manner, data can be continuously output in the order of D2, D3, D0, and D1 in synchronization with the clock.

Next, FIG. 2B shows an example in which data is output in the burst transfer mode of the microprocessor i486 and the first output data number is the first D1. As shown in FIG. 2B, when the first clock is input, the output of the counter 12 is set so that D1 and D2 are 1 and D0 and D3 are 0, and the output of the counter 13 is D.
1 and D3 side are set to 1. Thus, when the first clock is input, only the output path of data D1 turns on switch 14, and data D1 is output. At this time, the output of the counter 12 on the D0 and D2 sides is inverted by the output 1 of the counter 13.

Next, when the second clock is input, the output of the counter 12 and the counter 13 turns on the switch 14 only in the output path of the data D0, and the data D0 is output. Similarly, the third is data D
The third and fourth outputs data D2. In this manner, data can be continuously output in synchronization with the clock in the order of D1, D0, D3, and D2. By setting the initial values of the counters 12 and 13 in this manner,
Data can be output in a desired data output order.

[0021]

As described above, the present invention provides a data register
To output a plurality of data stored in
It is possible to realize an excellent semiconductor device that can perform the following.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment.

FIG. 2 is a configuration diagram of a semiconductor device according to a second embodiment.

FIG. 3 is a configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 counter 2 address conversion circuit 3 decoder circuit 4 data register 5 switch 11 data register 12, 13 counter 14 switch

──────────────────────────────────────────────────続 き Continuation of the front page (72) Noriaki Amano, Inventor 1006 Odaka, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-184791 (JP, A) JP-A-2- 143983 (JP, A) JP-A-2-121186 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/34 G06F 5/00 H03K 19/00

Claims (2)

(57) [Claims] An output order of a plurality of sets is stored and input from outside.
Output data mode and output head data number
A desired output order from the stored output order.
To read data and specify the order of data output
Signals and the plurality of signals depending on each output of the counter.
An address conversion circuit for selecting a specific signal from each of the clocks for each clock ; a decoder circuit for receiving a signal from the address conversion circuit to perform a degode operation; a data register for temporarily storing a plurality of data; Said address translation by signal
Prior to the data output order specified by the signal input to the circuit
Output data stored in the data register
A semiconductor device including an output circuit . 2. A first data register for temporarily storing first data D0 and third data D2, and a second data D2
A second data register for temporarily storing first and fourth data D3, a first counter and two switches for selecting and outputting data of the first data register, and a second data register A second counter and two switches for selecting and outputting the data of the first and second data registers, a third counter for selecting and outputting the data of the first data register and the second data register in synchronization with a clock, and A semiconductor device, comprising: two switches, wherein the first and second counters operate by an output of a third counter.