JP3266245B2 - Drive circuit for image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of an image display device in which a liquid crystal is sandwiched between substrates and an active element provided for each pixel drives the liquid crystal.

[Prior Art] FIG. 15 shows a driving circuit of a conventional image display device having a shift register and a sample-and-hold circuit. (90)
Are connected in multiple stages, and the outputs D _S (1), D _S (2), D _S (3),.
The image signals D ^A , D ^B , and D ^C of the three data lines are sequentially sampled and held. When D _S (1) goes high (V _DD ) at the timing shown in the timing chart of FIG. 17, the data switch (91) is closed, and the image signal at that timing is sampled in the data capacity (92). D Open _S (1) is low (V _BB) (91), holds the image signal sampled in (92). The sampled and held image signal is buffer-output from the buffer amplifier (93). Transfer switch (94) that closes when the enable signal W is high
Through each column electrode of the image display device, D (1), D
(2), D (3),... Are simultaneously supplied. No.
FIG. 16 is a circuit diagram of a one-bit shift register. The clock-controlled inverters (95) and (100) are turned on and off simultaneously, and similarly, (97) and (98) are turned on and off simultaneously. When the clock CK is high, data D is input from (95), the output signal Q up to that is held at (99) and (100), and when the CK is low, the inverted clock is made high by (101), The data entered from (95) is (96),
Hold by (97) and (98), (99)
To the output Q. Shift register as shown in Figure 17 transfers data D _S clock CL, successively D _S for each clock period _{(1), D S (2} ), D S (3), ... becomes high I have. In the image display device, the drive circuits for the column electrodes as described above are mounted on the upper and lower sides of the substrate, and the odd-numbered column electrodes supply image signals from the upper drive circuit, and the even-numbered column electrodes supply image signals from the lower drive circuit. The following configuration is adopted. If you are using the timing of FIG. 17 on the upper side of the drive circuit, and the data obtained by delaying a half period of the clock CL of the D _S is below the drive circuit, using an inverted clock CL. As a whole, the image signal is sampled and held every half cycle of the clock. In displaying a television image, a driving method of a simple line sequential system is usually used. In one horizontal scanning period, the image signal of the pixel group of one row of the image display device is updated, and in one field period of the NTSC television signal, the pixel group of 240 rows of one frame of the image display device is driven.

[Problem to be Solved by the Invention] In a high-definition image display device in which the number of rows is doubled to 480 and the number of columns is 480 or more, an image of a pixel group in one row is half of one horizontal scanning period. A double-speed line sequential method of rewriting signals and driving two rows of pixel groups in one horizontal scanning period is used. 48
It has a pixel group of 0 rows, for example, called a triangle or delta, and for a pixel arrangement shifted from row to row, the conventional column-side drive circuit is a multiple of the TAB IC with an integrated circuit mounted on a flexible substrate. It is necessary to sequentially supply the image signals sampled and held during one horizontal scanning period from different TAB ICs to the same column electrode every half period of one horizontal scanning period. There is a problem that mounting is difficult and it is difficult to realize a high-definition image display device.

[Means for Solving the Problems] The present invention can use as many ICs as the number of terminals required to supply signals to column electrodes without increasing the number of TAB ICs driving the image display device. It is another object of the present invention to obtain an integrated circuit for driving an image display device which can suppress the number of elements to be formed into an IC to be lower than a multiple and can perform a double-speed line sequential driving. In order to achieve the object, the present invention provides a shift register, a sample-and-hold circuit that turns on a data switch at each output of the shift register, and samples and holds an image signal of a data line, and a sample-and-hold image. And a buffer amplifier to which a signal is input. The driving circuit of the image display device, wherein the image display device sandwiches the liquid crystal between the substrates and drives the liquid crystal with an active element provided for each pixel. An image signal is given to the inside of a drive circuit composed of an integrated circuit, and a multi-phase clock obtained by dividing a single-phase clock by the number of clocks required according to the number of column electrodes to be driven. A clock is provided, a half-bit shift register is connected in multiple stages, and one half-phase clock is input to each half-bit shift register. Two registers are provided, and two sample and hold circuits are provided to sample and hold the image signal of the data line at the output timing of each shift register, and the sample and hold circuit is provided at each output timing of the shift register during one horizontal scanning period. The data switch is turned on to sample the image signal of the data line, and the image signal is transferred to the buffer amplifier by the enable signal in the horizontal retrace period following the sampling period of one horizontal scanning period, and the image signal is located corresponding to the same column electrode. The output of each buffer amplifier connected to the outputs of the two sample-and-hold circuits is sequentially and selectively output to the terminal of the column electrode every half of one horizontal scanning period to perform double-speed line sequential driving. A driving circuit for an image display device.

FIG. 1 is a configuration diagram of a drive circuit of an image display device according to the present invention. One system is a half-bit shift register (1)
Are connected in multiple stages, and the shift register of the other system also has a similar half-bit shift register (2) connected in multiple stages. (3) and (4) are one-phase clocks CL and CL ', respectively.
Is divided by 1 / N to generate an N-phase clock. One system is a clock of φ ₁ , φ ₂ , φ ₃ ,..., And the other system is φ ₁ ′, φ ₂ ′, φ
₃ ', in ... of the clock, and transfer the data D _S in the shift register. The reset signal R is used to bring the frequency divider into an initial state during the horizontal flyback period. The data switch (5) is sequentially turned on and off at the output timing of each half-bit shift register, and the image signal of the data line is sampled and held in the data capacity (6). After stored the image signal of one horizontal scanning period to each data volume in synchronization with the high enable signal W _O of the horizontal retrace period to turn on the transfer switch (7), the signal on the input capacitance of the buffer amplifier (8) Is transferred and converted into a signal of low output resistance by a buffer amplifier. In view of the sampling order, the output of each of the two buffer amplifiers located corresponding to the same column electrode has one output terminal via a select switch (9) and the other output terminal via a select switch (10). And the image signal of the system selected by the select signals W and W ′ is
D (1), D (2), D (3),... Are supplied to the column electrodes. The data line on which the image signal is sampled and held at each output timing of the shift register has image signals D ^A , D ^B , and ^B (one of which corresponds to red (R), green (G), and blue (B)).
Three data lines D ^C, D ^A which is the other system corresponding to three colors similar ', D ^B', is composed of D ^C 'three data lines, individually wiring each line in the integrated circuit Have been. P is a signal for selecting the output pulse width from the shift register. By selecting a high (V _DD ) or low (V _SS ) signal,
The sampling pulse width for controlling the data switch of the sample-and-hold circuit configured in units of (5) to (9) and (10) can be changed. O _S is the buffer output of the shift register of the integrated circuit the final stage, a signal which is a data input of the next integrated circuit. V _DD , V _SS , V _BB (V _DD > V _SS ≧
V _BB ) is a power input for driving the circuit.

[Operation] In the present invention, a shift register and a sample-and-hold circuit are formed in two systems in an integrated circuit, and a half-bit shift register is used as a unit of a circuit element of the shift register. And the number of elements are almost the same, and a single-phase clock is divided into a multi-phase clock, and the data of the shift register is transferred by the multi-phase clock. The signal processing of the drive circuit is simple with the phase clock. By using two circuits, the image display device can be driven in a double speed line sequential system. If one system image signal is supplied to the column electrode during one horizontal scanning period by the select signal W or W ′, driving can be performed by a simple line sequential method.

[Embodiment] FIG. 2 is a circuit diagram for generating single-phase clocks CL and CL 'which are the basis for generating a multi-phase clock for a shift register of two circuits in a drive circuit of an image display device according to the present invention. . When the clock state setting input S is open, low (V _SS ), and high (V _DD ), S1, S2, and S3 are selectively set to high, and the clock CL of one system is different from the clock CL of the other system.
CL ′ is the same or delayed clock. CL is an inverter an clock input CL _O (28), a phase of the clock transmitted through (29), in S1 is high, the CL 'at CL _O phase with (22) a clock-controlled inverter (23) is there. When S2 is high, ▲ ▼ is also high, (2
5), (24) and the delay element (27) for a fixed time make CL '
Is a signal delayed by a certain time from CL. Similarly, when S3 is high, ▲ ▼ is high, (26), (24) and (27),
Further, a signal delayed by a time obtained by adding a half cycle of the clock to the fixed time by the inverter according to (22) is defined as CL ′. Figure 5 timing chart, D _S (1) of FIG. 6, D _S
(2), D _S (3),..., The output timing of the shift register of one system is sequentially shifted by one period of the base one-phase clock CL. When the driving circuits of the pixel display device are arranged on the upper and lower sides of the substrate for odd columns and even columns, inverted clocks ▲ ▼ and ▲
Since ▼ 'is used, the pixel pitch corresponds to a half cycle of the clock, and if the same signal is used for CL and CL', the arrangement is such that there is no pixel shift for each row, and CL 'is a signal delayed for a certain period of time, for example, 1/4 clock cycle. If there is, the pixels are shifted by half a pitch every other row, CL '
If the signal is delayed by 3/4 clock cycle, it is selectively used for driving an arrangement shifted by one and a half pitches every other row. The delay element (27) is configured such that a delay line is connected between the output terminals of (25) and (26) and the input terminal of (24), or the delay time is determined by resistance and capacitance. In the case where the input / output terminals of (25), (26) and (24) are directly connected to the outside of the integrated circuit, they are formed by attaching a capacitor or the like. The state setting circuits (11) to (21) connect the resistors (11) and (12) that divide the voltage between the power supply V _{DD and} V _SS to 1/2, and connect the comparator (1) to the input terminal S.
Connect the non-inverting and inverting input terminals of (6) and (17), divide the power supply by 1/3 with resistors (13), (14), and (15).
(V _DD −V _SS ) /
Connect the reference potential of 3, 2 (V _DD- V _SS ) / 3 to (16), (1
The outputs of 7) are NAND (18), and the outputs of S1 and (16) are inverted by (20) through inverter (19) and the outputs of S2 and (17) are inverted by (21) to S3. When S is open (1
The outputs of 6) and (17) are each high, S1 is high,
▲ ▼, S2, S3 are low, and when S is low (16), (1
7) Output low and high from S2, ▲ ▼ is high, S1, S
When 3 is low and S is high, (16) and (17) output high and low, so S3, ▲ ▼ is high, S1 and S2 are low, and the tri-state clock C to CL by input of S is output.
L 'can be set.

FIG. 3 is a circuit diagram for generating a two-phase or three-phase clock as a multi-phase clock in the drive circuit of the image display device of the present invention. Inverted output of the 1-bit shift register (37) (3
When the transfer clock selection input T is low, the 1/2 frequency divider circuit having 8) as a data input turns on (45) to (50) according to (57) and passes through (51) to (56). As shown in FIG. ₅ , a clock having the same phase as φ ₁ , φ ₃ , and φ _5, and a phase opposite to φ ₂ , φ ₄ , and φ ₆ and having a period twice that of the clock φ is output. The one-bit shift registers (30), (31), and (32) are connected in three stages, and the second stage is clocked in phase opposite to the other stages by (34), and the output of the third stage is (35) The 1/3 frequency divider circuit in which the data is inverted at the first stage and the clock is inverted by the output of the third stage at the exclusive OR (33), when T is high, (39) to (44) ) Is turned on, and through (51) to (56), as shown in FIG. 6, φ ₂ and φ ₅ are changed with respect to φ ₁ and φ ₄ .
1/3 clock cycle, φ ₃ and φ ₆ are shifted by 2/3 clock cycle by (36), and output clocks having a cycle three times as large as clock φ. R is a signal which becomes high at the beginning edge of the D _S which is a data input of the shift register of the driving circuit shown in FIG. 1 with the start signal of the enable signal W _O the same signal or horizontal scanning, (30) - (32 ), Initialize the output of the frequency divider circuit of (37). As φ, CL or CL ′ in FIG. 2 is used.
However other circuit strains of such clock φ is CL 'of the CL of FIG. 5, the (30) - (32), the shift register of R S ₁ is high, S ₁ is low (37) 5 and 6, the signal is cleared by a signal in which the change of R from high to low is half a cycle of CL. In this circuit, (31) and (32) can be half-bit shift registers into which data is written when the clock input CK is high. When φ is CL, φ ₁ to φ ₆ are sequentially input to the shift registers of each stage as transfer clocks of one system of multi-stage connected shift registers. phi is' time it is, phi ₁ to [phi] ₆ are other transfer clock lines phi ₁ 'CL becomes to [phi] _6'.

FIG. 4 is a circuit diagram of a shift register and a data input portion of the drive circuit of the image display device of the present invention. (58) is a phi ₁ one-bit shift register and a clock, the start signal D _S of the horizontal scanning and data, FIG. 5, at the rising edge of the as shown in FIG. 6 CL and transfers signals D _S D output as _S (0), outputs one of the signals of one cycle high clock phi ₁ of the multiphase clocks. For the data input of the shift register in which the half-bit shift registers described in FIG. 1 are connected in multiple stages, both circuits use this D _S (0).
(59) - constitute a half-bit shift register with (62), phi ₁ is data D _S (0) is inputted from a high (59), the data in the phi ₁ is low by (62) (60) , (6
Hold in 1). (63) - (66) is the next stage of the shift register which operates at a clock phi _2. (56), (6
The output pulse width selection signal, the second-stage output ▲ ▼, and the first-stage output Q (1) are input to the OR-AND of (8), and the ON / NAND output is changed to V _DD −V at (69) to (71). _{From SS}
The level is converted to a signal of V _DD -V _BB and output as D _S (1). Generally, D _S (M) is ▲ ▼, ▲ ▼, Q
(M), and when P is low, in FIG. 5 and FIG.
_{D S (1), D S} (2), D S (3), as shown ... in Q (M)
Same timing as (M = 1,2,3, ...), d when P is high
_{As shown in S} (1), d _S (2), d _S (3), ..., Q (M)
The sampling pulse is output at the same timing as ▲ ▼. A configuration may be adopted in which the transfer clock of the M-th stage shift register is input instead of ▲ ▼ to change the pulse width. The shift register of the other of the two systems uses φ ₁ ′, φ ₂ ′, φ ₃ ′,... As a transfer clock in the circuit configuration of (58) and thereafter shown in FIG.

FIG. 7 is a configuration diagram of a data line for transmitting an image signal of the drive circuit of the image display device of the present invention. Each line consists of a plurality of data lines, the one system R, G, image signals D ^A corresponding to B, D ^B, three data lines D ^C, the other system (7
2) The three data lines D ^A ′, D ^B ′, and D ^C ′ connected to one of the data lines via the selection switches of (80) are individually wired inside the integrated circuit. I have. When the input is K, V _DD -V of the state setting circuit as shown in FIGS.
Outputs converted from _SS to V _DD -V _BB are designated as K, K1, K2, and K3 corresponding to S, S1, S2, and S3. When K is open and K1 is selectively high, the selection switches (72), (73) and (74) are turned on, and the data lines D ^A ′, D ^B ′ and D ^C ′ are D ^A and D ^B, are connected to the data lines D ^C. When K is low and K2 is high (7
5), (76), (77) is turned on, D ^B, D ^C, each data line ^{D A D A ', D B} ', connected to the data line of the D ^C ', K is high K3
In but high, (78), (79), (80) is turned on, D ^C, D ^A,
Each data line D ^A of D ^B ', D ^B', are connected to the data line of the D ^C '. 2, 3, 4, and 7 are functionally matched with the drive circuit shown in FIG. 1 and are incorporated in a semiconductor integrated circuit. When the driving circuit is arranged vertically by the concatenation of the order of the column electrodes of the image display device, and the display color is different for each pixel, by setting both S and K to low, the pixels shifted by half a pitch for every other row are obtained. It is possible to drive an image display device having a triangular pixel configuration in which column electrodes transmit image signals. If S is high and K is open, it is possible to display an image display device having a triangular pixel configuration in which a column electrode transmits an image signal of the same color to a pixel shifted by one and a half pitch every other row.

Image signal D ^A double-speed line sequential method of FIG. 8 is an image display apparatus according to the present ^{invention, D B, D C, D} A ', D B', D C ' enable signal W _O,
The timing of the select signals W and W 'is shown. V _{β to} V
Following the sampling period of one horizontal scanning period of the image signal of the potential of _α , there is a horizontal retrace period in which W _O is high, and W for supplying the sampled image signal of one of the two systems to the column electrode is used. There is a high period and a period in which W 'for supplying the sampling image signal of the other system to the column electrode is high, and W' is an inverted signal of W. Of course, the interval of the high (V _DD ) period shown for W and W 'is narrowed, and the low (V _BB ) period is reduced by 50%.
A driving method longer than the duty is also possible.

FIG. 9 shows an enable signal W _O , select signals W and W ′, and row electrode signals of the double speed line sequential system of the image display device according to the present invention. G1, G2, and G3 are signals of the first row, the second row, and the third row. Each row signal has a selection period (V _GG period) of one horizontal scanning period of the image signal, and The next line sequentially enters the selection period every half period. In synchronization with the high of the W _O in each field of the image signals W, W 'becomes successively high, odd rows W are high, even rows W' is an image signal of the high period of the way take into pixel groups respectively ing. The row signal is a signal potential that sets the non-selection period to V _EE (<V _BB <V _β ), and W _O , W, and W ′ convert the V _DD −V _SS signal inside the integrated circuit to V _DD − the signal potential of V _BB, transfer switches, and controls the select switch.

In the double-speed line-sequential driving of the image display apparatus according to the present invention shown in FIG. 10, in the odd field of the television image signal, W ′ and W are sequentially set to high in synchronization with the high of W _O , and in the even field which becomes interlaced scanning. in synchronization with the high of the W _O W, it is sequentially high a W '. As shown by G1, G2, and G3, each row signal has a half period of one horizontal scanning period of the image signal as a selection period, and the next row is sequentially selected for each of the selection period and the synchronization period. A signal for displaying the pixel group of the first row of the image display device with the image signal of the odd field is put into the pixel group of the first row by G1, and a signal for displaying the pixel group of the third row is G2 and G3 is the selection period. By doing so, it is put into the pixel group on the second and third rows. In the even-numbered field, the signal for displaying the pixel group on the second row is put into the pixel group on the first and second rows by setting G2 as the selection period after G1, and the signal for displaying the pixel group on the fourth row is set to three. The liquid crystal is AC-driven by inverting the image signal for each field in the pixel group of the row and the fourth row. If the image signals of the two data lines are input from outside the integrated circuit and inverted for each field, and the signal of one system is inverted for the other, the signal of the pixel inverted for each row Can be displayed. Of course, it is also possible to invert the image signal input to the integrated circuit by the horizontal scanning period and also invert for each field, invert the polarity of the image signal of the pixel group by the row of the image display device, and perform AC driving. .

FIG. 11 is a circuit diagram showing an input portion of an image signal to a data line of a drive circuit of the image display device of the present invention. Forward rotation,
The image signals D ^a , D ^b , D ^c and ^a , ^b , ^c which are the pair of inversions are
Are selected by periodically inverting the signal to be input to each field, and the image signals D ^A , D ^B , and D ^C are inverted periodically. V F input of (87) - from V _DD -V _SS in (89) _DD -V _BB
Level is changed to (81) ~
Turn on the switch of (83) and set D ^a , D ^b , and D ^c to D ^A , D
^B, and transmitted as D ^C, F is high and F2 is high, (84)
~ The switch is turned on the (86), ^{a, b,} and ^c
D ^A , D ^B , and D ^C. Forward, ^a image signal which is a pair of inverted F is low, ^{b, c,} F is high D ^a, D ^b, in the manner to select a D ^c outputs ^{A, B,} and ^C, 11 The image signal of the other system can be configured by inverting the image signal of one system shown in the figure, and the image signal of the other system can be selectively rotated normally with respect to the one system, Alternatively, a selection means can be provided so as to be inverted. In addition to such a configuration, the configuration of FIG. 7 can be modified by adding D ^A , D ^B , D ^C or ^A ,
^By selectively supplying an image signal to the data line from ^B and ^C, it is possible to cope with various pixel arrangements of the image display device and a selective inversion specification of the image signal.

Figure 12 is an enable signal W _O and the select signal W simple line sequential method of an image display device as a reference example illustrates the W '. The clocks of the two circuits are in-phase, a non-inverted image signal is input to one of the systems, and an inverted image signal is input to the other system, and AC is driven by setting W high in an odd field and high in an even field W '.

FIG. 13 shows a simple line sequential system of an image display device shown as a reference example, in which clocks similar to those described in FIG. When the signal is high, the W and W 'signals are inverted for each field, and the image signals input to the pixels for each row and each field are inverted, and the AC driving is performed.

FIG. 14 shows a simple line sequential method of an image display device shown as a reference example, in which an image signal of the other system is used as an inversion signal for one system and an image signal that is inverted for each field is input. The method is shown. In each field, W and W 'are alternately set high for each horizontal scanning period, and the image signals entering the pixels are inverted for each row and each field, and AC driving is performed.

Using the timings of W _O , W, and W ′ in FIG. 14, an image signal that is inverted in each field in a normal rotation for both systems may be input, and an image signal input to a pixel in each field may be inverted to perform AC driving. it can.

[Effects of the Invention] A driving circuit of an image display device according to the present invention includes a shift register and a sample-and-hold circuit, and a clock for transferring data in the shift register for supplying an image signal to a column electrode of the image display device. Has a resolution sufficient to drive a high-definition image display device while maintaining the transfer clock frequency low,
The dual speed line sequential display is performed by using two functions. Note that the driving circuit of the present invention also has a function of performing a display in a simple line-sequential system when the setting is limited to some of the functions. The present invention has a configuration in which selection of clocks of two circuits corresponding to the pixel arrangement of an image display device and selection of a color image signal are also easily performed, and an input signal is set so that a shift register as a unit has a half bit. As a result of the processing, the number of components of the integrated circuit is not so large as compared with the conventional case, and the function and quality are excellent.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a drive circuit of an image display device according to the present invention. 2 and 3 are circuit diagrams for generating one-phase and multi-phase clocks of the drive circuit of the image display device of the present invention. FIG. 4 is a circuit diagram of a shift register and a data input portion of the drive circuit of the image display device of the present invention. 5 and 6 are timing charts showing the operation of the shift register of the drive circuit of the image display device according to the present invention. FIG. 7 is a configuration diagram of a data line for transmitting an image signal of the drive circuit of the image display device of the present invention. 8, 9 and 10 are timing charts of a double-speed line-sequential image display device using the drive circuit of the present invention. FIG. 11 is a circuit diagram showing an input portion of an image signal to a data line of a drive circuit of the image display device of the present invention. FIGS. 12, 13 and 4 are timing charts of a simple line sequential type image display device using a drive circuit shown as a reference example. FIG. 15 is a drive circuit diagram of a conventional image display device, FIG. 16 is a circuit diagram of a one-bit shift register, and FIG. 17 is a timing chart of the drive circuit in FIG. (1), (2): each half-bit shift register serving as a unit of the two circuits (3), (4): each of two frequency divider circuits for generating a multi-phase clock from one phase (5): Data switch (6): Data capacity (7): Transfer switch (8): Buffer amplifier (9), (10): Select switch CL, CL 'for selecting one of two systems of sampling image signals: Two systems One-phase clock input D _S : horizontal scan start signal D ^A , D ^B , D ^C which becomes the data input of the shift register: image signal D ^A 'supplied to one of the two data lines , D ^B ', D ^C ': Image signal supplied to the data line of the other of the two systems W _O : Enable signal W, W ': Select signal for controlling the select switch

Claims (4)

(57) [Claims] 1. A shift register, a sample and hold circuit for turning on a data switch at each output of the shift register to sample and hold an image signal of a data line, and a buffer to which the sampled and held image signal is input A driving circuit of the image display device, comprising: an amplifier; and the image display device drives the liquid crystal by an active element provided for each pixel with the liquid crystal interposed between the substrates, and an image signal is supplied to the column electrode from the buffer amplifier. In the driving circuit composed of integrated circuits, a multi-phase clock obtained by dividing a single-phase clock by the number of clocks required according to the number of column electrodes to be driven is provided, and a half bit is provided. Are connected in multiple stages, and each half-bit shift register has two shift registers with one of the multiphase clocks input. In addition, two sample and hold circuits are provided to sample and hold the image signal of the data line at the output timing of each shift register, and the sample and hold circuit turns on the data switch at each output timing of the shift register during one horizontal scanning period. The image signal of the data line is sampled, and the image signal is transferred to the buffer amplifier by the enable signal in the horizontal retrace period following the sampling period of one horizontal scanning period, and two systems of sample signals located corresponding to the same column electrode are used. An image characterized in that the output of each buffer amplifier connected to the output of the hold circuit is sequentially and selectively output to the terminal of the column electrode every half of one horizontal scanning period, and performs double-speed line sequential driving. A driving circuit of a display device. 2. The driving circuit for an image display device according to claim 1, wherein a polyphase clock of the other system is generated from a one-phase clock as a basis for generating a multiphase clock of one system. . 3. The driving circuit for a pixel display device according to claim 1, wherein the data lines are individually wired for each system inside the integrated circuit. 4. The driving circuit according to claim 1, wherein the data lines are provided in accordance with the number of colors of red, green, and blue, and the image signal is a color image signal.