JP3200261B2 - Distance measuring device and distance measuring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distance measuring device,
In particular, an image formed on a pair of optical sensor arrays of light incident through different optical paths from a distance measurement target, and an image formed on one optical sensor array and an image formed on the other optical sensor array. The present invention relates to a distance measuring device that calculates a degree of correlation while relatively shifting the distance and calculates a distance from a shift amount indicating the highest degree of correlation to a distance measurement target.

[0002]

2. Description of the Related Art FIG. 34 shows a TTL (th
1 shows an example of a phase difference detection type distance measuring device of the rough the lens type. FIG. 34A shows a configuration example, and FIG. 34B shows an example of the processing circuit. A description will be given taking a focus detection device for a camera as an example.

A light beam from an object, which is a subject, is converged by a photographing lens 201, passes through a film equivalent surface 202, and enters a condenser lens 203, a separator lens 2
Reach 04. The separator lens 204 divides the incident light into two light fluxes,
And the reference line sensor 206. The image of the object on the optical axis 208 of the photographing lens 201 becomes two images by the separator lens 204 and forms images on the line sensors 205 and 206, respectively.

The line sensor 205 is called a reference line sensor because it has p light receiving elements and is used as a reference. The line sensor 206 has q more than p light receiving elements, reads out signals from the p light receiving elements while changing the phase, and compares the signals from the reference line sensor 205 with the position. This is for detecting a phase difference, and is called a reference line sensor.

The detection signals from the reference line sensor 205 and the reference line sensor 206 are supplied to a processing circuit 207. While changing the readout phase of the detection signal from the reference line sensor 206, the processing circuit 207 calculates the degree of correlation described later, detects the extreme value of the degree of correlation, and detects the focus position.

It is to be noted that a method has been proposed in which external light is taken in by a pair of lenses having the same characteristics arranged before the reference line sensor and the reference line sensor without passing through the photographing lens 201, and the distance to the object is similarly measured. ing.

FIG. 34B shows a configuration example of the processing circuit 207. The signals from the reference line sensor 205 and the reference line sensor 206 are supplied to the A / D converter 209, and the analog signal is converted into a digital signal. This digital signal is temporarily stored in the RAM 2 via the CPU 210.
11 is stored. After that, the digital signal stored in the RAM 211 is read out, and the CPU 210 performs a correlation operation to detect an extreme value of the degree of correlation, and generates an output signal indicating a distance to the object.

In the focus detection devices shown in FIGS. 34A and 34B, the charge stored in the photosensor is converted from charge to voltage to form a detection signal, which is converted into a digital signal and stored in the RAM 211. The operation is performed by reading out this signal.

In the distance measuring apparatus according to the conventional example, the distance can be measured only in a range where an image is formed on the reference line sensor 205. Normally, an image is formed only at the center of the shooting range of the camera, and distance measurement is performed. Therefore, the main subject is
When it is located at a position shifted from the center of the shooting range, the main subject is not focused.

As a method for solving this drawback, for example, Japanese Patent Publication No. 3-67203 discloses a distance measuring device capable of measuring not only a front direction of a camera but also a distance to a subject in an oblique direction. In this distance measuring device, the reference line sensor is made longer than in the conventional example, and a plurality of reference positions are provided on the reference line sensor. As a result, it is possible to simultaneously measure the distance for a plurality of areas in the shooting range.

[0011]

The phase difference detection type distance measuring apparatus according to the prior art can measure the distance of a subject in an area imaged on a reference line sensor. Normally, the reference line sensor is set so that a subject in a direction perpendicular to the sensor surface forms an image. That is, when the distance measuring device is mounted on a camera, the distance can be measured only at the center of the photographing range.

When the main subject is located at a position deviated from the center of the photographing range, it is necessary to measure the distance from the front of the camera to the direction of the main subject, return the original direction, and press the shutter. is there.

The distance measuring device disclosed in Japanese Patent Publication No. 3-67203 can measure the distance to an object in a diagonal direction of a camera, but the main object is located in any of a plurality of distance measurement ranges. Cannot be determined.
Therefore, the distance to the main subject cannot be calculated from the obtained plurality of distance information. In addition, a plurality of areas that can be measured are fixed in advance, and if the main subject is not in this area, the distance to the main subject cannot be measured.

Further, it is necessary to provide circuits for calculating the degree of correlation by the number of areas to be measured. Therefore, when a large number of ranging areas are provided, there is a disadvantage that the circuit becomes complicated.

After the electric charge stored in the photosensor is read and converted into a digital signal, the electric charge stored in the photosensor disappears. Therefore, when the amount of light is insufficient, for example, the photosensor must be irradiated with light again to generate charges. Therefore, there is a disadvantage that the distance measurement time becomes long.

An object of the present invention is to specify a region where a main subject is located even when the main subject is not located at the center of the photographing range, and to perform distance measurement only on the region. An object of the present invention is to provide a distance measuring technique capable of minimizing the extension of the distance measuring time even when the distance is short.

[0017]

According to the distance measuring apparatus of the present invention, a large number of pixels including an optical sensor for generating an image signal according to the amount of received light are arranged in a straight line, and the pixels pass through spatially different paths. A pair of pixel arrays on which a subject to be measured is imaged, image signal storage means provided for each pixel for storing an image signal generated by the optical sensor, and an image signal from the image signal storage means. An image signal reading means for non-destructively reading the image data, measuring an amount of light applied to the pair of pixel arrays, detecting that a received light amount has reached a predetermined level, and performing an image signal generating operation by the optical sensor. A pair of received light amount detecting means for stopping, a contrast calculating means for obtaining a contrast signal from the image signal read by the image signal reading means, and a maximum value of the image signal A signal level determining means for detecting and storing, and a contrast obtained by the contrast calculating means is lower than a contrast reference level, and a maximum value of the image signal detected by the signal level determining means is a reference signal level. Lower than
An image signal transfer unit for adding an image signal newly generated by the optical sensor to an image signal stored in the image signal storage unit without discarding the image signal stored in the image signal storage unit And

The distance measuring method according to the present invention accumulates photocharges generated by each of the photosensors constituting a pair of photosensor arrays on which a subject to be measured is formed via spatially different paths. A first photocharge storage step, a step of transferring and storing the photocharge to image signal storage means provided for each of the photosensors, and a second light for storing photocharges newly generated by the photosensors A charge accumulation step, a step of detecting a contrast and a maximum received light amount based on the photocharge stored in the image signal storage means, and, when the contrast and the maximum received light amount are equal to or less than a reference value, the second light Adding a photocharge accumulated in the charge accumulation step to the photocharge stored in the image signal storage means.

[0019]

When a sufficient amount of electric charge cannot be obtained in one integration operation for storing an image signal corresponding to the amount of received light, the integration operation is performed again and the electric charge accumulated in the previous integration operation is discarded. Without this, a newly generated photocharge can be added (repeated integration). This is because an electric signal corresponding to the amount of accumulated charges can be obtained without discarding the accumulated photoelectric charges.

In addition, in the repetitive integration operation, the time for the repetitive integration can be adjusted according to the amount of charge accumulated in the first integration operation. As a result, the number of integration operations and repetitive integration operations can be minimized. Therefore, it is possible to shorten the time for the distance measurement.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of a method for measuring a distance to a subject according to an embodiment of the present invention will be described with reference to FIG.

FIG. 2A shows a case where the main subject is located substantially at the center of the screen, and FIG. 2C shows a case where the main subject is divided into left and right sides of the screen and there is no main subject at the center. . Long rectangles 6 on the left and right in the center of the screen indicate a contrast measurement area.

Before the distance measurement, the contrast inside the contrast measurement area 6 is measured. FIGS. 2B and 2D show the contrast values of the objects in FIGS. 2A and 2C, respectively. FIG. 2B shows that the contrast is high in the central main subject portion and low in the distant subject on the right side of the screen. FIG. 2 (D)
This indicates that the contrast is high in the main subject part on the left and right sides of the screen, and low in the center part of the screen.

In the case shown in FIG. 2B, distance measurement is performed on the highest contrast area 7 at the center of the screen.
In the case shown in FIG. 2D, the areas 7a and 7b having high contrast are divided into the left and right sides of the screen, so that the distance measurement is performed on one of them. Note that distance measurement may be performed for both of them, and the average may be obtained.

As described above, by measuring the contrast in a relatively large area of the screen, selecting an area having a high contrast and measuring the distance only in that area, it is possible to focus on the main subject with a high probability. . This is particularly effective when the main subject is not at the center of the screen, as in the case shown in FIG.

Next, an outline of a distance measuring apparatus according to an embodiment of the present invention and its operation will be described. FIG. 1A is a schematic block diagram of a distance measuring device according to an embodiment of the present invention and a relevant portion of a camera body incorporating the distance measuring device. FIG. 1 (B)
1 shows a schematic processing flow of distance measurement by the system shown in FIG.

The distance measuring device includes a photoelectric conversion unit 1, a memory unit 2,
It comprises a contrast operation circuit 3 and an A / D conversion circuit 4. The A / D conversion circuit 4 is connected to a microcomputer 5 of the camera body via an interface port (not shown).

The operation of the distance measuring device will be described with reference to FIG. The photoelectric conversion unit 1 includes a plurality of pixels arranged in a straight line, and generates an electric signal (image signal) according to the amount of received light (step a1). The generated image signal is input to the memory unit 2, and the memory unit 2 stores the input image signal as an analog signal (step a).
2). Specifically, the charge generated in the photoelectric conversion unit 1 is referred to as CC
The data is transferred by D and stored in the MOS capacitor. Pixel, CC
D and MOS capacitors are integrally formed close to each other on a semiconductor substrate, and are connected by various gates.

The contrast calculation circuit 3 includes a memory unit 2
Is input. The contrast calculation circuit 3 outputs an electric signal (contrast information) corresponding to the contrast from the image signal of the adjacent pixel (step a3). The contrast information is input to the A / D conversion circuit 4, converted into a digital signal, and input to the microcomputer 5 of the camera body.

The microcomputer 5 selects an area where the main subject is located based on the input contrast information (step a4). Usually, it is considered that the main subject is located in the area having the highest contrast.

The memory section 2 extracts an image signal of the selected area from all the image signals in accordance with an instruction from the microcomputer 5, and transfers it to the microcomputer 5 via the A / D conversion circuit 4 (step a5).

The microcomputer 5 performs a correlation operation based on the input image signal (step a6). Further, an interpolation calculation is performed from the calculated correlation value to calculate a distance to the subject (step a7).

FIG. 3 is a block diagram showing a distance measuring apparatus according to an embodiment of the present invention. The CCDs 10a and 10b are composed of a plurality of pixels arranged in a straight line. Each pixel is
It has a light receiving element for receiving light and converting it into an electric signal (image signal) according to the amount of received light, and a memory for storing the image signal. This image signal forms an image signal sequence according to the light intensity distribution. The CCDs 10a and 10b are left and right CCDs for defining a base line (base) of a triangle having a subject as one vertex for performing triangulation.

AGC (automatic gain control) monitors 8a, 8b
Are each composed of one light receiving element, and are used to adjust the integration time for generating image signals by the left and right CCDs 10a and 10b. The AGC monitors 8a and 8b are irradiated with light amounts corresponding to the total light amounts irradiated on the pixels of the CCDs 10a and 10b, respectively, and the sum of the light reception amounts of the pixels is output as an electric signal. By dividing this by the number of pixels, the average value of the amount of received light of each pixel can be obtained.

The AGC circuit 9 includes AGC monitors 8a and 8
From b, an electric signal corresponding to the amount of received light is input. AGC
The circuit 9 compares the input electric signal with a reference value, and
The end of charge integration by the CDs 10a and 10b is determined.
That is, the integration operation ends when the average value of the light reception amounts of the pixels of the CCDs 10a and 10b reaches a constant value.

The pixel selectors 11a and 11b select pixels from which signals in the CCDs 10a and 10b are read. Specifically, it is constituted by a shift register, and can sequentially designate and scan each pixel arranged linearly. A large number of continuous pixels are divided into a plurality of pixel groups, and the start position and the end position of the scan can be designated in pixel group units.

When selected by the pixel selectors 11a and 11b, the image signal stored in the memory of the pixel is read and sent to the CCD signal processing circuit 12. At this time, information stored in the memory of the pixel can be read nondestructively without being erased. Therefore, the image signal can be read out a plurality of times only by performing one photoelectric conversion process (integration operation).

Further, by repeatedly performing the integration operation by the CCDs 10a and 10b, the image signal stored by the previous integration operation can be additionally stored (hereinafter referred to as "repetitive integration") without initial setting. it can.

The CCD signal processing circuit 12 shapes the waveform of the image signal read out via the pixel selectors 11a and 11b, gives a gain, and the like. The image signal that has been subjected to waveform shaping and provided with a gain is input to a contrast calculation circuit 13 and an A / D conversion circuit 14.

The contrast calculation circuit 13 calculates the absolute value of the difference between the image signals of adjacent pixels from the image signals continuously output for each pixel from the CCD signal processing circuit 12, and calculates the absolute value for each pixel group. Add sequentially. The signal obtained by the addition in this manner corresponds to the contrast in the scanned range. This contrast signal is sent to the A / D conversion circuit 14 for each scan. For example, by performing scanning for each pixel group, a contrast signal can be obtained for each pixel group. By performing a plurality of scans in this way, contrast can be obtained for a plurality of areas within the photographing range.

This contrast signal is supplied to the A / D conversion circuit 1
The digital signal is converted into a digital signal by 4 and output to the microcomputer on the camera side via the serial port 16 and the input / output circuit 19.

The image signal for each pixel is directly converted to A /
The signal is input to the D conversion circuit 14 and is converted into a digital signal. The image signal for each pixel converted into a digital signal is output to the microcomputer on the camera side via the serial port 16 and the input / output circuit 19. Further, this image signal is input to the signal level determination circuit 15.

The signal level determination circuit 15 determines the value of the image signal for each pixel within the scanned range, and stores the maximum value, that is, the output level of the pixel irradiated with the maximum amount of light. This maximum output level is output to the microcomputer on the camera side via the serial port 16 and the input / output circuit 19 in the form of flag data.

This is used in the following cases. That is, when scanning all the pixels of the CCD 10a or 10b in order to select the area having the maximum contrast, the integration operation ends when the average of the output values of the image signals of all the pixels reaches a certain level. Therefore, when the light amount in the area without the main subject is strong, for example, in the case of backlight, the light reception amount in the area with the main subject relatively decreases, and a sufficient dynamic range for distance measurement cannot be secured. Sometimes. In such a case, it is used to determine whether or not to perform the renormalization integration.

The serial port 16 converts a parallel signal such as a contrast signal and an image signal into a serial signal, and sends the serial signal to the microcomputer on the camera side via the input / output circuit 19. The above-described designation of the operation mode of the distance measuring apparatus, the start position and the end position of the scan, the designation of the scan start, and the like are all performed by command input from the microcomputer on the camera side. This command is input to the serial port 16 via the input / output circuit 19.

The instruction decode circuit 17 translates a command input from the microcomputer. Sequence control circuit 18
Generates various timing signals used in each block in the distance measuring device based on the translation result of the command.

The temperature detection circuit 20 includes the CCDs 10a, 10
The temperature of the substrate on which b is formed is detected, converted into an electric signal, and input to the A / D conversion circuit 14. The temperature is converted into a digital signal by the A / D conversion circuit 14 and transferred to the camera microcomputer via the serial port 16 and the input / output circuit 19.

The distance measuring device is a molded product made of plastic or the like and thermally expands, so that the left CCD 10a and the right CCD 10b
Varies with temperature. Therefore, the base line length of the triangulation varies. Therefore, in order to calculate an accurate distance, it is necessary to correct the base line length based on the temperature at the time of distance measurement. The temperature detected by the temperature detection circuit 20 is used for correcting the base line length.

Next, a command input from the camera microcomputer will be described. Each command is composed of a total of 8 bits including a 4-bit operation code portion and a 4-bit operand portion.

The function of each command will be described below in detail. The PGC command is a command for controlling each gate of the CCDs 10a and 10b, and is used at the time of testing the distance measuring device itself and at the time of integration by integration. The operation code part is “0001”, and the operand part has bgc, cgc,
Any combination of the three types of tgc can be specified. When bgc is designated, the BG gate of the charge transfer unit of the CCDs 10a and 10b described later is turned on. Similarly, when cgc and tgc are specified,
The CLG gate and the TG gate are turned on, respectively.

The RGC command is also a command for controlling each gate of the CCDs 10a and 10b, and is used when testing the distance measuring device itself. The operation code is "0010"
And p1c, p2c, fgc, ce
Any combination of the four types of c can be designated. When p1c is specified, CC described later is used.
D10a, to turn on the phi ₁ gate of the read portion of 10b. Similarly p2c, fgc, when cec is specified, respectively phi ₂ gates, FGB, to turn on the CE gates.

The MDC command is a command for controlling each operation mode of the distance measuring device. The operation code is “0011”, and the operands are slp, eoi,
Any combination of the three types of agc can be specified.

When slp = 1 is specified, the distance measuring apparatus enters a sleep mode in which current consumption is reduced as much as possible. The distance measuring device includes an analog element such as an operational amplifier, a digital element such as a logic circuit, and a CCD. Among them, the logic circuit is formed of CMOS, and if the supply of the clock is stopped, the current consumption is almost eliminated. Also,
In the CCD, no current flows when each gate is turned off. Therefore, in order to suppress current consumption, it is necessary to stop the current flowing through the constant current source of the analog element. In the sleep mode, the current flowing through the constant current source is stopped, and the current consumption of the entire distance measuring apparatus can be reduced as much as possible.

When slp = 0 is specified, a normal mode is set, and normal operations such as contrast calculation and distance measurement can be performed. If eoi = 0 is specified,
Service request terminal S connected to the camera body
EOI that outputs an integration end signal (EOI signal) from RQ
Mode. This mode is automatically set after the initial setting of the distance measuring device, and the camera microcomputer can shift to the next processing by detecting the EOI signal from the service request terminal SRQ.

When eoi = 1 is specified, the command execution ends from the service request terminal SRQ, and A /
The mode becomes the EOC mode for outputting the D conversion end signal (EOC signal). In this mode, the microcomputer on the camera side can detect the end of the command execution and transmit the next command. When the scanning operation is performed, the end of the A / D conversion can be detected, and the data of the scanning result can be received from the serial port 16.

Whether the EOC signal indicates the end of the command or the end of the A / D conversion can be determined by the execution command. However, since there is no means for distinguishing whether the EOI signal or the EOC signal is output to the service request terminal SRQ, it is necessary to set an EOI mode or an EOC mode in advance with an MDC command.

When agc = 0 is designated, a normal mode for automatically terminating the integration operation is set. In this mode, the AGC circuit 9 operates, and when the amount of received light reaches a predetermined value, the integration operation is automatically terminated.

When agc = 1 is specified, the test mode is set in which the integration operation is not automatically terminated. In this mode, the AGC circuit 9 does not operate, and the integration time can be externally terminated. This mode is for CCD 10a, 10b
It is used for testing of the light receiving element.

The TRT command is sent to the CCD 10a, 10b
Is a command for transferring the electric charge accumulated in the light receiving element of each pixel to the memory unit. The operation code section is "010
0 ", and there is no parameter in the operand portion.

The SCT command is a command for instructing the start of scanning. The operation code section is "010
1 ", and m / p, l, and r parameters can be specified in the operand portion.

When m / p = 0, it indicates that the pre-scan is performed. Here, the pre-scan means the CCD1
This refers to a scan for reading the calculation result of the contrast for each pixel group of 0a and 10b.

When m / p = 1, it indicates that the main scan is executed. Here, the main scan is CC
This refers to scanning for reading out the image signals of the pixels D10a and D10b for each pixel.

When l = 1 and r = 0, the left CCD 10
a, and if l = 0 and r = 1, the right C
Scan the CD 10b. If l = 0 and r = 0, a dummy scan is performed. Here, the dummy scan refers to scanning by inputting a constant voltage to the contrast calculation circuit 13 and is used for the following purposes.

An analog amplifier is used for the contrast calculation circuit 13, and this output has an offset. When calculating the contrast of the scan range,
This offset is superimposed by the number of integrations. Dummy scan is performed to remove the influence of this offset. That is, when a dummy scan is performed, an integration result of only the offset can be obtained. By subtracting the integration result of the offset only from the integration result of the contrast obtained by performing a normal scan, the integration result of only the contrast can be obtained.

When l = 1 and r = 1, temperature information is read. This is used to correct the baseline length of the triangulation as described above. The SAS command is
This is a command for setting a scan start address. The operation code portion is "1000", and 16 addresses can be designated by a 4-bit operand portion.

The EAS command is a command for setting a scan end address. The operation code portion is "1001", and 16 addresses can be specified by a 4-bit operand portion, similarly to the SAS command.

FIG. 8 shows the relationship between the pixels on the CCDs 10a and 10b and the scan addresses. CCDs 10a and 10
b is composed of 160 pixels arranged linearly. Eight pixels at both ends of the 160 pixels are dummy pixels that are not used during actual distance measurement. 144 pixels excluding 16 pixels at both ends are pixels used at the time of distance measurement. The 144 pixels are divided into 12 pixel groups consisting of 12 consecutive pixels. Addresses from 2 to D (hexadecimal) are sequentially assigned to the twelve pixel groups.

The light receiving portions of the four dummy pixels (black dummy pixels) at both ends are shielded from light by a metal film or the like. Addresses 0 and F are respectively assigned to a pixel group at both ends composed of four black dummy pixels. A pixel group consisting of four pixels (white dummy pixels) inside the black dummy pixels has addresses 1 and E, respectively.
Is assigned.

As described above, an arbitrary pixel group can be specified by 16 addresses from 0 to F. The reason that the eight pixels at both ends are not used for distance measurement is that both ends of the light receiving element arranged in a straight line and the other parts,
This is because characteristics such as sensitivity are different.

The GNS command is sent to the CCD signal processing circuit 1
2 and a command for setting the gain of the contrast calculation circuit 13. The operation code portion is “1010”, and any combination of cds and con can be specified in the operand portion. Also, the remaining 2
The gain can be specified in four stages with bits. cd
When s = 1, the gain of the CCD signal processing circuit 12 is represented by c
When on = 1, the gain of the contrast calculation circuit 13 is set.

The ALS command is a command for setting the level of the AGC circuit 9. The operation code section is "1
011 ", and l / r can be specified in the operand portion. The level can be set in five steps with the remaining 3 bits. When l / r = 1, the level of the left AGC monitor 8a Is set, and when l / r = 0, A for right
The level of the GC monitor 8b is set.

This is used, for example, when photographing an object in which a person on a dark stage is illuminated by a spotlight. Since the person who is the main subject is brighter than the background, if the integration operation is performed until the average of the amount of received light of each pixel reaches the reference value, the image signal of the pixel in the area where the main subject is present overflows. Therefore, in such a case, it is necessary to lower the reference value and perform the integration operation again.

Conversely, in the case of a backlit subject, since the background is bright, if the integration operation is terminated when the average of the amount of light received by each pixel reaches the reference value, the image signal in the area of the main subject may be too weak. become. If the integration is repeated, the image signal is superimposed, and an image signal with sufficient strength can be obtained, but the number of integrations increases. In such a case, by increasing the reference value and performing repetitive integration again, an image signal having sufficient strength for distance measurement can be obtained by at least two integration operations.

The HLT command is a command for forcibly terminating the scanning operation. The operation code portion is “1110”, and there is no parameter in the operand portion. For example, when starting a scan and waiting for a response,
If the camera microcomputer receives another interrupt,
used.

The SWR command is a command for performing a software reset. The operation code section is "111
1 "and no parameter in the operand section. By performing a software reset, the CCDs 10a, 10a
The image signal stored in the memory b is initialized and the integration operation is started. At this time, the reference value of the AGC circuit 9,
The gain and the like of the CCD signal processing circuit 12 are not initialized.

When a reset signal is received from a reset terminal connected to the camera body, the integration operation is similarly started.
, The gain of the CCD signal processing circuit 12, etc. are all set to the initial values. Therefore, when the reference value of the AGC circuit 9 is changed and the integration operation is performed again, the software reset is used.

Next, the configuration and function of each block of the distance measuring apparatus will be described in detail. FIG. 4 shows a circuit of the serial port 16. 8 flip-flops 30a-3
0h are connected in series to form an 8-bit shift register 30. Top flip-flop 30a
, A serial input signal SI is input from the microcomputer on the camera side.

CK of each flip-flop 30a-30h
The terminal is connected to the serial clock SCK from the camera microcomputer.
Is supplied. Q terminal of the flip-flop 30a~30h respectively form outputs input data SI ₇ ~SI _0, input data is supplied to the distance measuring device.

The parallel data SO _{7 to} SO ₀ are sent from other blocks in the distance measuring device to the NAND gates 31a to 31a, respectively.
31h is provided to one input contact. The serial port load signal SPTLD is input to the other input contact of the NAND gates 31a to 31h. Outputs of the NAND gates 31a to 31h are connected to (-PR) terminals of the flip-flops 30a to 30h, respectively. Here, the minus sign indicates negative logic.

The control circuit 33 receives a read / write identification signal RW from the camera microcomputer. further,
The control circuit 33 is connected to the (-CL) terminals of the flip-flops 30a to 30h, and sends out a clear signal based on the read / write identification signal RW.

The counter 32 has a serial clock SC
K is supplied. The counter 32 counts clock pulses, and outputs a carry-out signal (-CO) when eight pulses are counted.

The Q terminal of the flip-flop 30h is connected to the D terminal of the flip-flop 34. A signal obtained by inverting the serial clock SCK is supplied to the CK terminal. The Q terminal of the flip-flop 34 sequentially forms and outputs a serial output signal SO in synchronization with the serial clock SCK.

FIG. 5 is a timing chart when data is input from the serial port 16. A serial clock SCK is supplied from the camera-side microcomputer, and a serial input signal SI is input in synchronization with the serial clock SCK. Specifically, each bit bi ₀ of the input data
To bi ₇ are sequentially supplied.

At the first pulse of the serial clock, the 0th bit bi ₀ of the input data is latched by the flip-flop 30a. The first and subsequent bits are sequentially latched in synchronization with the serial clock. At the same time, the latched bits are sequentially transferred in the shift register 30.

When the serial clock pulse is counted eight times, the counter 32 outputs the carry-out signal (-C
O) is output to. At this point, the flip-flop 30a
To 30h are the respective bits bi _{7 to} b of the input data.
i ₀ is latched. That is, the input data SI ₇ to
The SI _0, each bit bi ₇ ~bi ₀ of the input data is output.

Here, the upper 4 bits bi of the input data₇
~ Bi_FourIndicates the opcode part of the command, and the lower 4 bits
Tobi_Three~ Bi₀Represents an operand part. Therefore, in the future
To distinguish between the opcode part and the operand part, enter
Data SI₇~ SI_FourIs OC _Three~ OC₀, Input data S
I_Three~ SI₀OR_Three~ OR₀It may be expressed as

FIG. 6 is a timing chart when data is output from the serial port 16. When the read / write identification signal RW falls and a data output is requested, the control circuit 33 causes the flip-flops 30a to 30h
A clear signal (-CL). Thus, flip-flop 30a~30h is initialized, Q contacts SI ₇ ~SI ₀ of each flip-flop 30a~30h is initialized.

[0088] The output data SO ₇ to SO _0, has appeared each bit bo ₇ to Bo ₀ of the output data. When the serial port load signal SPTLD is applied, the bits bo _{7 to} bo ₀ of the output data are latched by the flip-flops 30a to 30h, respectively. This allows
The Q contacts SI ₇ ~SI ₀ of each flip-flop appears each bit bo ₇ to Bo ₀ of the output data.

When the first pulse of the serial clock SC is applied, the data SI ₀ appearing at the Q contact of the flip-flop 30h is latched by the flip-flop 34, and the output data SO has the output data bit bo.
₀ appears. At the same time, flip-flops 30a-30g
Is transferred in the shift register 30.

In this manner, by applying the second and subsequent pulses, the output data bo _{1 to} bo ₇ appear in the output data SO sequentially. When all the bits have been output, the counter 32 outputs a carry-out signal (-CO).

FIG. 7 shows the instruction decode circuit 17. Input data OC _{3 to} OC input to serial port 16
₀ is supplied to the instruction decode circuit 17. That is, the operation code part of the input command is supplied. Further, a carry-out signal (−
CO) is supplied.

The operation codes OC _{3 to} OC ₀ supplied from the serial port 16 are decoded by decoding circuits 40 a to 40 k each including a NAND gate and a NOR gate.
It is provided to one input contact of ND gates 41a to 41k.

AND gate or NAND gate 41a
The carry-out signal C
O is supplied. Therefore, the decoding circuits 40a to 40k
The result decoded according to the operation code by
Signals PGC, RGC, MDC, (−TRT), (−) corresponding to each operation code in synchronization with carry-out signal CO.
SCT), SAS, EAS, GNS, ALS, (-HL
T), output as SWR.

The signals corresponding to the respective operation codes are input to the sequence control circuit 18. Sequence control circuit 18
Generates a timing signal necessary for each block in the distance measuring apparatus based on a signal corresponding to each operation code.

Next, referring to FIG. 8 to FIG.
a and 10b will be described. FIG. 8 shows a CCD 10a,
10b shows the configuration of each pixel. As described above, each of the CCDs 10a and 10b is composed of 160 linearly arranged pixels.

FIG. 9 is an enlarged view of one pixel. FIG. 9A is a plan view. Pixels are linearly arranged in the vertical direction in the figure. The upper diagram in FIG.
FIG. 9A is a cross-sectional view taken along the line AA ′, and the lower part of FIG. The clear gate CLG and the clear drain CLD are formed at positions deviated from the AA ′ direction in the plan view, but are shown in the same cross section for the sake of explanation in the cross sectional view. Therefore, although the storage gate ST is described as being separated into two in the cross-sectional view, the storage gate ST is actually integrated.

An n ⁻ -type buried channel 51 is selectively formed on the surface of a p-type substrate 50, and the periphery thereof is p-type.
⁺ Are surrounded by regions 52a and 52b. At one end of the buried channel 51 on the p ⁺ region 52a side, an overflow drain OFD of the n ⁺ region is formed. Since the p ⁺ regions 52a and 52b form a potential barrier for the electrons, the electrons accumulated on the substrate surface are transferred in the n ⁻ region 51 only in the AA ′ direction in the figure.

Light receiving area PD and overflow drain OF
An overflow gate OFG having an insulated gate structure is formed between D and D. Overflow gate OFG
Is applied with a constant voltage so as to form a potential barrier for electrons generated in the light receiving region PD. Also,
A power supply voltage is always applied to the overflow drain OFD, and electrons that have crossed the potential barrier below the overflow gate OFG flow into the overflow drain OFD.

A barrier gate BG having an insulated gate structure, a storage gate ST, a transfer gate TG, and a first CCD are provided between the light receiving region PD and the p ⁺ region 52b.
The gate φ ₁ , the second CCD gate φ ₂ , and the floating gate FG are formed in this order with a slight overlap while maintaining insulation.

In the direction perpendicular to the AA ′ direction of the region where the storage gate ST is formed, the clear gate CLG and the clear drain CLD having the insulated gate structure are formed as described above. Clear drain CLD
, The power supply voltage is always applied, and the clear drain CLD
Is set to be lower ( higher potential) than the potential of the channel region (storage region) below the storage gate ST. Where the potential
Is the potential energy for electrons. Less than
The same applies to the following description.

Therefore, by applying a positive voltage to the clear gate CLG to make the potential of the channel region below the clear gate CLG lower than the potential of the storage region, the electrons accumulated in the storage region can be reduced.
All can be discharged to the clear drain CLD.

On the floating gate FG, a gate FG2 connected to the ground potential is formed via an insulating film, and the floating gate FG and the gate FG2 form a capacitor. This prevents the potential of the floating gate FG via the interlayer insulating film from fluctuating significantly when signal charges are injected.

The floating gate FG is connected to the MO
It is connected to the floating gate bias voltage FGB via the S transistor TR1, and to the inverting input contact of the operational amplifier AMP1 via the MOS transistor TR2. The gate electrode of MOS transistor TR1 is connected to gate voltage CE. The gate electrode of the MOS transistor TR2 is connected to the selection contact KCn of the pixel selectors 11a and 11b as shown in FIG.

The non-inverting input terminal of the operational amplifier AMP1 is connected to the analog reference voltage Vref. Operational amplifier A
The output contact of MP1 is fed back to the inverting input contact via a parallel connection of a capacitor C1 and a switch SW1 controlled by a preset signal PR. The output contact forms an output signal CCDOUT. In this manner, a change in the potential of the floating gate FG is output as a signal via a switched capacitor circuit using an operational amplifier.

FIG. 10 shows the drive timing of the CCDs 10a and 10b. FIGS. 11A to 11E are potential diagrams showing the integration start operation. First, as shown in FIG. 10, the barrier gate BG and the clear gate CLG are in a high voltage state (ON state), and the gate voltage CE is in a high voltage state. Further, the transfer gate TG, the CCD first gate φ ₁ , the CCD second gate φ ₂ , and the floating gate bias voltage FGB are in a low voltage state (OFF state) (FIG. 11A).

At this time, since the barrier gate BG and the clear gate CLG are in the ON state, electrons constantly generated in the light receiving region PD are discarded to the clear drain CLD via the storage region. Since the gate voltage CE is in the high voltage state, the MOS transistor TR1 is turned on, and the floating gate bias voltage FGB is applied to the floating gate FG.

Next, the transfer gate TG and the CCD
1 gate φ₁, CCD second gate φ _TwoAre on at the same time
And the floating gate bias voltage FGB becomes high.
A voltage state is set (FIG. 11B). Floating game
The bias voltage FGB is applied to the transfer gate TG, etc.
It takes an intermediate value between the applied positive voltage and the ground potential. That
Therefore, the transfer gate TG
The potential of the channel up to FG is shown in FIG.
As shown in FIG._TwoAnd floating
The shape has a step at the boundary with the gate FG.

Next, the floating gate bias voltage FGB, the CCD second gate φ ₂ , the CCD first gate φ ₁ , and the transfer gate TG are sequentially turned off in this order (FIGS. 11C to 11D). As a result, the electrons accumulated in the channel from the transfer gate TG to the floating gate FG are removed from the clear drain CLD.
Can be discarded.

Due to variations in the manufacturing process, the potentials of the channels from the transfer gate TG to the floating gate FG are not completely equal, and some irregularities occur. Even in such a case, by sequentially turning off the floating gate FG as described above,
The stored electrons can be almost completely discarded.

Next, the clear gate CLG is turned off (FIG. 11E). As a result, electrons do not flow from the storage region to the clear drain CLD, and the electrons generated in the light receiving region PD are accumulated in the storage region. In this way, charges corresponding to the amount of light received by each pixel are accumulated in the storage area of that pixel.

FIG. 12 is a potential diagram showing a repetitive integration start operation performed when the accumulated charge is insufficient. In the channel region below the floating gate FG, charges have already been accumulated by the integration operation up to the previous time (FIG. 12).
(A)).

Barrier gate BG and clear gate CLG
Is turned on, and all charges accumulated in the storage region are discharged to the clear drain CLD (FIG. 12B).
Next, the clear gate CLG is turned off. Thereby, the charges generated in the light receiving area PD are accumulated in the storage area. At this time, the integration operation can be newly performed without discharging the charge accumulated by the integration operation up to the previous time.

FIG. 13 is a potential diagram showing the charge transfer operation. As shown in FIG. 13A, the barrier gate BG is turned off to end the integration operation. Thereby, a potential barrier is formed between the light receiving region PD and the storage region, so that electrons generated in the light receiving region PD do not flow into the storage region. Since the light is constantly irradiated, electrons are generated, but these electrons are discharged to the overflow drain OFD through the potential barrier under the overflow gate OFG.

Next, the transfer gate TG and the CCD
1 gate φ₁, CCD second gate φ _TwoAnd floatin
The gate bias voltage FGB is turned on (FIG. 13
(B)). Therefore, the channel under these gate electrodes
Potential drops and accumulates in the storage area
Charges transferred are transfer gate TG, CCD first gate
φ₁, CCD second gate φ_TwoTransferred down.

At this time, when performing the integral integration, the electric charge accumulated by the previous integration operation remains below the floating gate FG. In this case, the charge is similarly transferred to the transfer gate TG, the CCD first gate φ ₁ , CC
D is transferred second gate phi ₂ below.

Next, the transfer gate TG and the CCD
1 gate φ₁, CCD second gate φ _TwoTo turn off sequentially
(FIGS. 13C to 13E). This allows these
The charge accumulated under the gate electrode is floating
The data is transferred under the gate FG. Thus, a new integral
In this case, the charge corresponding to the amount of received light is floated.
Is accumulated under the floating gate FG. Continue from previous integration
When the renormalization integration is performed, the
The sum of the load and the charge according to the amount of received light is floating
It is stored under the gate FG.

FIG. 14 is a potential diagram showing a scan start operation. FIG. 14 shows a state in which the charge transfer operation has been completed.
It is shown in (A). Electric charges corresponding to the amount of received light are accumulated below the floating gate FG. CCD second gate φ ₂
Is turned on (FIG. 14B). As a result, the charges accumulated under the floating gate FG are transferred to the CCD.
It is transferred to the _second lower second gate phi. Next, the gate voltage CE is set to a low voltage state, and the MOS transistor TR1 is turned off (FIG. 14C). Therefore, the floating gate FG is in a floating state.

[0118] Then, the CCD second gate phi ₂ to the OFF state (FIG. 14 (D)). As a result, the charges stored under the CCD second gate φ ₂ are transferred again under the floating gate FG. For this reason, the potential of the channel below the floating gate FG increases, and at the same time, the potential of the floating gate FG decreases. Thus, the potential of the floating gate FG changes according to the amount of light received by each pixel.

Next, a method of extracting the potential change of the floating gate FG as an output of the CCD will be described with reference to FIG. First, the preset signal P
By temporarily closing the switch SW1 by R to make the non-inverting input contact and the output contact conductive, the capacitor C1 is discharged and the output contact is set to the analog reference voltage V.
Reset to ref.

The floating gate FG is set to the analog reference voltage Vref by setting the gate voltage KCn of the pixel to be read to a high voltage state and turning on the MOS transistor TR2. At this time, a charge corresponding to a change in the voltage of the floating gate FG flows out or flows in. This charge amount is charged to the capacitor C1 via the MOS transistor TR2. Therefore, a voltage corresponding to the charge is generated at the output CCDOUT.

FIG. 15 shows the CCD 10 and the pixel selector 11. The CCD 10 includes 160 linearly arranged pixels and an image signal reading circuit 61. The gate electrode of the MOS transistor TR2 of each pixel is connected to the pixel selector 11, and the image signal of the pixel that has received the selection signal KC from the pixel selector 11 is read.

Since all the pixels have the same configuration, only the n-th pixel 60n will be described. As described with reference to FIG. 9, one end of the buried channel 51n is connected to the overflow drain OFD. Overflow gate O
FG, barrier gate BG, storage gate ST, clear gate CLG, transfer gate TG, CCD first
The gate φ ₁ and the CCD second gate φ ₂ are common to all pixels. The storage region of the buried channel 51 below the storage gate ST is connected to the clear drain CLD via the MOS transistor TR3n.

The floating gate FG is connected to the floating gate bias voltage FGB via the MOS transistor TR1n. MOS transistor T
A gate voltage CE common to all pixels is applied to the gate electrode of R1n.

As described above, since the gate voltages of all the pixels are connected in common, the above-described integration start operation,
The charge transfer operation and the scan start operation are performed simultaneously for all pixels.

The drain of the MOS transistor TR2n is connected in common to all pixels, and the operational amplifier AMP1
Connected to the inverting input contact. Further, the gate electrode is independently connected to the pixel selector 11 for each pixel. Accordingly, only the MOS transistor TR2n selected by the pixel selector 11 is turned on,
Only the image signal of the pixel is applied to the inverting input contact of the operational amplifier AMP1. The image signal applied to the inverting input contact of the operational amplifier AMP1 is output as an electric signal to the output contact CCDOUT of the operational amplifier AMP1 as described above.

Next, the pixel selectors 11a and 11b will be described with reference to FIGS. FIG.
2 shows a part of a shift register section of a pixel selector. Shift registers 70 (0) to 70 (39) are connected in series. In the figure, 70 (0) to 70 (3) are shown. The X terminal of the shift register 70 (m) is connected to one input contact of the NOR gates 71 (m) and 72 (m). The Y terminal of the shift register 70 (m) is connected to one input contact of the NOR gates 73 (m) and 74 (m).

Further, NOR gates 71 (m) and 73
The timing signal (-DC) is applied to the other input contact of (m).
0), a timing signal (-DC1) is supplied to the other input contact of the NOR gates 72 (m) and 74 (m).

Shift registers 70 (0) to 70 (39)
The clear signal CL described later with reference to FIG.
Are supplied, and all the shift registers 70 (0) to 70 (0) to 70
(39) can be initialized at the same time.

The pixels which can be the scan start or end address, that is, 1, 5,.
A preset signal (-PRi) for setting the start of scanning is provided in the shift register 70 (m) that outputs the selection signal KC (4m + 1) corresponding to the ninth, twenty-one, ..., 141, 153, and 157th pixels. Is supplied.

For example, since the address 9 is assigned to the ninth pixel, the preset terminal (-PR) of the shift register 70 (2) that outputs the selection signal KC9 is connected to the preset signal (-PR) corresponding to the address 2. PR2). Since the shift register 70 (3) does not correspond to a pixel which can be a scan start or end address, its preset terminal (-PR) is always pulled up to a high level.

By presetting the shift register 70 (m) corresponding to the scan start address, the high level is sequentially synchronized with the clock CK2 from the head select signal KC (4m + 1) of the preset shift register 70 (m). Moves.

The Q contact of the shift register 70 (m) that outputs a selection signal KC (4m + 1) corresponding to a pixel which can be a scan start or end address is connected to a scan end detection circuit 80 described later with reference to FIG. I have. Shift register 70 corresponding to the current scan address
The Q contact of (m) becomes high level, and notifies the scan end detection circuit 80 of the scan address signal Q (n) of FIG. The scan end detection circuit 80 compares the current scan address with the scan end address and detects the end of the scan.

FIG. 17 shows one shift register 70.
(M) to four selection signals KC (4m + 1) to KC (4
6 is a timing chart for explaining a mechanism for generating (m + 4). Timing signal (-DC0), (-D
C1) generates pulses whose phases are different from each other by 180 °. FIG. 17 shows a case where the shift register 70 (0) is preset.

When the shift register 70 (0) is preset, the output X0 of the X terminal goes low. Thereafter, when the timing signal (-DC0) goes low, the selection signal KC (1) goes high. At this time, since the timing signal (-DC1) is at a high level, the selection signal KC (2) is at a low level. Also, Y
Since the output Y0 of the terminal is at a high level, the selection signal KC
Both (3) and KC (4) are at low level.

At this time, after presetting, the timing signal (-DC0) is always changed to the timing signal (-DC1).
The timing is controlled so as to become low level earlier than before.

When the timing signal (-DC0) goes high, the selection signal KC (1) goes low.
Next, when the timing signal (-DC1) goes low, the selection signal KC (2) goes high.

In synchronization with the clock CK2, the output X0 of the X terminal goes high, and the output Y0 of the Y terminal goes low. At this time, the timing signal (-
DC0) and (−DC1) in synchronization with the selection signal KC.
(3), KC (4) sequentially goes high. In this way, by combining with the timing signals (-DC0) and (-DC1), 4 shifts from one shift register.
One select signal can be generated.

In this embodiment, the shift register 70
Are formed on the same substrate in parallel with the CCDs 10a and 10b. Since the pitch of the CCD is usually about 24 μm, if one shift register corresponds to one selection signal, it is necessary to manufacture one shift register within a 24 μm width. But this is difficult.

If four select signals are generated from one shift register as in this embodiment, 96 μm
It is only necessary to manufacture one shift register within the width. Therefore, pattern design becomes easy.

FIG. 18 shows a part of the address decoding section of the pixel selector 11. Operand portions OR3 to OR0 of an input command are supplied to a NAND gate group 81 including eight NAND gates. The NAND gate group 81 includes four upper bit decoding signal lines 82a.
Then, a decoding signal is supplied to the four lower bit decoding signal lines 82b.

The upper bit decoding signal line 82a
An address signal (AD (i)) can be generated by selecting an arbitrary one from the decoding signal lines 82b for the lower bits and inputting the selected one to the NOR gate 79. For example, the signal input to the NOR gate 79 (2) is “0” when the operand portion is “0010”.
(Low level) ", and the address signal AD (2) becomes" 1 (high level) ".

Sixteen NOR gates 79 are provided, and by designating a desired address in the operand portion, the corresponding address signal AD (i) can be set to a high level.

FIG. 19 shows a scan start address setting circuit 83 and a scan end detection circuit 8 of the pixel selector 11.
Indicates a part of 0. Address signals AD (0) to AD (15) generated by the address decoding unit shown in FIG.
Are the latch circuits 77 (0) to 77 (1) of the scan start address setting circuit 83 and the scan end detection circuit 80, respectively.
5), 78 (0) to 78 (15).

The start address setting signal SAS is supplied to the CP contact of the latch circuit 77, and the pulse of the start address setting signal SAS is applied to the latch circuit 77 (i) corresponding to the designated address. The address signal is latched. An end address setting signal EAS is supplied to a CP terminal of the latch circuit 78. When a pulse of the end address setting signal EAS is applied, the address signal is latched in the latch circuit 78 corresponding to the designated address. Is done.

The output signal of latch circuit 77 (n) is
It is supplied to one input contact of the ND gate 75 (n). The scan input signal SCST is supplied to the other input contact of the NAND gate 75 (n). By applying the pulse of the scan start signal SCST, the preset signal PR (n) corresponding to the set address is output. Thus, the scan is started from the corresponding pixel as described above.

The output signal of latch circuit 78 (n) is
It is supplied to one input contact of the ND gate 76 (n). The other input contact of the NAND gate 76 (n) is supplied with the scan address signal Q (n). The scan address signal Q (n) goes high when scanning is performed up to the address corresponding to Q (n).

Therefore, when the scan is executed up to the scan end address, the corresponding NAND gate 76 (n)
Both input contacts become high level and the output terminal becomes low level. The output contacts of the NAND gates 76 (0) to 76 (15) are wired-OR connected and connected to the inverting set contact (-S) of the flip-flop 84. Therefore, when the output contact of one NAND gate 76 goes low, the inverted set contact (-S) of the flip-flop 84 goes low and the flip-flop 84 is set.

As described above, when scanning is performed up to the scan end address, the flip-flop 84 is set, and the clear signal (-CL) is output. The inverted signal of the clear signal (-CL) is supplied to all shift registers 70, and all shift registers 70 are initialized.

FIG. 20 shows an AGC circuit. The illustrated circuit includes an AGC monitor for left 8a, an AGC monitor for right 8b, and an AGC circuit 9. The left AGC monitor 8a and the right AGC monitor 8b output a voltage according to the amount of received light. The AGC circuit 9 compares the voltage output from the AGC monitor with the determination voltage, and inverts the output when the voltage matches.

Since the configurations of the left and right AGC monitors are the same, only the left AGC monitor 8a will be described.
The anode of the photodiode LPD is grounded, and the cathode is connected to the inverting input contact of the operational amplifier LAMP. The non-inverting input contact of the operational amplifier LAMP is connected to a constant voltage of 2.5V.

The capacitor LC1 is connected between the inverting input contact and the output contact of the operational amplifier LAMP. The capacitor LC1 includes a series circuit of a capacitor LC2 and a switch LSW2, and a capacitor LC3 and a switch LSW.
SW3 series circuit, capacitor LC4 and switch LSW
4 and the switch LSW0 are connected in parallel.

Switches LSW2, LSW3, LSW4
Are the AGs supplied from the other blocks of the distance measuring device, respectively.
C gain setting signals AGCGN1, AGCGN2, AGC
It is opened and closed by GN3. The output contact of the operational amplifier LAMP is connected to A through a switch LSW5.
It is connected to the inverting input contact of the comparator CCMP of the GC circuit 9.

The switch LSW0 is opened and closed by a signal voltage φ _CLG applied to the clear gate CLG of the CCD 10. When the clear gate CLG is on, the switch LSW0 is closed. At this time, the operational amplifier L
The output signal LAGCOS of the AMP becomes 2.5V.

The switch LSW0 is opened in synchronization with the turning off of the clear gate CLG. That is, C
The switch LSW0 is opened simultaneously with the start of the integration operation of the CD10. Thereby, the capacitor LC1 is charged by the photocurrent generated by the photodiode LPD. Since the cathode of the photodiode LPD is connected to the inverting input contact of the operational amplifier LAMP, the potential is kept at 2.5V. Therefore, the output signal LAGCOS of the operational amplifier LAMP increases by a voltage corresponding to the amount of charge charged in the capacitor LC1.

At this time, the switches LSW2, LSW3,
When the LSW 4 is closed, the combined capacitance of the capacitor charged by the photocurrent changes. Thereby, the sensitivity for converting the amount of received light into voltage can be changed.

For example, capacitors LC2, LC3, LC
4 is 1 times the capacity of the capacitor LC1, 2
In the case where the value is set to twice or four times, the combined capacitance can be doubled by closing the switch LSW2 as compared with the case where only the capacitor LC1 is used. Similarly, switch LSW
2 and LSW3 are closed four times, switch LSW2,
If all the LSW3 and LSW4 are closed, the number can be increased by eight times. Thus, the light receiving sensitivity can be changed to 1/2, 1/4, or 1/8 times.

The LSW 5 is controlled by a switch open / close signal LSEL supplied from another block in the distance measuring device. By closing LSW5, the left operational amplifier L
The output signal LAGCOS of the AMP can be supplied to the AGC circuit 9. Similarly, by closing the switch RSW5, the output signal RAG of the right operational amplifier RAMP is
COS can be supplied to the AGC circuit 9.

The AGC circuit 9 includes a comparator CCMP,
It is composed of switches SW2 and SW3. The left AGC monitor 8 is connected to the inverting input contact of the comparator CCMP.
a or the output signal of the right AGC monitor 8b is selectively supplied. Further, to the non-inverting input contact, one of 2.75 V and 3.0 V is selectively applied as a judgment voltage.

The selection of the judgment voltage is performed by the AGC level setting signal AGCLV supplied from another block in the distance measuring apparatus.
1, a switch SW2 controlled by AGCLV2,
This is performed by opening and closing SW3. The judgment voltage is 2.75 V by closing the switch SW2,
The voltage becomes 3.0 V by closing the switch SW3.

Since the initial value of the output signals of the AGC monitors 8a and 8b is 2.5V, the change in the voltage until reaching the determination voltage is 0.25V or 0.5V. Therefore, the determination level can be switched between two levels of 0.25V and 0.5V.

The output signal of the left AGC monitor 8a is AGC
When the switch 9 is supplied to the circuit 9, when the switch LSW0 is opened, the potential of the inverting input contact of the comparator CCMP rises from 2.5 V according to the amount of received light as described above.
Initially, since the voltage is lower than the judgment voltage, the comparator CCM
The P output signal AGCCMP is at a high level.

When the output signal of the AGC monitor 8a reaches the determination voltage 2.75V or 3.0V, the output signal AGCCMP of the comparator CCMP is inverted and goes to a low level. Thus, the left or right AGC monitor 8
An output signal AGCCMP can be generated by detecting that the amount of light applied to a or 8b has reached a certain amount.

By changing the combined capacitance of the capacitors in the AGC monitors 8a and 8b in four steps and changing the determination voltage of the AGC circuit 9 in two steps, the detection sensitivity of the amount of received light can be changed in eight steps. . However, in practice,
Since the combined capacitance of the capacitor changes by a factor of 2, 4, and 8 and the determination level changes by a factor of 2, the combination of these changes the total in five stages.

The operational amplifiers LAMP, RAMP, and the comparator CCMP use an n-channel MOS transistor as a current source, and a current control signal CCN is supplied to a gate electrode of each n-channel MOS transistor. When the distance measuring apparatus enters the sleep mode, the current control signal CCN becomes 0 V, and almost no current flows. In this way, by setting to sleep mode,
Current consumption can be suppressed.

FIG. 21 is a circuit diagram of the CCD signal processing circuit 12. CC is connected to the inverting input contact of the operational amplifier AMP2.
The output signal voltage V _{CDSIN of} D10 is provided. The non-inverting input and output contacts are shorted. Further, the output contact is connected to the inverting input contact of the operational amplifier AMP3 via the capacitor C2. In the capacitor C2,
A series circuit of the capacitor C3 and the switch SW4 and a series circuit of the capacitor C4 and the switch SW5 are connected in parallel to form an input-side capacitance.

A constant voltage of 3 V is applied to the non-inverting input contact of the operational amplifier AMP3. Operational amplifier AM
The inverting input contact of P3 is connected to the capacitor C5 and the switch SW.
7 is connected to an output contact via a parallel circuit. A series circuit of a capacitor C6 and a switch SW6 is connected in parallel to the capacitor C5 to form an output-side capacitance.

The switches SW4, SW5 and SW6 are controlled to open and close by CDS gain control signals CDSG1, CDSG2 and CDSG0 generated in other blocks in the distance measuring device, respectively. The switch SW7 is a CDS clamp signal CDS_CL generated in another block in the range finder.
Opening / closing is controlled by the MP.

The capacitance of the capacitors C3, C5 and C6 is equal to the capacitance of the capacitor C2,
4 is set to twice the capacitance of the capacitor C2. Therefore, by closing the switch SW4, the input-side capacitance is doubled, and the switches SW4, S4
By closing W5, the input-side capacitance can be quadrupled. Similarly, by closing the switch SW6, the output-side capacitance can be doubled.

Assuming that the operational amplifier is ideal, the inverting input contact of the operational amplifier AMP3 is fixed at 3V. Further, the voltage of the electrode of the capacitor C2 connected to the operational amplifier AMP2 becomes equal to the output signal voltage V _CDSIN of the _{CCD 10} .

When the switch SW7 is closed, the output signal voltage V _CDS of the operational amplifier AMP3 is fixed at 3V. After the switch SW7 is opened, when the signal voltage V _CDSIN is applied to the inverting input contact of the operational amplifier AMP2, the charge stored in the input-side capacitance changes according to the change in the voltage. Charges are accumulated in the output-side capacitance in accordance with this change.

As the output-side capacitance is charged,
The voltage between the electrodes changes according to the charge, and the output signal voltage V _CDS of the operational amplifier AMP3 changes. The output signal voltage V is determined by the ratio between the input-side capacitance and the output-side capacitance.
The amount of change in _CDS is different. Switches SW4, SW5, SW
6 to change the input-side capacitance and the output-side capacitance to change the amount of change in the output signal voltage V _CDS to 、 １, 1, 2, and 4 times the amount of change in the signal voltage V _CDSIN. can do.

The output signal voltage V _CDS is supplied to the contrast calculation circuit 13 and the A / D conversion circuit 14. As described above, the output signal of the CCD 10 can be supplied to the contrast calculation circuit 13 and the A / D conversion circuit 14 with a constant gain.

Next, the contrast calculation circuit 13 will be described with reference to FIGS. FIG. 22 shows a CCD that converts a potential difference into electric charges, and transfers and accumulates the converted electric charges.
Indicates a part. 22A is a plan view, FIG. 22B is a cross-sectional view, FIG. 22C is a potential diagram of a channel region, and FIG. 22D is a timing chart of each gate of the CCD.

On the surface of p-type substrate 90, n ⁺ regions 91 and 92 are formed at predetermined intervals. n ⁺ region 9
1, the input gate IG1, the dummy gate DG, the input gate IG2, the transfer gate TRG, the storage gate STG, and the output gate OG having an insulated gate structure are so overlapped with each other that they are insulated and slightly overlap each other. They are formed in order.

The voltage ID is applied to the n ⁺ region 91. Also, a predetermined DC voltage is applied to the input gate IG1 and the output gate OG. The dummy gate DG is
Connected to DC power supply VCC. The voltage ID is normally at a high level, and periodically generates a low-level pulse.

During a period P in which the signal voltage Vin is being applied to the input gate IG2, a low-level pulse is applied to the voltage ID. As a result, the electrons in n ⁺ region 91 cross over the potential barrier under input gate IG1 and enter input gate IG2.
Injected below. At this time, the transfer gate TRG
Is low level, the electrons are transferred to the transfer gate T
It is not injected below RG.

When the voltage ID returns to the high level, some of the injected electrons are returned to the n ⁺ region 91 over the potential barrier under the input gate IG1. At this time, the amount of charge accumulated under the input gate IG2 is equal to the input gate I
This corresponds to the potential difference between G1 and the input gate IG2.

Next, by applying a positive pulse to the transfer gate TRG, the electrons accumulated under the input gate IG2 are transferred under the storage gate STG. By applying a negative pulse to the storage gate STG, electrons accumulated under the storage gate STG can pass through a potential barrier under the output gate OG and be n ⁺
Transfer to area 92.

By changing the signal voltage Vin applied to the input gate IG2 and repeating this process,
The amount of charge corresponding to the signal voltage Vin can be sequentially transferred to the n ⁺ region 92, accumulated and integrated.

The dummy gate DG is formed between the input gates IG1 and IG2 for manufacturing reasons. In this method, the difference between the voltages applied to the input gates IG1 and IG2 is taken out as the amount of charge, so that the input gates IG1 and IG2 need to have the same inter-substrate capacitance per unit area.

For this purpose, both are preferably formed as a first polysilicon gate or a second polysilicon gate. In this embodiment, the input gates IG1 and IG2 are both formed of the first polysilicon gate, and IG1 and I
A dummy gate DG made of the second polysilicon is provided so that no gap is formed between G2. At this time, IG1 and I
A power supply voltage is applied to DG so that the dummy gate DG between G2 does not become a potential barrier.

FIG. 23 shows the contrast calculation circuit 13 including the CCD section described with reference to FIG. An n ⁺ region 92 is formed in the center of p-type substrate 90. The CCD shown in FIG. 22 is provided symmetrically on both sides of the n ⁺ region 92. For the CCD on the left side of the n ⁺ region 92, the gate electrode IG1b corresponding to the input gate IG1 is supplied with the analog reference voltage Vref, and the gate electrode IG2b corresponding to the input gate IG2 is supplied with the signal voltage Vin. I have.

Conversely, for the CCD on the right side of n ⁺ region 92, gate electrode IG1a corresponding to input gate IG1
Is supplied with the signal voltage Vin, and the input gate IG
The analog reference voltage Vref is applied to the gate electrode IG2a corresponding to No. 2.

The output signal voltage V CDS of the CCD signal processing circuit 12 is input to the difference voltage generation circuit 93. The output signal voltage V CDS is a signal voltage corresponding to the amount of light received by the pixels, and the output signal voltages of the pixels in the scan range are sequentially supplied. The difference voltage generation circuit 93 generates a signal voltage Vin obtained by calculating a difference between output signal voltages of adjacent pixels based on the output signal voltage V CDS.

Operational Amplifier AMP of Difference Voltage Generating Circuit 93
The output signal voltage V.sub.CDS of the CCD signal processing circuit 12 is input to the inversion input contact 4 via the capacitor C7 as described above. The inverting input contact is connected to the output contact via a parallel circuit of a switch SW8 and a capacitor C8. The output contact forms and outputs a signal voltage Vin. Further, an analog reference voltage Vref is applied to a non-inverting input contact of the operational amplifier AMP4.

The operation of difference voltage generating circuit 93 will be described below with reference to FIG. FIG. 24 is a timing chart of the contrast calculation circuit 13. Scanning is started by a negative pulse of the scan start signal (-SCST). When scanning is started, a voltage corresponding to the amount of received light of each pixel is sequentially generated in the output signal voltage V CDS substantially in synchronization with the clock.

The clamp signal CONCLMP goes low in synchronization with the negative pulse of the scan start signal (-SCST), and the switch SW8 is opened. When the output voltage V1 of the first pixel is generated in the output signal voltage VCCS, a charge corresponding to the voltage V1 is accumulated in the capacitor C7.
At the same time, a charge equal to this charge amount is also stored in the capacitor C8. Here, assuming that the capacitances of the capacitors C7 and C8 are equal, a potential difference V1 occurs between the electrodes of the capacitor C8 due to the accumulated charge, and a voltage V1 is generated in the output signal Vin.

Here, the analog voltages V1 and Vin represent differences from the analog reference voltage Vref. Hereinafter, similarly, the analog voltage indicates a difference from the analog reference voltage Vref.

Next, the control signal CONCLMP
Temporarily goes high, and the switch SW8 is temporarily closed. As a result, the signal voltage Vin is set to the potential of the inverting input contact of the operational amplifier AMP4, that is, the analog reference voltage Vref. At this time, the capacitor C7
, The output signal voltage V1 is still applied, and the voltage V
An electric charge corresponding to 1 is stored.

Thereafter, the output signal voltage VCDS returns to the analog reference voltage Vref. At this time, the charge stored in the capacitor C7 is discharged, and the capacitor C8 is charged with the same amount of charge. As a result, the signal voltage Vin has the voltage −
V1 appears.

Next, the output voltage V2 of the second pixel is applied to the output signal voltage VCCS. At this time, the capacitor C
Since the terminal voltage of the capacitor 7 becomes V2, the amount of charge corresponding to the voltage V2 among the charges charged in the capacitor C8 moves to the capacitor C7. Therefore, the capacitor C8
Is V2-V1 and the signal voltage Vin is
The voltage V2-V1 appears.

Next, when the clamp signal CONCLMP temporarily goes high, the switch SW8
Is temporarily closed, and the signal voltage Vin is set to the analog reference voltage Vref. At this time, the output signal voltage V2 is still applied to the capacitor C7, and charges corresponding to the voltage V2 are accumulated.

This state corresponds to the voltage V1 corresponding to the head pixel.
Is applied, the clamp signal CONCLM
This is the same state as the state after P temporarily goes high. Therefore, by repeating this operation, the signal voltage Vin has a difference between the output voltages corresponding to the adjacent pixels in the order of V3-V2, V4-V3,.

With the negative pulse of the scan end signal (-SCEND), the clamp signal CONCLMP is fixed at a high level, and the signal voltage Vin becomes the analog reference voltage V.
Holds ref. As described above, the difference-(Vi + 1-Vi) between the output voltages corresponding to the adjacent pixels appears in the signal voltage Vin. At this time, if Vi + 1> Vi, the output signal Vin becomes lower than the analog reference voltage Vref, and if Vi + 1 <Vi, the output signal Vin becomes higher than the analog reference voltage Vref.

When the output signal Vin is equal to or lower than the analog reference voltage Vref, that is, when Vi + 1> Vi, the potential below the input gate IG2a is higher than the potential below the input gate IG1a. Therefore, the n ⁺ region 91a
Are injected below the input gate IG2a. Thereafter, n ⁺ region 9 according to the procedure described in FIG. 22
2

At this time, the potential under input gate IG2b is higher than the potential under input gate IG1b.
No. Therefore, when the voltage ID becomes low level,
n ⁺ regions 91b electrons injected from the voltage ID is returned to the n ⁺ region 91b when returning to the high level. Therefore, when Vi + 1> Vi, the electrons injected from n ⁺ region 91b are not transferred.

Conversely, when the output signal Vin is the analog reference voltage V
ref or more, that is, when Vi + 1 <Vi, the same applies.
From our considerations, n⁺Only electrons injected from region 91b
Is n ⁺Transferred to area 92 and n⁺Injected from region 91a
The transferred electrons are not transferred. In this way, the adjacent image
The absolute value of the difference between the elementary output voltages | Vi + 1−Vi |
Charge amount is n⁺Can be transferred to area 92 and stored
You.

Next, the contrast signal reading circuit 94
Will be described. The n ⁺ region 92 is connected to the inverting input contact of the operational amplifier AMP5. The inverting input contact of the operational amplifier AMP5 is connected to the output contact via a parallel circuit of the switch SW9 and the capacitor C9. The output contact of the operational amplifier AMP5 is a capacitor C11
Is connected to the inverting input contact of the operational amplifier AMP6.

An inverting input contact and an output contact of the operational amplifier AMP6 are connected by a parallel circuit of a switch SW10 and a capacitor C10. Operational amplifier AMP5, A
The non-inverting input contact of MP6 has an analog reference voltage V
ref is given. An output contact of the operational amplifier AMP6 forms and outputs a contrast signal Vcon.

Before the start of the contrast calculation, the switch opening / closing signals CONRS1 and CONRS2 are at the high level, and the switches SW9 and SW10 are closed.
Therefore, no charge is stored in the capacitors C9, C10, C11, and the analog reference voltage Vref appears at the output contacts of the operational amplifiers AMP5, AMP6. At the start of the contrast calculation, the switch open / close signal CONRS1,
CONRS2 goes low, and switches SW9, S9
W10 is released.

Since the potential of n ⁺ region 92 is held at analog reference voltage Vref, all charges transferred to n ⁺ region 92 are charged to capacitor C9. here,
Assuming that the capacitance between the input gate IG2 and the substrate 90 is Cst, the charge amount Qsig transferred per cycle is Qsig = C
It is represented by st · Vin. This charge amount Qsig is stored in the capacitor C9 in synchronization with the low-level pulse of the storage gate STG.

At the output contact of the operational amplifier AMP5, a voltage corresponding to the amount of charge charged in the capacitor C9 appears. For example, if the selection is made such that Cst = C9 / 2, a voltage Vin / 2 appears at the output contact of the operational amplifier AMP5.

The amount of charge corresponding to this voltage is
11 is charged. At the same time, the same amount of charge
It is also charged to zero. As a result, a voltage proportional to the voltage Vin appears at the output contact of the operational amplifier AMP6. Thus, the contrast signal Vcon is output.

By repeating the transfer and accumulation of the charge corresponding to the output signal Vin, a voltage proportional to the output signal Vin of the corresponding cycle is superimposed on the contrast signal Vcon.
Thus, at the end of the last charge transfer,
A voltage corresponding to the sum of the absolute values of the differences between the output signals of the adjacent pixels appears in the contrast signal Vcon.

In the above-described contrast calculation circuit 13, a method has been described in which the weighed electric charge is integrated by an integrating amplifier and converted into a voltage. However, it is also possible to configure a floating diffusion amplifier.

FIG. 25A shows a cross section of the charge weighing section of the contrast calculation circuit 13 constituted by a floating diffusion amplifier and a contrast signal readout circuit 94.
a. n ⁺ regions 91, 92 and input gate IG1,
Dummy gate DG, input gate IG2, transfer gate TRG, storage gate STG, output gate OG
Has a contrast calculation circuit 13 shown in FIG.
Is similar to

At a predetermined distance from n ⁺ region 92, n
⁺ Region 95 is formed. Voltage RD is applied to n ⁺ region 95. A reset gate RG having an insulated gate structure is formed between n ⁺ regions 92 and 95. The n ⁺ region 92 is connected to an input contact of a source follower amplifier (SF amplifier).

FIG. 25B shows the potential under each gate electrode. FIG. 25C shows a timing chart.
Before calculating the sum of the absolute values of the differences between the output signals of the respective pixels, a positive pulse is applied to the reset gate RG and the n ⁺ region 92
Is initially set to the potential of the n ⁺ region 95. Since a constant voltage RD is always applied to the n ⁺ region 95, n
⁺ Region 92 is set to voltage RD.

The operation of weighing the charge amount corresponding to the difference between the output signals of the adjacent pixels and transferring it to the n ⁺ region 92 is the same as that described with reference to FIG. When the n ⁺ region 92 to the signal charge is transferred, the potential of the n ⁺ region 92 is reduced to the initial setting level. The transfer of the signal charge is repeated, and a voltage corresponding to the integrated charge amount is generated in n ⁺ region 92. This voltage is output via the SF amplifier. The difference between the voltage level at the time of the initial setting and the voltage level after the integration is completed corresponds to the integration output.

Next, the configuration and operation of the signal level determination circuit 15 will be described with reference to FIGS. 26 and 27. The signal level determination circuit 15 checks the upper 3 bits of each A / D-converted pixel output to determine the level as L1.
The determination can be made in eight ways at seven slice levels of L7. Further, the level of the maximum output pixel in the scanned range can be known.

FIG. 26 is a circuit diagram of the signal level determination circuit 15. The output signal of each pixel is A / D converted by the A / D conversion circuit 14, and the output signal data (-D0) to (-D0)
D7) is supplied to the decode circuit 101. The result of decoding the upper three bits of the output signal data is output to the output ports 103a to 103g of the decoding circuit 101.

For example, when the upper three bits are "110", only the output port 103a is "0", and the other output ports are "1". When the upper three bits are "000", only the output port 103g becomes "0" and the output ports 103a to 103f become "1".

That is, as the output level of each pixel changes from a low level to a high level, the output port whose output becomes "0" moves from 103a to 103g. Output port 1
03h is “0” when the output signal data is “00000000”, and is “1” otherwise. That is, when the output signal of the pixel is saturated, the output port 103h
Becomes “0”.

Each output port 103 of the decode circuit 101
a to 103 h are connected to one input contact of each of the NOR gates 102 a to 102 h of the NOR gate group 102. Further, a level determination signal LEV is supplied to the other input contact of each of the NOR gates 102a to 102h.

Outputs of the NOR gates 102a to 102g are respectively supplied to the flip-flops 10 via OR gates.
0a to 100g are input to the R input contact. Each OR
The output of the (−Q) output contact of the upper flip-flop is given to the other input contact of the gate.
The output of the NOR gate 102h is the flip-flop 10
0h is input to the R input contact.

The scan start signal SCT is supplied to the S input contact of each flip-flop. The Q output contacts of the flip-flops 100a to 100h form and output flag data (-F0) to (-F7), respectively.

At the start of scanning, the level determination signal LE
V is "1", and when a positive pulse is applied to the scan start signal SCT, each flip-flop 100a
S input contact of "~ 100h" is "1", R input contact is "0"
become. Therefore, each of the flag data (-F0) to (-F
7) are all "1". When the scan is started, the scan start signal SCT becomes low level, and the S input contacts of the flip-flops 100a to 100h become "0".

While the significance information is being output to each output port of the decode circuit 101, the level determination signal LEV
Becomes "0", and the flip-flops 100a to 100a
A negative logic of the state of the output ports 103a to 103h of the decode circuit 101 is given to the R input contact of h.

When the output signal data of the first pixel is input to the decoding circuit, the decoding result is output to each flip-flop 1.
00a to 100h. Only the R input contact of the flip-flop corresponding to the output port whose state is "0" becomes "1", and the corresponding flag data becomes "0". Further, the state of the (−Q) output contact becomes “1”, and the state of the R input contact of the flip-flop lower than the flip-flop becomes “1”. In this way, all the flag data lower than the corresponding flip-flop becomes “0”.

Thereafter, the output signal data of each pixel is sequentially input, and the state of the R input contact of the flip-flop corresponding to the output signal data of the pixel becomes "1". If the corresponding flag data is already "0", no change occurs. When the corresponding flag data is “1”, the flag data changes to “0”. At the same time, all flag data lower than the corresponding flag data become “0”.

By repeating this, at the end of the scan, the flag data corresponding to the maximum output pixel in the scan range is held. FIG. 27 shows the relationship between the output level of the maximum output pixel and the flag data. As shown in FIG. 27, the level of the maximum output pixel with respect to the level of the saturation output can be identified in eight stages. Further, by the flag data F7,
It can be determined whether there is a saturated pixel in the scan range.

FIG. 28 shows the temperature detection circuit 20. This temperature detecting circuit detects a temperature by utilizing a difference between respective temperature coefficients of an ion implantation resistor and a polysilicon resistor formed in a semiconductor process. Generally, the temperature coefficient of the ion implantation resistance is 4000 ppm / ° C., and the temperature coefficient of the polysilicon resistance is 400 ppm / ° C., which is about a ten-fold difference. The configuration and operation will be described below.

The source electrode of pMOS transistor TR4 is connected to DC power supply Vcc, and the drain electrode is grounded via a series circuit (bias array) in which resistors R1 to R6 made of polysilicon are connected in this order. I have.
The pMOS transistor TR5 has a source electrode connected to the DC power supply Vcc, and a drain electrode connected in series with resistors R7 to R10 made of polysilicon and resistors R11 and R12 formed by ion implantation in this order. (Temperature detection array).

The inverting input contact of the operational amplifier AMP7 has
An analog reference voltage Vref is provided. The non-inverting input contact is at the drain electrode of the pMOS transistor TR4, and the output contact is at the pMOS transistors TR4 and TR5.
Is connected to the gate electrode of

The drain electrode of the pMOS transistor TR4 is connected to the input contact VZERO of the A / D converter 110, the connection point between the resistors R2 and R3 is connected to the input contact VFULL, and the connection point between the resistors R7 and R8 is connected to the input contact VIN. ing.

By applying feedback with the operational amplifier AMP7, the pMOS is set so that the input contact VZERO of the A / D converter 110 becomes the analog reference voltage Vref.
The current of the transistor TR4 is controlled. Here, assuming that the resistance values of the polysilicon resistors R1 to R10 are r, the current value I flowing through the bias array is I = Vref / (6 ·
r).

Therefore, the voltage at the input contact V FULL of the A / D converter 110 is V FULL = (4/6) · V ref. On the other hand, since the same current also flows through the temperature detection array, if the resistance values of the ion implantation resistors R11 and R12 are r ', the voltage at the input contact VIN of the A / D converter 110 is as follows.

VIN = I. (3r + 2r ') = (1/2) .Vref + (1/3). (R' / r) .V
Therefore, when encoding is performed with 8 bits, the output CD of the A / D converter 110 is as follows: CD = (VIN−VZERO) / (VFULL−VZERO) · 256 = (1.5−r ′ / r) · 256 .

As is apparent from this equation, the output CD of the A / D converter 110 does not depend on the analog reference voltage Vref. That is, even if the analog reference voltage Vref changes, the output CD of the A / D converter 110 does not change.
If the temperature changes in this state, the value of r '/ r changes, so that the output CD of the A / D converter 110 changes.

In the circuit shown in FIG. 28, from the above equation, if r = r 'at room temperature, the A / D converter 110
Is 1/2 of the full scale range. However, when this circuit is actually mounted on an IC chip, the output CD at room temperature fluctuates due to manufacturing variations of the respective resistors. In the example shown in FIG. 28, in order to suppress the output fluctuation at room temperature, only two of the resistors of the temperature detection array are ion implantation resistors.

That is, when all of the resistors R8 to R12 are formed by ion implantation, the voltage detection sensitivity with respect to temperature increases, but the output voltage range is out of the range of the A / D converter 110 due to manufacturing variations. Could be. To avoid this, the detection sensitivity is adjusted using a polysilicon resistor.

In consideration of manufacturing variations, A / D
The output CD of converter 110 cannot be directly converted to temperature. Therefore, the output at room temperature is calculated as
It is preferable to store the data in an OM or the like and perform a process of calculating a change in temperature from a change in output.

Here, if the temperature coefficient of the polysilicon resistance is ignored and the temperature coefficient of the ion implantation resistance is α and the output at room temperature is CD0, the relationship between the output change ΔCD and the temperature change ΔT is ΔT = ΔCD / (CD0−1.5 × 256) / α. For example, since α ≒ 4000 ppm / ° C.,
Assuming that CD0 = 128, the least significant bit of the output CD corresponds to about 1 ° C.

In this embodiment, the above-mentioned temperature detecting circuit is used for detecting the substrate temperature of the distance measuring device. However, the applicable range of the temperature detecting circuit is not limited to this. Generally, it can be used for temperature detection of a semiconductor substrate on which an electronic circuit is formed. For example, the dark current can be compensated by detecting the substrate temperature of the CCD imaging device.

FIG. 29 shows a bias circuit. The bias circuit includes a current control gate voltage CCN of the current source nMOS transistor, a current control gate voltage CCP of the current source pMOS transistor, and a reference voltage V used in the CCD.
The OC is supplied to each block in the distance measuring device. Hereinafter, the configuration and operation of the bias circuit will be described.

Depletion type nMOS transistor TR6 and enhancement type nMOS transistor TR
7, the drain electrode of the transistor TR6 is connected to the power supply voltage VCC, and the source electrode of the transistor TR7 is connected to the ground potential GND.

The gate electrode of the transistor TR6 is connected to the source electrode and functions as a current source. The gate electrode of the transistor TR7 is connected to the moving contact of the switch SW11. The switch SW11 outputs the sleep signal S
It operates by LP, and in the sleep mode, the gate electrode of the transistor TR7 is set to the ground potential GND. Thereby, in the sleep mode, the transistor TR6
And no current flows in the series circuit of TR7.

In the normal mode, the transistor TR7
Is connected to the drain electrode, and a voltage corresponding to a constant current passed by the transistor TR6 is generated at the gate electrode of the transistor TR7. In the case of this embodiment, the gate electrode of the transistor TR7 is configured to be 2.0V.

An analog reference voltage Vref is applied to the inverting input contact of the operational amplifier AMP8. The analog reference voltage Vref may be supplied from the outside or may be generated by a constant voltage generating circuit inside the distance measuring device.

In the sleep mode, the operational amplifier AMP8
The switch S is connected to the gate electrode of the current source transistor
Since the ground potential GND is supplied via W12,
No current flows. Further, in the normal mode, 2.0 V is supplied in the same manner, and the operation mode is set.

The pMOS transistor TR8 and the resistor R1
3 to R18 are connected in series in this order, the source electrode of the transistor TR8 is connected to the power supply voltage VCC,
The resistor R18 is connected to the ground potential. The drain electrode of the transistor TR8 is connected to the non-inverting input contact of the operational amplifier AMP8. Also, the transistor TR
In the normal mode, the gate electrode 8 is connected to the switch SW1.
3 is connected to the output contact of the operational amplifier AMP8.

By applying feedback by the operational amplifier AMP8, the drain current of the transistor TR8 is controlled so that the drain electrode of the transistor TR8 becomes the analog reference voltage Vref. In the case of this embodiment, the resistance values of the resistors R13 to R16 are set to 1.25 kΩ, the resistance R17 is set to 7.5 kΩ, and the resistance R18 is set to 2.5 kΩ. , A current of 200 μA flows.

A pMOS transistor TR9 and a resistor R1
9 to R24 are connected in series in this order, the source electrode of the transistor TR9 is connected to the power supply voltage VCC,
The resistor R24 is connected to the ground potential. Since the gate electrode of the transistor TR9 is connected to the gate electrode of the transistor TR8, a drain current of 200 μA equal to that of the transistor TR8 flows.

The resistance values of the resistors R19 to R24 are set to be equal to R13 to R18, respectively. Therefore, the connection points on the high voltage side of R19, R20, R21, R23, and R24 are 3.0V, 2.75V,
2.5V, 2.0V and 0.5V. Each constant voltage is supplied to each block in the distance measuring device.

The pMOS transistor TR10 and nMOS
The transistor TR11 is connected in series. The source electrode of the transistor TR10 is connected to the power supply voltage VCC, and the source electrode of the transistor TR11 is connected to the ground potential GND. Since the gate electrode of the transistor TR10 is connected to the gate electrode of the transistor TR8, the same amount of drain current 200 as that of the transistor TR8 is used.
μA flows. The gate electrode of the transistor TR11 is connected to the drain electrode, and the drain current is 200 μA.
Generates a gate voltage corresponding to.

In the normal mode, this gate voltage is supplied to each block in the distance measuring device as a gate voltage CCN for controlling the current of the nMOS transistor via the switch SW14. In the normal mode, the output contact voltage of the operational amplifier AMP8 becomes pM via the switch SW13.
The OS transistor current control gate voltage CCP is supplied to each block in the range finder.

In the sleep mode, the gate voltage CCP for controlling the pMOS transistor current is controlled by the switch SW13.
And the gate voltage CCN for controlling the current of the nMOS transistor is connected to the switch SW1.
4 to the ground potential GND. Therefore,
No current flows through the MOS transistors in each block, and current consumption can be reduced.

A constant voltage of 2.5 V is applied to the non-inverting input contact of the operational amplifier AMP9, and the inverting input contact and the output contact are short-circuited. As a result, the operational amplifier AMP9 forms and outputs a constant voltage of 2.5 V and supplies it to the CCD circuit as the reference voltage VOC. The gate electrode of the nMOS transistor serving as a current source in the operational amplifier AMP9 has nM
The gate voltage CCN for controlling the OS transistor current is supplied, and almost no current is consumed in the sleep mode.

As described above, by connecting the current control gate electrodes CCN and CCP supplied to the gate electrodes of the current source transistors of each block in the distance measuring apparatus to the ground potential GND and the power supply voltage VCC in the sleep mode, respectively. In addition, current consumption can be suppressed.

Next, with reference to FIGS. 30 to 32, an example of an operation flow in a case where the distance measuring device is incorporated in a camera body to measure a distance will be described. FIG. 30 is an operation flowchart of the distance measuring device and the camera body, FIG.
FIGS. 32B, 32A, and 32B show timing charts of an integration operation, a prescan operation, a repetitive integration operation, and a main scan operation, respectively.

First, the integration operation will be described with reference to FIG. 30 and FIG. In step b1, the power is turned on while applying a low level to the reset terminal (-RESET) of the distance measuring apparatus. While the reset terminal (-RESET) is at the low level, the distance measuring device is kept in the reset state.

At step b2, the reset terminal (-RES
ET) to high level. As a result, the accumulated charges under the storage gate ST and the floating gate FG shown in FIG. 9 are cleared. At the same time, the charge generated according to the amount of received light starts to accumulate below the storage gate ST, and integration starts.

At step b3, the process stands by until the integration is completed. When the integration is completed, the ranging device notifies the camera body of an integration end (EOI) signal at the fall of the service request terminal SRQ. That is, after the reset, the service request terminal SRQ is used for notification of the EOI signal. When the camera body detects the EOI signal, it proceeds to the next step. As a method of detecting the EOI signal, the EOI signal may be constantly monitored by a loop process, or an interrupt process may be activated by a fall of the service request terminal SRQ.

At step b4, the camera body inputs an MDC command to the distance measuring device to turn off the EOI output. That is, the operand eoi = 1 of the MDC command
To enter the command. As a result, the service request terminal SRQ enters a state in which a command execution end or an A / D conversion end (EOC) signal is notified.

When a command is input, the read / write terminal R
/ W is set to a high level. The command is input from the serial input / output terminal SIO in synchronization with the serial clock SCK supplied from the camera body.

At step b5, the camera body inputs a TRT command to the distance measuring device. Thereby, as shown in FIG. 13, the electric charge corresponding to the received light amount accumulated under the storage gate ST is transferred under the floating gate FG.

At steps b6 and b7, the clear gate is turned on and off. That is, the camera body inputs the PGC command as the operand cgc = 1 of the PGC command, and after the execution of the command, inputs the PGC command again as the operand cgc = 0. As a result, FIG.
As shown in FIG. In this way, by starting the reintegration immediately after the first integration operation is completed, the reintegration is performed in parallel during the analysis of the first integration result. The distance time can be reduced.

Next, referring to FIG. 30 and FIG. 31 (B),
The prescan operation will be described. Step b8-b
At 10, a dummy scan is performed. First, step b
In step 8, a scan start address and a scan end address of the dummy scan are set. That is, the camera body is
A desired address is set as an operand to the distance measuring device, and a SAS command and an EAS command are input.

At step b9, a gain is set. Specifically, the camera body sets a desired gain in an operand to the distance measuring device and inputs a GNS command. Thereby, the switches SW4 to SW6 of the CCD signal processing circuit 12 shown in FIG. 21 are set to a predetermined state, and the gain specified by the command is applied.

At step b10, a dummy scan is executed. Specifically, the camera body specifies execution of a dummy scan by an operand and inputs an SCT command to the distance measuring device. In the dummy scan, the output signal voltage VCCS of the pixel input to the contrast operation circuit 13 shown in FIG.
Is given a constant voltage. Therefore, the offset level of the contrast calculation circuit 13 is output after the end of the dummy scan. The value at this time becomes the zero level of the contrast value in the subsequent prescan.

When the dummy scan operation is completed, the distance measuring device sends an EOC signal from the service request terminal SRQ to notify the camera body of the completion of the operation. The camera body sets the read / write terminal R / W to low level, supplies the serial clock SCK to the distance measuring device, and reads data from the serial input / output terminal SIO.

At steps b11 to b13, a prescan is executed. In steps b11 and b12, a scan start address, a scan end address and a gain are set as in the case of the dummy scan. At this time, the gain is the same as the gain at the time of the dummy scan. This is because the offset changes when the gain is changed.

At step b13, a prescan is executed. Specifically, the camera body specifies execution of prescan with an operand and inputs an SCT command to the distance measuring device. When the prescan operation is completed, the ranging device sends an EOC signal from the service request terminal SRQ,
Notifies the camera body of the computation end. The camera body reads the contrast data from the serial input / output terminal SIO by performing the same processing as in the dummy scan.

When the reading of the contrast data is completed, the level data is set to the serial port 16 of the distance measuring device. The camera body reads the level data in the same way as the contrast data. Here, the level data is flag data shown in FIG.

As described above, the range specified by the scan start address and the scan end address is regarded as one zone, and the contrast data and the level data of the zone can be read.

In step b14, the camera body determines whether the entire range in which contrast data should be collected has been executed. If there is still a range in which contrast data should be collected, the scan start address and the scan end address are changed, and steps b11 to b13 are repeatedly executed. When the contrast data collection for the entire range is completed, the process proceeds to the next step.

As described above, the camera body can freely select the range in which contrast data is to be collected.
Also, the size of one zone for collecting contrast data can be set freely. Furthermore, it is possible for adjacent zones to overlap each other.

At Step b15, a main subject is detected. Usually, it is considered that the main subject is located in the zone having the highest contrast. If the predetermined contrast (contrast reference level) cannot be obtained and the main subject cannot be detected, the process proceeds to step b16, and it is determined whether or not execution of the repetitive integration can be performed. If the main subject has been detected, the process proceeds to step b19, and the main scan is executed.

When the contrast of each zone does not reach the predetermined level, or when searching for a zone having a higher contrast, the prescanning may be executed again from step b11 by expanding the contrast data collection range.

At step b16, it is determined whether or not the execution of the renormalization integration can be performed. If the contrast is low and the level data is high in all the selected zones, it is determined that distance measurement is impossible. When the contrast is low (for example, lower than the contrast reference level) and the level data is low (for example, lower than the reference signal level), the integration time is determined.

If the integration time is relatively short, it is possible to perform the integral integration, and the process proceeds to step b18 where the integral integration is performed. If the integration time is long and the integration cannot be performed, the process proceeds to step b17, the gain is changed, and the prescan is executed again. At this time, in the first pre-scan, non-destructive readout can be performed without initializing the amount of charge accumulated according to the amount of light received by each pixel, so the integration operation is repeated again in the second pre-scan. No need.

At step b17, a gain is selected. For example, when the output level of each pixel is low, a higher gain is selected and the process is executed again from step b11. At this time, it is preferable to select a gain as high as possible so as not to saturate the level data.

Next, the repetitive integration operation will be described with reference to FIGS. In step b18, the camera body inputs an MDC command to the distance measuring device, and the EOI
Turn on the output. That is, the command is input as the operand eoi = 0 of the MDC command. As a result, the service request terminal SRQ outputs the end of integration (EO
I) It is in a state to notify a signal. At this time, AGC commands 8a, 8b and A shown in FIG.
The level of the GC circuit 9 can be changed to increase or decrease the amount of integration.

After sending the MDC command, the process returns to step b3 and waits until the integration is completed. When the integration is completed, the ranging device sends an EOI signal from the service request terminal SRQ to notify the camera body of the completion of the integration. Since the renormalization integration starts from the step b7, the MD
In some cases, the integration has already been completed when the C command is input. In this case, the EOI signal is notified as soon as the MDC command is input.

As described above, by adding a charge corresponding to the amount of received light without discarding the charge accumulated in the integration operation up to the previous time, it is possible to obtain a level of contrast at which a main subject can be detected. There are cases.

Next, referring to FIG. 30 and FIG. 32 (B),
The main scan operation will be described. Step b19
The main scan is executed in steps b21 to b21. First, in step b19, a scan start address and a scan end address are set. Next, a gain is set in step b20. The setting method is the same as the method performed during the dummy scan in steps b8 and b9.

At step b21, a main scan is executed. Specifically, the camera body specifies execution of main scan by an operand and inputs an SCT command to the distance measuring device. When the A / D conversion of the output signal of one pixel is completed, the distance measuring device transmits the signal from the service request terminal SRQ to the A
A / D conversion end (EOC) signal is notified.

When the camera body receives the EOC signal,
The read / write terminal R / W is set to low level, the serial clock SCK is supplied to the distance measuring device, and data is read from the serial input / output terminal SIO. In parallel with the reading of the pixel data for one pixel, the distance measuring device starts A / D conversion of the next pixel, and notifies the EOC signal when the A / D conversion ends. By repeating this operation, pixel data of all pixels can be sequentially read.

At the time of prescan, only one of the right and left CCDs needs to be scanned, but at the time of main scan, both right and left CCDs need to be scanned.

At step b22, it is determined whether or not to perform a main scan on another area. If the main scan is to be performed on another area, the process returns to step b19, and the main scan is repeatedly executed by changing the scan start address, the scan end address, and the gain.
For example, when there are a plurality of main subject candidates, the main scan is also performed for other areas. This makes it possible to measure the distance for a plurality of subjects. When the main scan is completed for the area to be measured, the process proceeds to step b23.

At step b23, temperature data is read. Specifically, the camera body specifies the output of temperature information as an operand and inputs an SCT command to the distance measuring device.
When the A / D conversion is completed, the ranging device notifies the camera body of the EOC signal from the service request terminal SRQ, as in the case of the SCT command of the main scan.

The operation flow described above is an example in which the distance measuring apparatus of this embodiment is used. The distance measuring device of the present embodiment
Since a predetermined operation is performed by a command from the camera body, various usages are possible not only in the above-described usage example but also in a program of the camera-side microcomputer. For example, the size of the contrast measurement range, the method of detecting the main subject,
It is possible to freely set the focusing method when there are a plurality of main subjects, the size of the distance measurement range, and the like.

Further, by detecting the difference in luminance between a certain area of the main subject and another area, it is possible to obtain information as to whether the subject is in a backlight state or in a spotlight state.

As shown in FIG. 32B, at the time of executing the main scan, the distance measuring device transmits the pixel data to the camera microcomputer by serial communication while sequentially A / D converting the CCD output. For this reason, if the serial communication is interrupted, the pixel data is skipped, so that basically the serial communication cannot be interrupted. Therefore, it is necessary to interrupt the scanning operation when any interruption occurs in the camera microcomputer. The wait function for interrupting the scanning operation of the distance measuring device will be described below with reference to FIG.

The principle of the wait function is to stop the scan operation by stopping the clock in the distance measuring device by setting the wait terminal WAIT of the distance measuring device to high level. When the wait terminal WAIT is returned to the low level, the internal clock of the distance measuring apparatus starts to operate, and the scanning operation is restarted.

FIG. 33A shows a circuit for realizing a wait function, and FIG. 33B shows a timing chart thereof. Wait terminal WAIT is connected to flip-flop 120
Is connected to the D input contact. Clock terminal CLK0
Is connected to the CK input contact of the flip-flop 120, and the flip-flop 12
1 CK input contact.

The Q output contact of the flip-flop 120
It is connected to the D input contact of the flip-flop 121. The OR gate 124 has a flip-flop 120,
The clock terminal CLK0 is connected through the Q output contact 121 and the NOT gates 122 and 123 connected in series. The output of the OR gate 124 forms the clock signal CLK and is supplied to the distance measuring device.

When the wait terminal WAIT goes high, the output signal Q1 at the Q output contact of the flip-flop 120 goes high in synchronization with the rise of the clock CLK0. In synchronization with the next fall of the clock CLK0, the output signal Q2 at the Q output contact of the flip-flop 121 goes high.

When the wait terminal WAIT goes low, the output signal Q1 at the Q output contact of the flip-flop 120 goes low in synchronization with the rise of the clock CLK0. In synchronization with the next fall of the clock CLK0, the output signal Q2 at the Q output contact of the flip-flop 121 goes low.

When one of output signals Q1 and Q2 is at the high level, internal clock CLK supplied to the inside of the distance measuring device
Remains at the high level. Thus, when the wait terminal WAIT is at the high level, the internal clock CLK stops. The reason for delaying the rise and fall of the wait terminal and taking the OR with the clock CLK0 is to prevent the internal clock CLK from stopping at an incomplete timing.

When the clock frequency in the distance measuring device is high and the frequency of the serial clock SCK for serial communication is low, the pixel data read cycle is longer than the pixel scan cycle. Skipping occurs. Even in such a case, skipping can be prevented by using the weight function.

That is, when the service request terminal SRQ shown in FIG. 32 (B) falls, a high level is applied to the wait terminal WAIT to stop the internal clock CLK of the distance measuring device, thereby interrupting the scanning operation. In this state, serial communication is performed, and pixel data is slowly read. When the wait terminal WAIT is returned to the low level when the communication is completed, the distance measuring apparatus restarts the scanning operation.
Since the serial port transmits data in synchronization with the serial clock SCK, communication is possible even when the internal clock CLK of the distance measuring device is stopped.

As described above, by setting the wait terminal WAIT to the high level, processing other than the integration operation in the distance measuring apparatus can be interrupted. Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0294]

According to the present invention, the time for the photoelectric conversion operation for detecting the main subject and measuring the distance can be saved. For this reason, quick focusing becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram and a schematic operation flow of a distance measuring apparatus according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a distance measuring method according to an embodiment of the present invention.

FIG. 3 is a block diagram of a distance measuring apparatus according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a serial port of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 5 is a timing chart when data is input from a serial port.

FIG. 6 is a timing chart when data is output from a serial port.

FIG. 7 is a circuit diagram of an instruction decoding circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 8 is a conceptual diagram for explaining an arrangement of pixels of a CCD and an addressing method of a distance measuring apparatus according to an embodiment of the present invention.

FIG. 9 is a plan view, a sectional view, and a potential diagram of one pixel of a CCD of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 10 is a timing chart showing the drive timing of the CCD.

FIG. 11 is a potential diagram for explaining an integration start operation of the CCD.

FIG. 12 is a potential diagram for describing a repetitive integration start operation of the CCD.

FIG. 13 is a potential diagram for explaining a charge transfer operation of the CCD.

FIG. 14 is a potential diagram for explaining a scan start operation of the CCD.

FIG. 15 is a circuit diagram of a CCD of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 16 is a circuit diagram of a shift register unit of a pixel selector of a distance measuring apparatus according to an embodiment of the present invention.

FIG. 17 is a timing chart of a pixel selector.

FIG. 18 is a circuit diagram of an address decoding unit of a pixel selector of a distance measuring apparatus according to an embodiment of the present invention.

FIG. 19 is a circuit diagram of an address setting unit of a pixel selector of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 20 is a circuit diagram of an AGC monitor and an AGC circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 21 is a circuit diagram of a CCD signal processing circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 22 is a plan view, a cross-sectional view, a potential diagram, and a timing chart for explaining the operation principle of the contrast calculation circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 23 is a cross-sectional view, a potential diagram, a differential voltage generation circuit, and a circuit diagram of a contrast signal reading circuit of the contrast calculation circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 24 is a timing chart of the contrast calculation circuit.

FIG. 25 is a sectional view, a potential diagram, and a timing chart for explaining the operation principle of the floating diffusion type contrast calculation circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 26 is a circuit diagram of a signal level determination circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 27 is a table for explaining a relationship between digital pixel data and flag data.

FIG. 28 is a circuit diagram of a temperature detection circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 29 is a circuit diagram of a bias circuit of the distance measuring apparatus according to the embodiment of the present invention.

FIG. 30 is a flowchart illustrating an example of an operation flow when measuring distance using the distance measuring apparatus according to the embodiment of the present invention.

FIG. 31 is a timing chart of an integration operation and a prescan operation.

FIG. 32 is a timing chart of a repetitive integration operation and a main scan operation.

FIG. 33 is a circuit diagram and a timing chart for explaining a wait function.

FIG. 34 is a schematic diagram showing a configuration example of a conventional distance measuring device and a block diagram of a processing circuit.

[Explanation of symbols]

Reference Signs List 1 photoelectric conversion unit 2 memory unit 3 contrast calculation circuit 4 A / D conversion circuit 5 microcomputer 6 contrast measurement area 7, 7a, 7b high contrast area 8a, 8b AGC monitor 9 AGC circuit 10, 10a, 10b CCD 11, 11a 11b Pixel selector 12 CCD signal processing circuit 13 Contrast operation circuit 14 A / D conversion circuit 15 Signal level judgment circuit 16 Serial port 17 Instruction decoding circuit 18 Sequence control circuit 19 Input / output circuit 30 Shift register 30a-30h Flip-flop 31a-31h NAND circuit 32 the counter 33 control circuit 34 flip-flop 40a~40k decode circuit 41a~41k NAND, AND gate 50 p-type substrate 51 buried channel 52a, 52b p ⁺ region 0 Pixel 61 Readout circuit 70 Shift register 71, 72, 73, 74 NOR gate 75, 76 NAND gate 77, 78 Latch circuit 79 NOR gate 80 Scan end detection circuit 81 NAND gate group 82 Decoding signal line 83 Scan start address setting circuit 84 flip-flop 90 p-type substrate 91a, 91b, 92, 95 n ⁺ region 93 difference voltage generating circuit 94, 94a contrast signal reading circuit 100a-100h flip-flop 101 decoding circuit 102 NOR gate group 102a-102h NOR gate 103a-103h output Port 110 A / D converter 120, 121 D flip-flop 122, 123 NOT gate 124 OR circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-148910 (JP, A) JP-A-63-17416 (JP, A) JP-A-2-238415 (JP, A) JP-A-1- 230012 (JP, A) JP-A-62-95867 (JP, A) JP-A-64-18255 (JP, A) JP-A-3-20707 (JP, A) JP-A-2-50584 (JP, A) JP-A-64-39178 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02B ⁷ /28-7/40 G03B 13/36 H04N 5/222-5/257 H04N 5 / 30-5/335

Claims (11)

(57) [Claims] A plurality of pixels including an optical sensor for generating an image signal according to the amount of received light are linearly arranged, and a pair of pixels on which an object to be measured is formed via spatially different paths. A pixel array, an image signal storage unit provided for each pixel for storing an image signal generated by the optical sensor, and an image signal reading unit for non-destructively reading an image signal from the image signal storage unit. A pair of light receiving amount detecting means for measuring the amount of light applied to the pair of pixel arrays, detecting that the amount of received light has reached a predetermined level, and stopping an image signal generation operation by the optical sensor; A contrast calculating means for obtaining a contrast signal from the image signal read by the image signal reading means; and a signal level for detecting and storing a maximum value of the image signal. Judging means, when the contrast obtained by the contrast calculating means is lower than a contrast reference level, and when the maximum value of the image signal detected by the signal level judging means is lower than the reference signal level, Without discarding the image signal stored in the storage means,
An image signal transfer unit for adding an image signal newly generated by the optical sensor to an image signal stored in the image signal storage unit. 2. The optical sensor according to claim 1, further comprising a potential barrier provided in a region adjacent to the optical sensor, wherein a boundary with the optical sensor is separated by a potential barrier capable of controlling conduction / non-conduction. 2. The distance measuring apparatus according to claim 1, further comprising a charge accumulating unit provided for each pixel for temporarily accumulating. 3. The distance measuring apparatus according to claim 2, further comprising a charge discarding unit for discarding the charge stored in said charge storage unit. 4. The light receiving amount detecting means according to claim 1, wherein said light receiving amount detecting means can switch a reference level of a light receiving amount for stopping an image signal generating operation by said optical sensor. The distance measuring device as described. 5. The image signal reading means for controlling the image signal reading means to specify a pixel to start reading and a pixel to end reading in an operation of continuously reading image signals from the image signal storage means. 5. The distance measuring device according to claim 1, further comprising a scanning range setting unit. 6. A first photocharge storage step for storing photocharges generated by each of the photosensors forming a pair of photosensor arrays on which a subject to be measured is formed via spatially different paths. Transferring the photocharge to image signal storage means provided for each photosensor and storing the photocharge; and storing a photocharge newly generated by the photosensor in a second step.
And a step of detecting a contrast and a maximum amount of received light based on the photocharge stored in the image signal storage unit. When the contrast and the maximum amount of received light are equal to or less than a reference value, the second Adding a photocharge stored in the photocharge storage step to the photocharge stored in the image signal storage means. 7. The distance measuring method according to claim 6, further comprising the step of repeatedly performing the second photocharge storage step, the detection step, and the photocharge transfer step after the photocharge transfer step. 8. A pair of pixels including an optical sensor that generates an image signal according to the amount of received light is linearly arranged, and a pair of objects on which an object to be measured is formed via spatially different paths. A pixel array, an image signal storage unit provided for each pixel for storing an image signal generated by the optical sensor, and an image signal reading unit for non-destructively reading an image signal from the image signal storage unit. An image signal transfer for adding an image signal newly generated by the optical sensor to an image signal stored in the image signal storage unit without discarding the image signal stored in the image signal storage unit. And a distance measuring device. 9. The image processing apparatus according to claim 1, further comprising: a contrast calculating unit for obtaining a contrast signal from the image signal read by the image signal reading unit, wherein the image signal transferring unit determines that the contrast obtained by the contrast calculating unit is a contrast. When the image signal is lower than the reference level, the image signal newly generated by the optical sensor is replaced with the image signal stored in the image signal storage unit without discarding the image signal stored in the image signal storage unit. The distance measuring apparatus according to claim 8, which is added. 10. A pair of pixels for measuring an amount of light applied to the pair of pixel arrays, detecting that the amount of received light has reached a predetermined level, and stopping an image signal generation operation by the optical sensor. And a signal level determining means for detecting and storing a maximum value of the image signal, wherein the image signal transfer means has a maximum value of the image signal detected by the signal level determining means. When the image signal is lower than the reference signal level, the image signal newly generated by the optical sensor is stored in the image signal storage unit without discarding the image signal stored in the image signal storage unit. 9. The distance measuring apparatus according to claim 8, which is added to a signal. 11. A first accumulator that accumulates a photocharge generated by each of the photosensors constituting a pair of photosensor arrays on which an object to be measured is formed via spatially different paths.
A photo-charge storing step; a step of transferring and storing the photo-charge to image signal storage means provided for each of the photo-sensors; and a step of storing a photo-charge newly generated by the photo-sensor.
And a photo charge accumulation step of adding the photo charge accumulated in the second photo charge accumulation step to the photo charge stored in the image signal storage means.