JP3234965B2 - Color liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type color liquid crystal display device, and more particularly to a matrix type color liquid crystal display device which performs bidirectional horizontal scanning to display an image.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram showing a conventional example of a color liquid crystal display device. In the figure, 10 is a display pixel portion,
Reference numeral 20 denotes a vertical scanning circuit for performing vertical scanning of the display pixel unit 10, reference numeral 30 denotes a sampling circuit that samples an input image signal and outputs the sampled image signal to the display pixel unit 10, and reference numeral 40 denotes bidirectional horizontal scanning for sampling in the sampling circuit 30. Circuit. The bidirectional horizontal scanning circuit 40 includes, for example, one that switches output pulses of two scanning circuits having different scanning directions, or a type that incorporates a transfer direction switch.

The unit pixel of the display pixel section 10 is composed of a switching transistor 11, a liquid crystal and a pixel holding capacitor 12, the gate of the switching transistor 11 is connected to a vertical scanning circuit 20 by a gate line 13, and the input terminal of the switching transistor 11 Is the vertical data line 1
4 is connected to the sampling circuit 30. The other end of the pixel capacitor 12 is connected to the common electrode line 12-A, and a common electrode voltage _VLC is applied.

A color signal (red, blue, green) from a signal processing circuit 50 is supplied to an input of the sampling circuit 30. The signal processing circuit 50 performs gamma processing on the input image signal in consideration of liquid crystal characteristics, inversion signal processing for extending the life of the liquid crystal, and the like. In the control circuit 60, necessary pulses to be supplied to the vertical scanning circuit 20, the horizontal scanning circuit 40, the signal processing circuit 50 and the like are formed based on the input image signal.

The forward / reverse inversion switch SW connected to the control circuit 60 is for sending a switching pulse for changing the horizontal scanning direction from the control circuit 60 to the horizontal scanning circuit 40. For example, when observing a liquid crystal panel with a direct-view optical system, "H"
When observing through a reflection optical system, the scanning direction is reversed by setting it to "L".

FIG. 16 is an equivalent circuit diagram of the display pixel unit 10 and the sampling circuit 30. In the display pixel section 10, pixels of R, G, and B corresponding to three different colors, red, green, and blue, are sequentially and horizontally arranged in the order of R, G, and B to form a pixel row. The pixel rows are arranged in the vertical direction (vertical direction). Pixel positions of the same color are shifted by a distance of 1.5 pixels between adjacent rows. That is, the pixels (R, G, B) are arranged in a delta shape, and the pixels of the same color are connected to both sides of each data line 14 (d1, d2,...) For each row. I have. The sampling circuit 30 includes switching transistors SW1, SW
, And a capacitance (parasitic capacitance and pixel capacitance of the vertical data line), and the switching transistor S
By driving the gates of W1, SW2,... In a dot-sequential manner by the pulses h1, h2,.
The data is transferred and written to each pixel via the data line 14 (d1, d2,...). The selection of the row at that time is performed by the vertical scanning circuit 20.
Are controlled by vertical pulses φg1, φg2,.

In the dot sequential driving shown in FIG. 16, even if the scanning direction is changed by switching the forward / reverse inversion switch, the sampling is performed in accordance with the spatial pixel arrangement, so that the image quality is normal.

However, in the dot sequential driving of FIG. 16, the horizontal scanning pulses h1, h2, and h3 sample pixels of three colors (B, G, R) in a dot sequential manner. Frequency becomes very high. For example, NTSC
In a panel with 600 horizontal pixels, the sampling frequency for two rows in consideration of the pixel shift arrangement is about 20 MHz.
z. 1500 pixels for high definition display
Or more is required, in which case the sampling frequency will be about 50 MHz or more. Even with the current TFT liquid crystal,
Drivable frequency is more than ten MHz. Therefore, a plurality of scanning circuits are required to drive a high pixel panel.

In order to reduce the driving frequency, it is conceivable to simultaneously sample three color signals. The circuit configuration at this time is as shown in FIG. 17, where 2T and 4T are signal delay circuits having a delay time of one pixel and a delay time of two pixels on a horizontal pixel row, respectively. Since the pixels to be displayed are at different positions on the panel,
In order to compensate for the phase difference of the spatial displacement, in the forward scanning, the B signal passes through a delay circuit (4T) for two pixels.
The R signal passes through a delay circuit (2T) for one pixel. Even if the B, R, and G signals are simultaneously sampled by these delay circuits, the sampled signal becomes equivalent to the dot-sequential signal in the order of B, R, and G, and a correct image is displayed.

FIG. 18 is an explanatory diagram showing a state of interlaced scanning in a conventional liquid crystal display device having the same number of vertical pixels as the number of vertical scanning lines of a television. The pixels in each row of the display pixel portion (hereinafter, referred to as pixel rows) correspond to the vertical scanning pulses φg1, φg2,.
1, g2,... In the odd field, the signal of the horizontal scanning line odd1 is written to the row pixels g2 and g3, and similarly, the signal of odd2 is written to the row pixels g4 and g5. The drive after odd3 is performed every two rows. Also,
In the even field, the scanning combination is shifted by one line, and ev
The signal of en1 is written to row pixels g1 and g2, and even
The signal of n2 is written to the row pixels g3 and g4, and the subsequent signals are similarly written every two rows.

FIG. 19 shows an example of driving timing when the scanning example of FIG. 18 is applied to the conventional example of FIG. 16 (this driving method is a two-line simultaneous driving).
1, the vertical pulse φg2 corresponding to the row pixels g2 and g3
And φg3 become “H” (high state), the respective pixel transistors 11 (see FIG. 15) of the row pixel become conductive, and the image signal sequentially sampled by the sampling circuit 30 is output to each of the row pixels g2 and g3. Written to the pixel.
This sampling is performed by horizontal scanning pulses h1, h2,.
The “H” period is performed. Even in the scan after odd2,
Similar driving is performed.

[0012]

However, FIG.
In the conventional circuit configuration shown in (1), if the horizontal scanning direction is reversed (reverse scanning), a correct image cannot be displayed. That is, in the case of reverse scanning, the spatial phase on the panel is in the order of G, R, and B, but the sampled signal is in the order of B, R, and G by the delay circuit. Since the spatial sampling is different, the image is jagged and the color moiré becomes conspicuous in the high frequency region of the image.

Further, according to the conventional two-line simultaneous driving, the same sampling signal is written to pixels which are spatially separated by 1.5 pixels from two simultaneously driven row pixels, so that the driving method is simple. However, there is no improvement in the sampling frequency, and color moire occurs at low resolution. Further, a pixel shift arrangement shifted by 1.5 pixels in the horizontal direction has a bad effect that an edge portion of an image is displayed in a zigzag manner by driving by a combination of row pixels shifted by one line between an odd field and an even field. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. An image signal is sampled on a pixel having a scanning line number equal to or greater than that of a television by using a pulse of a low horizontal drive frequency, and a high resolution image is obtained. It is an object of the present invention to provide a color image display device capable of switching the horizontal scanning direction while performing a proper image display.

[0015]

The configuration of the present invention which has been achieved to achieve the above object is as follows.

That is, a first aspect of the present invention is a liquid crystal panel having a pixel group in which at least pixels corresponding to three different colors are sequentially and repeatedly arranged in the row direction in a predetermined order in a plurality of rows in the vertical direction. In a color liquid crystal display device comprising
Input image signal of one pixel set composed of three pixels
Sampling that sequentially samples signals at the same timing
Signal means for writing to each row pixel
And means, in order to compensate for the spatial positional deviation of 3 pixels each other constituting the repeating unit, before each color input signal line
A signal delay circuit for delaying an input image signal, and horizontal scanning
Spatial displacement between the three pixels that varies with direction
To accommodate the respective colors input in response to the horizontal scanning direction
And a switching means for switching the connection of the signal delay circuit and the signal line, 2 lines of sampling hands of the signal supply means
Stage for writing within one horizontal period to the respective set of pixels of the two rows to each other are adjacent, in the two rows
Sampling with a phase corresponding to the spatial arrangement of each pixel set
In the color liquid crystal display device which is characterized in that the grayed.

A second aspect of the present invention is a liquid crystal panel having a pixel group in which at least pixels corresponding to three different colors are repeatedly arranged in the row direction in a predetermined order in a plurality of rows in the vertical direction. In a color liquid crystal display device comprising
Input image signal of one pixel set composed of three pixels
Sampling that sequentially samples signals at the same timing
Signal means for writing to each row pixel
Means and three pixels connected to each of the three differently colored input signal lines and constituting the repeating unit.
In order to compensate for the positional displacement,
A / D conversion that takes A / D conversion timing of input image signal
An A / D converter for a pulse is input, to the A / D converter
A memory connected, a signal processing circuit having a D / A converter connected to said memory, changed by the horizontal scanning direction
To cope with the spatial displacement between the three pixels
In, and a switching means for switching the A / D conversion pulse to be sent to the A / D converter in accordance with the horizontal scanning direction, wherein
The two-system sampling means of the signal supply means writes the respective pixel sets of the two rows adjacent to each other within one horizontal period, so that the pixel sets of the two rows are adjacent to each other .
A color liquid crystal display device is characterized in that sampling is performed at a phase corresponding to a spatial arrangement .

[0018]

The first and second aspects of the present invention are further characterized in that the signal supply means includes the sampling means.
It consists of two signal supply means, each having one system.
And that the repeating units are arranged in a line-type RGB sequence, and the repeating units are arranged in a delta-type RGB sequence.

[0020]

[Embodiment and Function] [Embodiment 1 (Reference Embodiment) ] FIG. 1 shows a partial circuit configuration of a display device of this embodiment.

In this embodiment, the gates of the switching transistors connected to the three pixels of each line type RGB are simultaneously driven by a pulse from the horizontal scanning circuit.

In the forward scan, the pulses h _n , h
_{n + 1} , hn _{+ 2} ,...
In the reverse direction scanning, pulse _{h m, h m + 1,} h m + 2, ···
Are sequentially sampled.

Since the pixels to be displayed are at different points on the panel, in order to compensate for the phase difference of the spatial displacement,
In the forward scan, the B signal is a delay circuit for two pixels (2T)
, And the R signal passes through a delay circuit (1T) for one pixel.
On the other hand, in the reverse scanning, the switching signal φ from the switching circuit 70 is output.
SW switches the connection between the two switches SW, B
The G signal is passed through a delay circuit (2T) for two pixels without passing the signal through the delay circuit. FIG. 1 shows a switching state in the reverse scanning.

As described above, when the horizontal scanning direction is switched, the spatial sampling of the color signal becomes normal by switching the delay circuit in accordance with the arrangement of the R, G, and B pixels to be simultaneously sampled. For this reason, even in the case of performing image display by performing bidirectional horizontal scanning, a display image is not jagged by an image input signal in a high-frequency region, and color moiré can be made inconspicuous.

[Embodiment 2] FIG. 2 shows a partial schematic configuration diagram of a display device of this embodiment. In the figure, 31, 32, 3
3 and 31 ', 32', and 33 'are R, G, and B, respectively, for each color.
Signal line having color information corresponding to the filter of
Reference numerals 00 and 200 denote memory circuits for sampling and storing signals on the signal lines 31, 32, 33 and 31 ', 32', 33 ', respectively, and 300 denotes an interlace circuit. As a result, a drive signal is supplied to each pixel. Each pixel is provided with a switching transistor for applying a drive signal to the liquid crystal, a pixel electrode, and a filter. Reference numeral 15 denotes a delay circuit. The delay time 2T is a spatial sampling period between pixels in one row, and is about 90 ns when the number of horizontal pixels is 600. In order to match the phases of the B and R signals with the G signal, the delay of the B signal is 4T for two pixels and the delay of the R signal is 2T for one pixel. In the case of scanning inversion, the delay of the G signal with respect to the B signal is 4T.

As shown in FIG. 2, the pixels in each row are B, R,
The pixels in adjacent rows are shifted from each other by の of the repetition pitch. That is, the above-mentioned delta type array is provided. Therefore, pixels of the same color have 1.
The arrangement is shifted from each other by five pixels. Column data lines D1, D
2,... Dj are connected to pixels such that the color of the corresponding pixel in each row is any combination of B and G, R and B, and G and R.

In FIG. 2, column data lines D1 to D1
With respect to Dj, pixels of any one color of a set of B and G, R and B, and G and R are assigned to the left side and the other to the right side. In addition, the column data lines D1 to D
Each of j is connected to a reset switch Tr-c for resetting a residual charge of a column data line, a reset pulse φc is applied to its gate line, and a reset potential Vc is applied to its source. Further, the column data lines D1 to Dj are connected to memory circuits 100 and 200 for supplying each color signal. The memory circuits 100 and 200 include capacitors C11 to C1n and C21 to C2n as storage means.
And a transfer switch group T as a switching means.
r-T1 and Tr-T2.

Signal transfer from the memory circuits 100 and 200 to the column data lines D1 to Dj is controlled by transfer pulses φT1 and φT2 applied to the gates of the transfer switch groups Tr-T1 and Tr-T2. The B signal is stored in the memory C11 connected to the column data line D1, and the G signal is stored in the memory C21. Similarly, the R signal is stored in the memory C12 of the column data line D2, the B signal... Is stored in the memory C22. Signal lines 31, 32, 33 and 3
1 ', 32', and 33 'to each of the memory circuits 100 and 2
00 is controlled by bit pulses H11 to H1n and H21 to H2n from the horizontal shift register. The pulses H11 to H1 and H21 to H2n are applied in parallel to the gates of three sampling transistors, respectively, and the R, G, and B signals are simultaneously sampled by the pulses and temporarily stored in a memory. For example, capacitors C11, C12, and C13 each have B
1, R1 and G1 are connected to capacitors C22, C23,
Signals of B2, R2, and G2 are stored in C24, respectively.

The row control lines V1 to Vn connected to the gates of the switching transistors of each pixel are led to the interlace control circuit 300. Interlace control circuit 3
The gate electrode of the switch transistor 00 is guided to the vertical scanning circuit 20, and gate pulses φGo, φGe, and φG are applied to the source electrode, respectively.

FIG. 3 is a schematic block diagram of the display device of this embodiment. Horizontal scanning circuits 30-1 and 30-2 and memory circuits 100 and 200 are provided above and below a liquid crystal panel 10 having a pixel group having the arrangement shown in FIG. As shown in FIG. 3, the signal from the recording / reproducing device 60 is input to the signal processing circuit 40 and the control circuit 50, respectively, and the signal from the control circuit 50 is divided into two horizontal scanning circuits 30-1 and 30. -2. Also,
The signal from the signal processing circuit 40 is similarly input to the memory circuits 100 and 200 divided into two.
The control circuit 50 further supplies a signal to the vertical scanning circuit 20 and the signal processing circuit 40.

FIG. 4 is a timing chart of each signal in this embodiment. R (G, B) shown are signal lines 31-33,
These are signals input to 31 'to 33'. Each color signal is a pulse H11 from the horizontal scanning circuits 30-1 and 30-2.
To H1n and H21 to H2n are temporarily stored in the memories 100 and 200. The B, R, and G signals are simultaneously sampled by the pulses H11 to H1n and H21 to H2n, respectively. As shown, H11 to H1n and H
21 to H2n have a phase difference of 180 degrees. When the horizontal effective scanning period ends in this way, the blanking period (H
BLK), a gate pulse φGo (P2) is applied to the row control line (gate line) V1 and a reset pulse φ
c (P1) is applied simultaneously. Therefore, the pixel and the column data line connected to the gate line V1 are reset to the potential Vc. The reset potential Vc is preferably a black potential of the color signal, but may be an intermediate potential of the inverted signal. Next, the pulse φc is turned off and the transfer pulse φT1 (P3) is turned on, and the signal charges of the memory circuit 100 are written to the pixels connected to the gate line V1. Subsequently, a gate pulse φGe (P5) and a reset pulse φc (P4) are applied to the gate line V2, and the corresponding pixel and column data line are reset. Then, the pulse φT2 (P
6) is turned on, and the signal charges of the memory circuit 200 are written to the pixels connected to the gate line V2. A similar operation is repeated for one field period. In the next field, the gate pulses φGe and φG are output from the interlace control circuit 30.
0 (not shown) to perform interlace driving.

Since the three pixels B, R, and G, which are simultaneously sampled, are at different points on the panel, in order to compensate for the phase difference of the spatial displacement, the B signal is equivalent to two pixels in the forward scan. The R signal passes through a delay circuit (2T) for one pixel. On the other hand, in the reverse scan,
The connection of the three switches SW is switched by the switching signal φSW from the switching circuit 70, the B signal does not pass through the delay circuit, and the G signal passes through the delay circuit (4T) for two pixels. FIG. 2 shows a switching state in the forward scanning.

As described with reference to FIG. 4, in this embodiment, writing is performed on two adjacent pixel rows, odd and even, within one horizontal period (1H). As shown in FIG. 2, the odd-numbered rows (V1, V3,...) Are even-numbered rows (V2, V4,...) So that spatial sampling of the color signals of the rows can be normally performed regardless of the horizontal scanning direction.
The pixel arrangement and wiring connection are such that the number of repeating units of R, G, B is larger than that of (.)).

As shown in FIG. 4, the timing of the sampling pulse in the forward scan is H11, H21,
H12, H22, ..., H2 (n-1), and H1n. At this time, for example, three pixels B11, R11, and G11 corresponding to the pulse H11 correspond to three pixels B11, R11, and G11 corresponding to the pulse H21.
The spatial phase is 180 more than that of the pixels B21, R21, and G21.
Therefore, sampling corresponding to the spatial pixel arrangement is performed, and a correct image can be displayed.

On the other hand, although the timing of the sampling pulse in the reverse scanning is not shown in the figure, H1n, H
2 (n-1), H1 (n-1), H2 (n-2),.
, H21, H11. At this time, for example, the three pixels G1n, R1n, and B1n corresponding to the pulse H1n become the three pixels G2 (n-1),
The spatial phase is 1 more than R2 (n-1) and B2 (n-1).
Since it is ahead by 80 degrees, sampling corresponding to the spatial pixel arrangement is performed, and a correct image can be displayed.

Although the pulse numbers are different, the driving pulses H11 to H11 of the horizontal scanning circuit are independent of the horizontal scanning direction.
1n and H21 to H2n can be used without change.

The delay circuit according to the present invention is formed into an IC in a small-sized display device. In the circuit formed as an IC, it is necessary to adjust the frequency characteristic in order to compensate for variations in element characteristics. In the first embodiment, bidirectional horizontal scanning can be supported by three delay circuits and two changeover switches. However, in the present embodiment, it is realized by two delay circuits and three changeover switches. In addition, the adjustment man-hour can be reduced. Specifically, the delay circuit can be constituted by an LC circuit for discrete components, and a time constant circuit or a sample-and-hold circuit controlled by gm for an IC.

With the configuration of the present embodiment described above, it is possible to display an image excellent in both horizontal resolution and vertical resolution and free from flicker.

The relationship between the spatial phase of the pixel and the phase of the sampling pulse is determined by the wiring connection between the pixel and the horizontal scanning circuit and the sampling circuit (memory circuit) near both ends of the two pixel rows. Yes, simply R, G, B
Is not determined only by the number of repeating units of the three pixels.

In FIG. 2, the arrangement is shifted by 1/2 pixel. However, as shown in FIG. 5, an aligned arrangement without shifting the pixel may be used. In this case, the sampling pulses H11 to H1
n and H21 to H2n may have the same phase.

[Embodiment 3] FIG. 6 is a schematic block diagram of a display device of this embodiment. This embodiment is the same as the second embodiment in the panel configuration, the signal delay circuit, and the wiring for the horizontal drive pulse, but the input signal is different. That is, in the second embodiment, the sampling phase is changed from the same signal of R, G, and B to write to the pixels in two rows, but in the present embodiment, the odd field signal is supplied to the memory circuit 100 by the frame memory 80 and to the even circuit. The field signal is taken into the memory circuit 200, and signals of both odd and even fields are simultaneously displayed. By this driving, it is possible to obtain extremely excellent image performance without flicker in both the horizontal resolution and the vertical resolution.

Although not particularly mentioned in the above description,
In order to prevent the deterioration of the liquid crystal, it is preferable that the polarity applied to the liquid crystal be alternately reversed (inverted driving). In this case, the polarities may be reversed in accordance with the signals that are distributed up and down, or the polarities may be reversed for each frame. In the above description, R,
Although an example using three colors of G and B has been described, other colors may be further combined as necessary.

The configuration of, for example, a memory circuit shown in each of the above embodiments is merely an example, and it goes without saying that the configuration can be appropriately modified as long as it has a similar function. For example, if one more column data line is added and pixels of each row are connected, a memory circuit is not required. Double-speed scanning in which two pixel rows are continuously written in the same time as one horizontal scan may be used. It is also natural that the present invention can be appropriately modified within the scope of the present invention.

[Embodiments 4 to 6] Another embodiment will be described with reference to FIGS. Also in these drawings, the concept of the panel configuration, the signal delay circuit, and the wiring related to the horizontal drive pulse is the same as in the second embodiment.

FIG. 7 is a diagram in which the connection of the pixels to the column data lines is changed. Pixels of the same color are alternately connected to one column data line for each row.

FIG. 8 shows a configuration in which sampling of color signals is simultaneously performed on two rows of pixel columns. In this example, 2
The pixel signals B1, R1, G1 (B2, R2, G2,.
Are sampled at the same time, and the spatial sampling period in the horizontal direction is の of that in the second embodiment, so that the delay time of the delay circuit 15 is １ ／ (however, the substantial spatial sampling period of two rows is (Equivalent to Example 2). Therefore, when the delay circuit 15 is configured by an analog circuit, the shorter the delay time, the better the phase characteristics and the higher the image quality.

FIG. 9 is the same as the pixel connection method of FIG. 5, but has the same effect as that of FIG. 8 because the color signals are sampled simultaneously for two rows of pixel columns.

[Embodiment 7] In the above-described embodiments 1 to 6, a signal delay circuit and a signal delay circuit are provided in order to make the spatial phase and the sampling phase of the three pixels R, G, and B the same during bidirectional horizontal scanning. Although an apparatus including means for switching the connection of the signal delay circuit according to the horizontal scanning direction has been described, a circuit corresponding to the signal delay circuit may be configured using a memory (analog, digital).

In this embodiment, an example in digital processing will be described, but it is also possible to replace it with analog processing.

FIG. 10 shows a schematic block configuration for bidirectional horizontal scanning in the color liquid crystal display device of this embodiment.
In the figure, reference numeral 401 denotes an A / D converter, 402 denotes a digital memory, 403 denotes a D / A converter, and 404 denotes a driver.

In the case of the forward scanning, the signals of the respective signal lines at the same timing of the sampling switch input must be, for example, B _n , R _{n + 1} , G _{n + 2 in} terms of the phase relationship, and in the reverse direction. In the case of scanning, it is necessary to set _Gn , Rn _{+ 1} , and _{Bn + 2} . Therefore, in the present embodiment, as shown in FIG. 10, the A / D conversion pulses φ _{B / G} and φ _{G / B} of the B and G signals.
Is switched when the scanning direction is reversed.

FIG. 11 shows an A / D conversion timing chart in this embodiment, and FIG. 12 shows an output signal at the time of D / A conversion.

In this embodiment, in a display device having a digital processing system, A / A is switched according to switching of the horizontal scanning direction.
By the simple operation of switching the D conversion pulse,
Sampling corresponding to the spatial pixel arrangement of the liquid crystal panel becomes possible. Further, since the delay circuit as described above is unnecessary, there is an effect that adjustment of these delay amounts is not required.

[Embodiment 8 (Reference Embodiment) ] An example of a color liquid crystal display device performing left-right reversal display using a memory will be described.

This embodiment employs a method in which the horizontal scanning direction of the panel is not changed at the time of horizontal reversal, and the readout of the memory is changed. FIG.
FIG. 14 shows an output signal at the time of left-right inversion.

The writing to the memory in this embodiment is the same as that in the seventh embodiment, except that the signal reading from the memory is read by counting up the address in the reverse direction.

Since the panel always scans in the forward direction, the signal from the memory is read out in the reverse direction, and as shown in FIG.
_{n + 1,} R _n, by simultaneous sampling a signal G _n-1, and displays the images of the right and left reversed. By providing a means for counting the addresses of the memory and sequentially reading the signals from the memory in accordance with the counted addresses and a means for switching the counting direction of the addresses in accordance with the normal display or the inverted display, the left-right inversion is provided. The corresponding bidirectional horizontal scanning circuit becomes unnecessary. Therefore, the horizontal scanning circuit is simplified, the area occupied by the circuit is reduced, and the panel accommodation rate and the yield are improved.

[0058]

As described in the foregoing, according to the color liquid crystal display device of the present invention, Oite the case of performing image display by performing bidirectional horizontal scanning, simultaneous corresponding to the spatial pixel arrangement of a liquid crystal panel Since sampling can be performed, high-resolution display faithful to an image signal can be performed.

Further, the color liquid crystal display device of the present invention samples an image signal with a pulse of a low horizontal drive frequency on a pixel having a scanning line number equal to or greater than that of a television, and displays a high-resolution image while maintaining a high resolution image display. it is possible to switch the bidirectional horizontal run 査.

Further, in the first color liquid crystal display device of the present invention, it is not necessary to switch the driving pulse of the horizontal scanning circuit irrespective of the horizontal scanning direction. Is achieved.

[Brief description of the drawings]

FIG. 1 is a partial circuit configuration diagram of a display device shown in Embodiment 1.

FIG. 2 is a schematic configuration diagram of a display device according to a second embodiment.

FIG. 3 is a schematic block diagram of the embodiment shown in FIG. 2;

FIG. 4 is a timing chart of each signal in the embodiment shown in FIG. 2;

FIG. 5 is a diagram showing an example of a pixel array applied to the present invention.

FIG. 6 is a schematic block diagram of a display device according to a third embodiment.

FIG. 7 is a schematic configuration diagram of an embodiment in which connection of pixels to vertical signal lines is changed from the embodiment of FIG. 2;

FIG. 8 is a schematic configuration diagram of an embodiment in which sampling of a color signal is performed simultaneously in two rows of pixel columns.

FIG. 9 is a schematic configuration diagram of another embodiment in which sampling of a color signal is performed simultaneously in two rows of pixel columns.

FIG. 10 is a schematic block diagram for bidirectional horizontal scanning in the display device shown in Embodiment 7.

FIG. 11 is an A / D conversion timing chart in the display device shown in the seventh embodiment.

FIG. 12 is a diagram showing output signals at the time of D / A conversion in the display device shown in Embodiment 7.

FIG. 13 is an A / D conversion timing chart in the eighth embodiment.

FIG. 14 is a diagram showing output signals at the time of left-right inversion in the eighth embodiment.

FIG. 15 is a block diagram showing a conventional example of a color liquid crystal display device.

16 is an equivalent circuit diagram of the display pixel unit 10 and the sampling circuit 30 in the display device of FIG.

FIG. 17 is a schematic configuration diagram showing a conventional example of a color liquid crystal display device that performs simultaneous sampling.

FIG. 18 is an explanatory diagram showing a state of interlaced scanning in a conventional liquid crystal display device.

19 is a timing chart showing an example of driving timing when the scanning example of FIG. 18 is applied to the conventional example of FIG. 16;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal panel 11 Switching transistor 12 Pixel electrode 13 Row control line 14 Column control line 15 Delay circuit 20 Vertical scanning circuit 30, 30-1, 30-2 Horizontal scanning circuit 31, 32, 33, 31 ', 32', 33 ' Signal line 40 Signal processing circuit 50 Control circuit 60 Recording / reproducing device 70 Switching circuit 100, 200 Memory circuit (sampling circuit) 300 Interlace circuit 401 A / D converter 402 Digital memory 403 D / A converter 404 Driver

Continuation of the front page (56) References JP-A-8-36159 (JP, A) JP-A-3-136594 (JP, A) JP-A-4-116687 (JP, A) JP-A-63-231395 (JP) JP-A-1-193897 (JP, A) JP-A-59-158178 (JP, A) JP-A-5-173514 (JP, A) JP-A-7-152905 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66-5/70

Claims (5)

(57) [Claims] 1. A least, a liquid crystal panel having a pixel group multiline arranged sequentially repeatedly arranged rows of pixels pixels corresponding to three different colors in the row direction in a predetermined order in the vertical direction
A color liquid crystal display device that performs bidirectional horizontal scanning, wherein one of the three pixels constituting the repeating unit is
The input image signals for the set of pixels are sequentially supported at the same timing.
The system has two sampling means for sampling.
To compensate the signal supply means for writing to a row of pixels, the spatial positional deviation of 3 pixels each other constituting the repeating unit, the input image of each color input signal line
A signal delay circuit for delaying an image signal ;
To accommodate misalignment in response to said horizontal scanning direction
Switching means for switching the connection between each color input signal line and the signal delay circuit; and two sampling means of the signal supply means write to each pixel group of two rows adjacent to each other within one horizontal period. Each pixel in the two rows to perform
A color liquid crystal display device characterized in that sampling is performed at a phase corresponding to the spatial arrangement of sets . Wherein at least a liquid crystal panel having a pixel group multiline arranged sequentially repeatedly arranged rows of pixels pixels corresponding to three different colors in the row direction in a predetermined order in the vertical direction
A color liquid crystal display device that performs bidirectional horizontal scanning, wherein one of the three pixels constituting the repeating unit is
The input image signals for the set of pixels are sequentially supported at the same timing.
The system has two sampling means for sampling.
A signal supply means for writing to a row pixel, and a signal supply means connected to each of the three different color input signal lines ;
Spatial positions of the three pixels that make up the repeating unit
The input image of each color input signal line to compensate for the shift
A / D conversion pulse that takes the A / D conversion timing of the signal
An input A / D converter, and connected to the A / D converter
That memory and a signal processing circuit having a D / A converter connected to said memory, spatial the three pixels mutually changing the horizontal scanning direction
To accommodate misalignment and a switching means for switching the A / D conversion pulse to be sent to the A / D converter in accordance with the horizontal scanning direction, sampling means of two systems of the signal supply means, with each other In order to write to each of the pixel sets in two adjacent rows within one horizontal period, each pixel in the two rows is written.
A color liquid crystal display device characterized in that sampling is performed at a phase corresponding to the spatial arrangement of sets . 3. The signal supply means according to claim 2 , wherein
From two signal supply means, each having one means
The color liquid according to claim 1 or 2, wherein
Crystal display device. 4. The color liquid crystal display device according to claim 1, wherein the repeating units are arranged in a line type RGB. 5. The color liquid crystal display device according to claim 1, wherein the repeating units are arranged in a delta type RGB.