JP3398709B2 - Burst frame transfer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst frame transfer system used in a VDSL system or the like, and particularly when transferring a burst frame using a pair cable used for a telephone line as a transmission path. The present invention relates to a burst frame transfer system that prevents near-end crosstalk.

[0002]

2. Description of the Related Art With the spread of the Internet, not only text information but also large-capacity information such as images, voices, and videos are actively communicated from various servers. In such a situation, VDSL
(Very high-bit-rate DegitalSubscriber Line, Very
The establishment of a high-speed communication environment such as a high-speed digital subscriber line is very important. In particular, the existing telecommunications carriers have a huge amount of assets, which are so-called twisted pair access lines using existing metallic cables. Therefore, it is a big problem to effectively utilize this and provide a high level service.

FIG. 9 shows such a VDS that has been conventionally proposed.
It is a diagram showing an outline of a communication system using the L system. VDSL modem 201 by-N units arranged on the terminal side in the communication system, connected to one each corresponding one of the first to M interface converter 203 ₁ ～203 _M of the metallic cable 202 to 1 Has been done. S interface converter 203 ₁ ~203 _M first to M is due to SDH (synchronous digital hierarchy) as an international standard for high-speed relaying rate system
TM (synchronous transfer mode) -1 signal and VDS
It is a device that performs interface conversion with an L signal. Interface converter of the first to _M 203 ₁ ~203 M
Each of the metallic cables 202 connected to has a lower limit of 64 Kbps and an upper limit of 2 when symmetrical transmission.
6 Mbps, 52 Mbps downlink for asymmetric transmission,
Data can be transferred at a transfer rate in the range of 6 Mbps upstream. These first to M interface converter 203 ₁ ～203 _M of possible connecting N number of metallic cables 202, respectively (illustrated one by one in the figure)
Therefore, the total transfer rate of these N metallic cables 202 is in the range of 64 Kbps to 156 Mbps. Here, 2 KHz ping-pong transmission method (TDD; Ti
me Division Duplexed).

First to Mth interface conversion devices 20
3 ₁ ~203 _M is between N number of cross-connect device 204, STM-1 by SDH with an optical cable 205
It is designed to transfer frames. Each optical cable 205 can transfer data at a transfer rate of 156 Mbps. Cross connect device 204
Between the SDH communication network 207 and the SDH communication network 207.
8 and repeater 209 are arranged in L sets. Here, the optical cable 21 is provided between the cross-connect device 204 and the terminal multiplex relay device 208, between the terminal multiplex relay device 208 and the repeater 209, and between the repeater 209 and the SDH communication network 207.
1, 212, 213 are arranged. These optical cables 211, 212, and 213 are adapted to transfer STM-1 frames by SDH at a transfer rate of 156 Mbps. Interface converter 203 ₁ ~203 _M first to M are each optical cable 20
2 KHz clock source 222 by line 221 different from 5
And a 2 KHz clock signal 223 is supplied. 2 KHz clock source 222
Are arranged in some upper device.

[0005] The first to interface converter 203 ₁ ~203 _M of the M in this communication system, for converting the signal format of the STM-1 frame and the VDSL signal. The clock signal 223 is used to prevent near-end crosstalk between metallic cables during burst frame transfer.

FIG. 10 shows a main part of a VDSL system in this communication system. Here, in order to simplify the explanation, the first interface converter 203 ₁
Shows the part related to. The first interface conversion unit 203 ₁ via a real line 225 V of the first to N
It is connected to the DSL modems 201 _{1 to} 201 _N.

FIG. 11 shows a case where the phases of the burst frames as the transmission signal and the reception signal output from the first and second VDSL modems in the VDSL system shown in FIG. 10 are out of phase. 12 is shown in FIG.
The first and second VDSL in the VDSL system shown in
It shows the case where the phases of the burst frames as the transmission signal and the reception signal output from the modem are in phase. In the example shown in FIG. 11, the real line 2 shown in FIG.
The transmission signal 231 ₁ transmitted from the first VDSL modem 201 ₁ to the first interface conversion device 203 _{1 at} 25
And from the first interface converter 203 ₁ to the first
Transmission timing of the reception signal 232 ₁ sent to the VDSL modem 201 ₁ and the transmission signal 231 ₂ sent from the _second VDSL modem 201 ₂ to the first interface conversion device 203 ₁ and the first interface conversion device 2
The transmission timing of the reception signal 232 ₂ sent from 03 ₁ to the second VDSL modem 201 ₂ is deviated. Therefore, transmission signals 231 _1, 231 ₂ and the reception signal 232 _1, 2
A time zone 235 in which 32 ₂ temporally overlaps occurs. Near-end crosstalk will occur during this time.

At the timing of the example shown in FIG.
Timing of the transmission signal 231 ₁ transmitted from the VDSL modem 201 ₁ to the first interface conversion device 203 ₁ and the transmission signal 231 ₂ transmitted from the _first VDSL modem 201 ₁ to the second interface conversion device 203 ₂ . And the transmission timing of the reception signal 232 ₁ sent from the first interface converter 203 ₁ to the first VDSL modem 201 ₁ in the same manner, and the first interface converter 203 ₁ to the second VDSL modem. 201 ₂
The transmission timing of the reception signal 232 ₂ sent to the receiver is the same. As described above, since the transmission signal, the transmission signal, and the reception signal and the reception signal completely match in each time zone 236, far-end crosstalk does not occur in these time zones.

It has been known that when near-end crosstalk as shown in FIG. 11 occurs, the line quality is greatly deteriorated. Figure 1
The far-end crosstalk shown in 2 has less influence on the line quality than the near-end crosstalk. Therefore, the first to the Mth shown in FIG.
Interface converter 203 _1-203 of _M is, 2KH
2 KHz clock signal 223 from the z clock source 222
The clock signal 223 is used to make the 2 KHz burst frame timings coincide with each other.

FIG. 13 shows the structure of an interface conversion device in this conventional system. Figure 9
1st to Mth interface converters 203 ₁ shown in FIG.
～203 _M, since identical in circuit configuration will be described of the circuit the first interface conversion unit 203 ₁ as an example here. The first interface conversion unit 203 _1, the first to N of VDSL modems 201 ₁ ～201 _N and one by one the first to VDSL line card 241 ₁ ～241 _N of the N corresponding shown in FIG. 9 It is prepared, and these are connected one to one. These VDSL line cards 241 ₁ ~241 _N of the first to N may, SDH
STM-1 interface block 242 and 2 KHz
It is connected to the clock receiving unit 243. The 2 KHz clock receiving unit 243 receives the 2 KHz clock signal 223 and uses it as the clock signal 251 for the first to N-th V signals.
And supplies it to the DSL line card 241 ₁ ~241 _N.

SDH STM-1 interface block
242 is the same as the cross-connect device 204 shown in FIG.
Connected to the first to Nth VDSL line cards 2
41 ₁~ 241_NRead in synchronization with the clock signal 251
The transmitted transmission signal 231 is transmitted to the SDH STM-1 interface.
Input to the base block 242 and STM by SDH-
It is sent to the cross-connect device 204 as one frame 261.
Or from the cross-connect device 204
Received data 232 from the received STM-1 frame 261
To the first to Nth VDSL line cards 241₁
~ 241_NTo output to the corresponding one of
ing.

[0012]

In such a conventional apparatus for burst frame transfer, each interface conversion apparatus 203 obtains a 2 KHz clock signal common to them from an external 2 KHz clock source 222. . For this reason, each interface conversion device 203 needs to arrange a line 221 different from the optical cable 205 for receiving a clock signal with the common 2 KHz clock source 222, which is a communication system using the VDSL system. There was a problem that it cost a lot of money to build.

Therefore, an object of the present invention is to provide a burst frame transfer system which realizes simplification of supply of a clock signal used for preventing near-end crosstalk when a metallic cable is used in a high-speed communication environment. It is in.

[0014]

According to a first aspect of the present invention, (a) communication terminals divided into a plurality of groups,
(B) It is arranged between the cross-connect device and (c) the communication terminal and the cross-connect device, and is provided for each group that converts the format of signals handled by these communication terminals and the signal handled by the cross-connect device for each group of communication terminals. And a cable for individually connecting the signal format conversion means, (d) each communication terminal of each group corresponding to each signal format conversion means, and (e) a cable provided for each signal format conversion means, and a predetermined cable is provided on the cable. Data transmission means for transmitting high-speed data in synchronization with a reference clock signal of a frequency; (to) a clock signal supply source for supplying the reference clock signal to the cross-connect device; and (g) from this clock signal supply source. Identification information indicating the timing that has the same cycle as the supplied reference clock signal and the position of the frame with respect to the reference clock signal. Cross-connect device side clock information transmitting means for incorporating the phase information representing the difference into the signal format converting means of each group at a cycle shorter than the cycle of the reference clock signal, and (h) respective signal format converting means. The identification information is taken out from the signal sent from the clock information sending means provided on the side of the cross-connect device to reproduce the clock signal having the same frequency as the reference clock signal and the phase information is taken out to obtain the same frequency as the reference clock signal. A burst frame transfer system is provided with a signal format conversion means side clock signal generation means for correcting the phase of a clock signal.

That is, according to the first aspect of the invention, the signal transmitted between the cross-connect device and the signal format conversion means for each group is a signal having the same frequency as the reference clock signal supplied to the cross-connect device side. The identification information for reproducing and the phase information with respect to the reference clock signal are incorporated and transmitted to each signal format conversion means side. On the signal format conversion means side, by extracting the identification information, a signal having the same frequency as the reference clock signal can be obtained, and the phase can be matched using the phase information. Therefore, if the clock signals reproduced by the respective signal format conversion means are used to communicate with the communication terminals of each group, the timing of the frames of the signals transmitted through the respective cables can be adjusted, and near-end crosstalk can be prevented. be able to.

According to the second aspect of the invention, (a) the communication terminals divided into a plurality of groups, (b) the cross-connect device, and (c) the communication terminals are arranged between the communication terminals and the cross-connect device. A signal format conversion means provided for each group for converting the formats of the signals handled by these groups and the signals handled by the cross-connect device,
(D) A cable for individually connecting each signal format conversion means to each communication terminal of the corresponding group, and (e) a signal format conversion means provided for each unit, and the cable is synchronized with a reference clock signal of a predetermined frequency. Data transmission means for transmitting high-speed data, (i) a clock signal supply source for supplying a reference clock signal prepared in one of the signal format conversion means, and (g) a clock signal supply source supplied from this clock signal supply source. The identification information indicating the timing having the same cycle as the reference clock signal and the phase information indicating the phase difference of the frame with respect to the reference clock signal are incorporated and sent to the cross-connect device side at a cycle shorter than the cycle of the reference clock signal. And a signal format conversion means side clock information transmission means, and (h) this signal format conversion means side clock information transmission means. Cross-connect device side clock information sending means for incorporating identification information and phase information and sending to each group of signal format converting means at a cycle shorter than the cycle of the reference clock signal, and (i) signal format converting means side clock information The identification information is taken out from the signal sent from the clock information sending means provided on the side of each signal format converting means without the sending means to reproduce the clock signal having the same frequency as the reference clock signal and the phase information. And a signal format converting means-side clock signal generating means for correcting the phase of a clock signal having the same frequency as the reference clock signal is provided in the burst frame transfer system.

That is, in the invention described in claim 2, the signal transmitted between the cross-connect device and the signal format conversion means for each group has the same frequency as the reference clock signal prepared on one of the signal format conversion means sides. The identification information for reproducing the signal and the phase information for the reference clock signal are incorporated and transmitted from the signal format conversion means to the cross-connect device. The cross-connect device transfers this to the signal to be transmitted with the respective signal format conversion means. Therefore, each signal format conversion means can obtain the signal of the same frequency as the reference clock signal by extracting the identification information, and can match the phase using the phase information. Therefore, if the clock signals reproduced by the respective signal format conversion means are used to communicate with the communication terminals of each group, the timing of the frames of the signals transmitted through the respective cables can be adjusted, and near-end crosstalk can be prevented. be able to.

According to a third aspect of the present invention, in the burst frame transfer system according to the first or second aspect, the cable is a metallic cable, the reference clock signal is a 2 KHz signal, and the data transmission means is a 2 KHz burst. The feature is that the frame is transmitted to the metallic cable.

That is, according to the third aspect of the invention, near-end crosstalk is prevented when a 2 KHz burst frame is transmitted to an existing metallic cable.

According to a fourth aspect of the present invention, in the burst frame transfer system according to the first aspect, the clock signal supply source for supplying the reference clock signal is built in the cross-connect device.

That is, the invention according to claim 4 indicates that not only the reference clock signal may be externally supplied to the cross-connect device, but it may be built-in.

According to a fifth aspect of the present invention, in the burst frame transfer system according to the first or second aspect, the signal format conversion means and the cross-connect device are SDH-based S.
The feature is that the TM-1 signal is transmitted.

The invention according to claim 6 is the burst frame transfer system according to claim 1 or claim 2, characterized in that the signal format conversion means and the communication terminal transmit a VDSL signal.

[0024]

DETAILED DESCRIPTION OF THE INVENTION

[0025]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows an outline of an example of a communication system using a burst frame transfer system according to an embodiment of the present invention. In this communication system, N VDSL modems are arranged for each N terminal 1
01 is a first to Mth interface conversion device 1031 to _1st through a pair of metallic cables 102, respectively.
It is connected to the corresponding one of 103 _M. First
~ The Mth interface converters 103 _{1 to} 103 _M are S
STM by DH (synchronous digital hierarchy)
(Synchronous transfer mode) -1 signal and VDSL (V
ery high-bit-rate Degital Subscriber Line, Very hi
gh-speed Degital Subscriber Line) A device that performs interface conversion with signals. The lower limit of the metallic cable 102 connected to the _first to Mth interface converters 103 _{1 to} 103 _M is 64 kbps, and the upper limit is 26 Mbps for symmetrical transmission, 52 Mbps downstream for asymmetric transmission, and 6 Mbps upstream. Data can be transferred at a transfer rate within the range. Since N metallic cables 102 can be connected to each of the _first to M-th interface conversion devices 103 _{1 to} 103 _M (one is illustrated in the figure), the N metallic cables 1 are connected.
02 total transfer rate from 64Kbps to 156Mbp
It becomes the range of s. Here, a 2 KHz ping-pong transmission system (TDD; Time Division Duplexed) is adopted.

The first to Mth interface converters 10
3 _{1 to} 103 _M are STM-1 by SDH using the optical cable 105 between N cross-connect devices 104.
It is designed to transfer frames. Each optical cable 105 can transfer data at a transfer rate of 156 Mbps. Cross connect device 104
Between the SDH communication network 107 and the SDH communication network 107.
8 sets of relays 109 are arranged. The terminal repeater 108 is provided for long-distance and large-capacity data transmission. Between the cross-connect device 104 and the terminal multiplex relay device 108, between the terminal multiplex relay device 108 and the repeater 109, and between the repeater 109 and the SDH communication network 107.
Optical cables 111, 112, and 113 are arranged between them. These optical cables 111, 112, 113
156 each STM-1 frame by SDH
Transfer is performed at a transfer rate of Mbps.

In this communication system, the VDSL modem 101 is arranged in, for example, an office or home.
Interface converter 103 ₁ 10 @ 2 to 10 @ 3 _M is located in the machine room, for example, pillars and buildings. Cross-connect device 104 is located within the telephone company.

FIG. 2 shows the configuration of the interface conversion apparatus of this embodiment. First to Mth shown in FIG.
Interface converter 103 ₁ 10 @ 2 to 10 @ 3 _M of, so have the same circuit configuration, will be described in the circuit of the first interface conversion unit 103 ₁ as an example here. The first interface conversion device 103 ₁ includes
VDSL modems 101 ₁ to 101 _N of the first to N shown in
When one by one and VDSL linecard 141 ₁ ～141 _N first to N corresponding are prepared, it is connected one-to-one. The first to N-th VDSL line cards 141 _{1 to} 141 _N include an SDH STM-1 interface block 142 and a 2 KHz clock recovery unit 143.
It is connected to the. The 2 KHz clock recovery unit 143 is S
The phase data 144 is received from the DHSTM-1 interface block 142 and the 2 KHz clock signal is reproduced. The reproduced 2 KHz clock signal 146 is supplied to the _{first to} Nth VDSL line cards 141 _{1 to} 141 _N.

SDH STM-1 interface block
142 is the same as the cross-connect device 104 shown in FIG.
Connected and the 1st to Nth VDSL line cards 1
41 ₁~ 141_NRead in synchronization with the clock signal 146 from
The transmitted transmission signal 151 is transmitted to the SDH STM-1 interface.
Input to the base block 142 and STM by SDH-
Send as one frame 152 to the cross-connect device 104
Or from the cross-connect device 104
Received data obtained from the received STM-1 frame 152
Data 154 to the first to Nth VDSL line cards 141₁
~ 141_NTo output to the corresponding one of
ing.

FIG. 3 and FIG. 4 show two STM-1 frames.
It represents one frame format. The STM-1 frame 152A shown in FIG. 3 corresponds to the STM-1 frame shown in FIG.
Like one frame 152B, it is repeated at a transfer rate of 156 Mbps at a cycle of 8 KHz, and is also called an SDH superframe. STM-shown in FIG.
One frame 152A is a SOH (Sect
Ion Over Head) 161A and a payload 162A accommodating actual data. STM-
As shown in the figure, three VC-3 units 163 are accommodated in the payload 162A of one frame 152A. Path overhead (POH) 1 of each VC-3 unit 163
The “H4” byte 165 in which the values of “0” to “3” are repeated in order is accommodated in 64. This "H4"
Byte 165 is a pointer (position information) used to indicate “0” to “3” as a multi-frame number of TU (Tributary Unit), and the signal state is “0”.
It repeatedly changes to 0 ”,“ 01 ”,“ 10 ”, and“ 11. ”Therefore, the STM-1 frame 152
A specific one of the "H4" bytes 165 in A is sequentially extracted, and a cycle in which this has the same value (for example, the value "0") is calculated to be 2 KHz.

The STM-1 frame 152B shown in FIG.
2 is composed of a SOH 161B as a management area and a payload 162B accommodating actual data. As shown in the figure, V is included in the payload 162B.
One C-3 part 163 is housed. VC-3 part 16
The 3rd path overhead (POH) 164 accommodates an “H4” byte 165 that sequentially repeats the values from “0” to “3”. Therefore, the "H4" byte 165 in the STM-1 frame 152B is sequentially extracted, and the cycle in which the same value (for example, the value "0") is obtained is 2 KHz. That is, in the STM-1 frames 152A and 152B shown in both FIG. 3 and FIG. 4, the 2 KHz clock source 2 in FIG.
It is possible to extract a clock signal similar to the 2 KHz clock signal 223 obtained from the step 22.

FIG. 5 shows the configuration of the phase information generation circuit arranged on the cross-connect device side. The phase information generation circuit 171 is a 2 KHz component detection circuit 172.
And a counter 173 arranged in the subsequent stage, and a 2 KHz phase detection section 174 arranged in the subsequent stage. The "H4" byte 165 described in FIGS. 3 and 4 is input to the 2 KHz component detection circuit 172. 2K
The Hz component detection circuit 172 inputs "H4" byte 1
The signal states of 65 are "00", "01", "10", "1"
When it becomes "00" of 1 ", the frame zero phase detection signal 175 is output to the counter 173. The counter 173 receives" 0 "to" 4095 "by a clock signal (not shown) of 8.192 MHz. Up to the SDH superframe (8KH
The count value is reset to "0" by the frame timing signal 176 output at the head timing of z), and the counting is restarted from this point. Counter 17
The 12-bit count value information 177 representing the count value output from 3 is input to the 2 KHz phase detection unit 174.

The 2 KHz phase detection unit 174 is adapted to input a 2 KHz burst frame timing signal 178 received from a clock supply device (not shown) on the network side, and 12-bit count value information 177 at this input timing. Is output and is also output as 12-bit phase information 179. This phase information 179 is SOH 161A shown in FIG. 3 or SO shown in FIG.
It is incorporated in a vacant specific area in H161B, and is sent to the _first to Mth interface conversion devices 103 _{1 to} 103 _M together with the data.

FIG. 6 shows the configuration of the 2 KHz clock reproducing section on the side of the first interface converter. Interface converter of the second to M 103 ₂ to 1
Since 03 _M also has the completely same circuit for the 2 KHz clock recovery unit 143, illustration and description thereof are omitted.

The SDH STM-1 interface block 142 in the _first interface converter 103 ₁ shown in FIG. 2 has the 12-bit phase information 1 described in FIG.
79 is extracted and used as phase data 144 for 2 KH.
It is supplied to the first 2 KHz phase detection unit 181 in the z clock reproduction unit 143. In the 2 KHz clock reproduction unit 143, "H4" obtained based on the STM-1 frame 152
2KH to detect 2KHz component from byte 165
A z component detection circuit 182 is also provided. This is a circuit having the same configuration as the 2 KHz component detection circuit 172 in FIG. Output from the 2 KHz component detection circuit 182,
The frame zero phase detection signal 183 indicating that the signal state of the “H4” byte 165 is “00” is the counter 184.
It is designed to be output to. The counter 184, similar to the counter 173 shown in FIG.
From “0” to “409” by a clock signal (not shown)
Values up to 5 "are counted. The counter 184 outputs the frame timing signal 18 output at the beginning timing of the SDH superframe (8 KHz).
5 is input. The 12-bit count value information 186 representing the count value output from the counter 184 is supplied to the second 2 KHz phase detector 187. These first and second 2 KHz phase detectors 1
A phase comparator 188 is provided on the output side of 81 and 187, and a 2 KHz burst frame signal generation circuit 189 is provided on the output side thereof. First and second two
The KHz phase detectors 181 and 187 are adapted to input the 2 KHz clock signal 191 output from the 2 KHz burst frame signal generation circuit 189 as a latch signal.

Such a 2 KHz clock reproducing unit 143
Then, the 2 KHz component detection circuit 182 uses the “H4” byte 16
When the signal state of No. 5 becomes "00", the frame zero phase detection signal 183 indicating this is output to the counter 184. The counter 184 has an SDH superframe (8KH
The frame timing signal 185 output at the top timing of z) is input. The counter 184 resets its count value to "0" at the timing when the frame timing signal 185 is input, and repeats the operation of restarting counting from this point. Then, when the frame zero phase detection signal 183 is input, 12-bit count value information 186 representing the count value at that time is supplied to the second 2 KHz phase detection unit 187. The 12-bit count value information 186 is latched at the rising edge of the 2 KHz clock signal 191 generated by the 2 KHz burst frame signal generation circuit 189, and its output is the 12-bit count value data 193 as the phase comparator 188.
Is supplied to. Similarly, the first 2 KHz phase detection unit 181 takes in the phase data 144 at that time sent from the cross-connect device 104 side by the 2 KHz clock signal 191, and compares the phase data 144 as 12-bit phase data 194. To the container 188.

The phase comparator 188 has the 12-bit count value data 193 and the 12-bit phase data 194.
Subtract. For example, the count value data 193 on the _first interface converter 103 ₁ side is “00000
000101 ", the cross-connect device 1
The phase data 194 on the 04 side is “00000000100
The phase comparator 188 performs these subtractions and outputs the calculation result “0x03” to the 2 KHz burst frame signal generation circuit 189.
Supply as 5. The 2 KHz burst frame signal generation circuit 189 uses the calculation result data 195 as the basis for the first
The phase of the 2 KHz burst frame signal on the side of the interface conversion device 103 ₁ is adjusted to the side of the cross-connect device 104, and the phase-matched 2 KHz clock signal 191
Will be output.

The adjusting the phase of 2KHz clock signals between in this example of an interface conversion device 103 ₁ and the cross-connect device 104 first using a 2KHz clock reproducing unit 143 of the first interface conversion unit 103 ₁ side I explained an example. The second to the interface converter 103 ₂ 10 @ 2 to 10 @ 3 _M of the M in the same manner to adjust the phase of 2KHz clock signal between the cross-connect device 104. Thus, these devices 104 and 103 ₁ to 1
It is possible to obtain the same effect as when the common 2 KHz clock signal is used among the 03 _M.

FIG. 7 shows these cross-connect devices and
It shows the relationship of the M-th interface conversion device. Here, using the common SDH communication network, the cross-connect device 104 is used as a master station, and the common 2 KHz is used among the _first to M-th interface conversion devices 103 _{1 to} 103 _M.
This means that the clock signal of can be used. These cross-connect devices 104 are used as master stations for clock signals, and the first to Mth interface conversion devices 103 ₁
Since the STM-1 frame is transmitted between ˜103 _M , any device can be a master station as long as the device has a clock signal source. An example thereof will be described in the following modified example.

Modification

FIG. 8 shows the basic configuration of a burst frame transfer system when the master station for clock signals is the first interface converter. This modified system is useful, for example, when there is no 2 KHz clock signal source on the network side. In this example, 2 KH included in the first interface converter 103 ₁
The phase of the 2 KHz clock signal is synchronized with the z clock signal source as a reference.

In the case of this example, 2K is added to the STM-1 frame transmitted by the _first interface converter 103 _1.
The phase information of the Hz burst frame and the identification information about the frequency corresponding to the “H4” byte 165 shown in the embodiment are incorporated and sent to the cross-connect device 104. The cross-connect device 104 incorporates the phase information and the frequency identification information in the same manner when sending the STM-1 frame to the _{second to M-th} interface conversion devices 1032 to 103M and sends them out. As a result, 2 KHz common to these devices 104, 103 _{1 to} 103 _M
It is possible to obtain the same effect as when using the clock signal of.

In the embodiment, the frequency of 2 KHz is reproduced by extracting the special signal state of the "H4" byte 165 by using the STM-1 frame 152A which is repeated at 8 KHz. Similarly, by incorporating identification information such as “H4” byte 165 into a signal having a frequency higher than the frequency to be transferred,
A desired frequency can be reproduced. Therefore, it goes without saying that the present invention is not limited to reproducing a clock signal having a frequency of 2 KHz and adjusting the phase thereof.

[0045]

As described above, claim 1 and claim 3
According to the invention of claim 6, the signal transmitted between the cross-connect device and the signal format conversion means for each group is a signal having the same frequency as the reference clock signal supplied to the cross-connect device side. Identification information for reproduction and phase information for the reference clock signal are incorporated and transmitted to each signal format conversion means side, and the identification information is extracted on the signal format conversion means side to obtain the same frequency as the reference clock signal. Signal is obtained and the phase is adjusted by using the phase information. Therefore, not only near-end crosstalk can be prevented, but also it is not necessary to provide a line for transmitting a clock signal from one clock supply source to each signal format conversion means, which results in cost and time required for system construction. You can save. Moreover, since the clock signal is regenerated using the existing signal, there is an advantage that the traffic of the signal does not increase.

According to the second, third, fifth and sixth aspects of the present invention, any one of the signals transmitted between the cross-connect device and the signal format conversion means for each group is used. The identification information for reproducing a signal having the same frequency as the reference clock signal prepared on the format conversion means side and the phase information for the reference clock signal are incorporated and transmitted from the signal format conversion means to the cross connect device. The connecting device transfers the signals to be transmitted to the respective signal format conversion means, so that each signal format conversion means extracts the identification information to obtain the signal having the same frequency as the reference clock signal, and the phase information is used. The phase can be adjusted. Therefore,
Not only can near-end crosstalk be prevented, but there is no need to provide a line for transmitting a clock signal from one clock supply source to each signal format conversion means, which saves cost and time required for system construction. be able to. Moreover, since the clock signal is regenerated using the existing signal, there is an advantage that the traffic of the signal does not increase.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an outline of an example of a communication system using a burst frame transfer system in an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an interface conversion device of this embodiment.

FIG. 3 is an explanatory diagram showing a first frame format of an STM-1 frame.

FIG. 4 is an explanatory diagram showing a second frame format of an STM-1 frame.

FIG. 5 is a block diagram showing a configuration of a phase information generation circuit arranged on the cross-connect device side in this embodiment.

FIG. 6 is a block diagram showing the configuration of a 2 KHz clock recovery unit on the side of the first interface conversion device in this embodiment.

FIG. 7 is a cross-connect device according to the present embodiment and first to
It is explanatory drawing which showed the relationship of the Mth interface conversion apparatus.

FIG. 8 is a system configuration diagram showing a principle configuration of a burst frame transfer system when a master station of a clock signal is a first interface conversion device as a modified example of the invention.

FIG. 9 is a system configuration diagram showing an outline of a communication system using a conventionally proposed VDSL system.

FIG. 10 is a schematic configuration diagram showing a main part of a VDSL system in a conventional communication system.

FIG. 11 is a timing chart showing a case where the phases of burst frames as transmission signals and reception signals output from the first and second VDSL modems in the VDSL system shown in FIG. 10 are out of phase.

FIG. 12 is a timing diagram showing a case where the phases of burst frames as transmission signals and reception signals output from the first and second VDSL modems are in phase in the VDSL system shown in FIG.

FIG. 13 is a block diagram showing a configuration of the conventional interface conversion device shown in FIG.

[Explanation of symbols]

101 VDSL modem 102 metallic cable 103 Interface conversion device 104 Cross-connect device 107 SDH communication network 108 terminal repeater 142 SDH STM-1 Interface Block 143 2KHz clock recovery unit 144 Phase data 146,191 2KHz clock signal 152 STM-1 frame 161 SOH (Section Over Head) 162 payload 165 "H4" bytes 171 Phase information generation circuit 172,182 2KHz component detection circuit 173 and 184 counters 174 2KHz phase detector 179 Phase information 181 First 2 KHz Phase Detector 187 Second 2 KHz phase detector 188 Phase comparator

Front page continuation (51) Int.Cl. ⁷ identification code FI H04Q 11/04 304 H04L 11/20 B (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 3/00 H04J 3/06 H04L 7/04 H04L 12/66 H04Q 11/04 304

Claims (6)

(57) [Claims] 1. A communication terminal that is divided into a plurality of groups, a cross-connect device, and a signal that is arranged between the communication terminal and the cross-connect device and that is handled by each group of communication terminals and a signal that the cross-connect device handles. A signal format conversion means provided for each group for converting the format of the above, a cable for individually connecting each signal format conversion means to each communication terminal of the corresponding group, and a signal format conversion means provided for each unit. A data transmission means for transmitting high-speed data to the cable in synchronization with a reference clock signal of a predetermined frequency; a clock signal supply source for supplying the reference clock signal to the cross-connect device; Identification information that represents the timing of the same cycle as the reference clock signal supplied from
Cross-connect device side clock information sending means for incorporating the phase information representing the phase difference of the frame with respect to the reference clock signal and sending it to the signal format conversion means of each group at a cycle shorter than the cycle of the reference clock signal. , The phase information and the identification information is taken out from the signal sent from the clock information sending means provided on the signal format converting means side to reproduce the clock signal having the same frequency as the reference clock signal. And a signal format conversion means side clock signal generation means for extracting the clock signal and correcting the phase of the clock signal having the same frequency as the reference clock signal. 2. A communication terminal that is divided into a plurality of groups, a cross-connect device, and a signal that is arranged between the communication terminal and the cross-connect device and that is handled by each group of communication terminals and a signal that the cross-connect device handles. A signal format conversion means provided for each group for converting the format of the above, a cable for individually connecting each signal format conversion means to each communication terminal of the corresponding group, and a signal format conversion means provided for each unit. A data transmission means for transmitting high-speed data in a cable in synchronization with a reference clock signal of a predetermined frequency; and a clock signal supply source for supplying the reference clock signal prepared in any of the signal format conversion means, Identification information indicating a timing having the same cycle as the reference clock signal supplied from the clock signal supply source, ,
A signal format conversion means side clock information sending means for incorporating the phase information representing the phase difference of the frame with respect to the reference clock signal and sending it to the cross connect device side in a cycle shorter than the cycle of the reference clock signal, and this signal format Cross-connect device side clock that incorporates the identification information and the phase information sent from the conversion means side clock information sending means and sends to the signal format conversion means of each group at a cycle shorter than the cycle of the reference clock signal Information identifying means and the signal format converting means side clock information transmitting means are not provided. The identification information is extracted from the signal transmitted from the cross connect device side clock information transmitting means provided on the signal format converting means side. When a clock signal having the same frequency as the reference clock signal is reproduced, The burst frame transfer system, characterized in that an extracted phase information and a signal format conversion means side clock signal generating means for correcting the phase of the clock signal of the reference clock signal and the same frequency. 3. The cable is a metallic cable, the reference clock signal is a 2 KHz signal, and the data transmission means transmits a 2 KHz burst frame to the metallic cable.
Alternatively, the burst frame transfer system according to claim 2. 4. The burst frame transfer system according to claim 1, wherein a clock signal supply source for supplying the reference clock signal is built in the cross-connect device. 5. The burst frame transfer system according to claim 1 or 2, wherein the signal format conversion means and the cross-connect device perform STM-1 signal transmission by SDH. 6. The burst frame transfer system according to claim 1, wherein the signal format conversion means and the communication terminal transmit a VDSL signal.