JP3428955B2 - Buffer battery power supply system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery power supply system, and more particularly to a buffered battery charger circuit capable of controlling the power supplied to an operating system and a rechargeable battery. A utility unique to the present invention resides in a power supply system for portable electronic devices. However, other utilities are also considered here.

[0002]

Prior Art and Problems to be Solved by the Invention FIG.
FIG. 1 is a simplified block schematic diagram of a conventional general power supply topology 20 for a portable electronic system 24. Operating system 24 derives power from either battery 18 or external input power adapter 10.
The power is regulated by the system DC / DC converter 22. The input power adapter 10 draws power from an external primary power source, such as an AC outlet or a DC power source, and provides the power directly to the system DC / DC converter 22 (through a separate diode 12) and Directly to the battery charger 14. While the primary power source is unavailable, the battery 18 allows the system D to pass through a separate diode 16.
It is connected to the C / DC converter 22 and provides power. When the primary power source is available, the battery is isolated from the power input of system DC / DC converter 22 by reverse-polarized (reverse-biased) diode 16. Further, the battery 18 is charged through the charger 14 when power is provided by the primary power source. This topology shown in FIG. 1 has the drawback that "a large and rapid voltage transient occurs at node 25, which is the input of system DC / DC converter 22".

FIG. 2 shows a buffer battery power supply 2
Figure 3 shows a simplified block diagram of a 0'topology. The battery pack 18 is the system DC / DC converter 2
It is always connected to the two inputs and provides the required power. An external input power adapter 10 powers the battery charger 14 when an external primary power source is available. The external input power adapter 10 is intended to adapt the parameters of the primary source to the charger input requirements. The battery charger 14 includes a system DC / DC to charge the battery 18 or to maintain the voltage of the fully charged battery at an optimum level.
Both converter 22 and battery 18 are powered in parallel. This "buffer battery topology"
Is the system DC / DC converter input (node 25)
Limits the voltage change at the normal battery pack voltage change and suppresses rapid voltage transients at this input. Further, if the power required by system 24 temporarily exceeds the capacity of input power adapter 10,
Both the input power adapter 10 and the battery 18
In parallel, power to system 24 is driven through converter 22. Unfortunately, however, the circuit 20 'shown in FIG. 2 provides a mechanism by which the power provided by the battery charger may be increased or decreased (based on preset limits and / or demands from the battery and / or system). Do not provide.

Similarly, US Patent No. 5,698, to Kates et al.
The 964 provides a battery charging circuit topology.
This circuit monitors the current from the AC adapter (ie, I _in ) and adaptively utilizes all available current to charge the battery. System DC / D
The C converter is directly powered by the AC adapter after the AC adapter is connected. The battery is disconnected from the system. Therefore, the voltage at the input of the system DC / DC converter remains a large transient (from the low voltage of the uncharged battery to the AC adapter voltage). The AC adapter voltage is always higher than the maximum charged battery voltage. In addition, the AC adapter output voltage can change, so that AC to both the system (eg, portable electronic device) and the battery is
No control is actually provided for the power delivered by the adapter. A similar topology is provided in Bell, US Pat. No. 5,723,970. The topology has similar and / or additional drawbacks to those mentioned above.

Therefore, there is a need to provide a buffered battery power supply system that can control both the total output power and the power delivered to the battery. Further, there is a need to provide a system that significantly reduces the voltage transients that occur in electronic devices and / or batteries.

[0006]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a buffer battery power supply system with feedback control of both the total output current delivered by the battery charger circuit and the voltage delivered to the battery. This solves the drawbacks mentioned above. In addition, feedback control is provided based on the total output power (total output current x total output voltage) delivered by the battery charger circuit.

In one embodiment of the present invention, a power supply system is provided that includes a charger circuit for generating a duty cycle. The duty cycle is for delivering power to the operating system and the battery.
A first feedback loop is provided to sense the total output current produced by the charger circuit, and a second feedback loop is provided to sense the current delivered by the charger circuit to the battery. First
The feedback loop and the second feedback loop include an error circuit for generating an error signal to the charger circuit. The charger circuit regulates the duty cycle, thereby controlling the total output current delivered to the operating system and the battery based on the value of the error signal.

In another embodiment of the invention, a power supply system is provided that includes an input power source and a charger circuit. The charger circuit is for generating a duty cycle for controlling the input power source to deliver controlled power to the operating system and the battery. A first feedback loop is provided to sense the total output current produced by the charger circuit. The first feedback loop generates a first error signal based on the total output current and the preset threshold total output current signal. A second feedback loop is provided to sense the current delivered by the charger circuit to the battery. The second feedback loop produces a second error signal based on the current delivered to the battery and the preset threshold battery current signal.
A third feedback loop is provided to sense the total output power produced by the charger circuit. The third feedback loop generates a third error signal based on the total output power and the preset threshold total output power signal. The charger circuit adjusts the duty cycle using the first error signal, the second error signal, and the third error signal. The duty cycle is for controlling the total output current and total output power delivered to the operating system and the battery.

In method form, the present invention provides a method of regulating the current delivered by a charger circuit to an operating system and a battery. The method comprises detecting a first error signal based on the total output current of the charger circuit and the preset threshold total output current signal. The method also includes detecting a second error signal based on the current sent by the charger circuit to the battery and the preset threshold battery current signal. One of the first error signal or the second error signal is provided as a feedback signal to the charger circuit. The charger circuit regulates the delivered current based on the first feedback error signal or the second feedback error signal.

[0010]

DETAILED DESCRIPTION OF THE INVENTION The following detailed description proceeds with reference to preferred embodiments and methods of use, but the invention is not intended to be limited to these preferred embodiments and methods of use. Will be understood by those skilled in the art. Rather, the invention is intended to be broad and limited only as set forth in the appended claims.

Other features and advantages of the present invention will become apparent as the following detailed description proceeds and by reference to the drawings. In the drawings, the same numbers represent the same parts. The drawings are as follows: FIG. 1 is a block diagram of a prior art power supply circuit topology.
FIG. 2 is a block diagram of another prior art power supply circuit topology. FIG. 3 is a block diagram of a preferred embodiment of the power supply system of the present invention. FIG. 4 is a detailed circuit diagram of the embodiment of FIG. FIG. 5 is a detailed circuit diagram of another embodiment of the power supply system of the present invention. Figure 6
FIG. 6 is a detailed circuit diagram of an example of a current-voltage multiplication circuit provided in the embodiment of FIG. 5. FIG. 7 is a detailed circuit diagram of another example of the current-voltage multiplication circuit provided in the embodiment of FIG.

FIG. 3 shows a block diagram of a preferred embodiment of the battery power system 30 according to the present invention. As mentioned above, the battery pack 18 is always connected to the system DC / DC converter through the sensing register 34. Preferably, the resistor 34 is a very low value resistor and is intended to sense the current into and out of the battery 18 (with a negligible voltage drop). The battery charger 32 is connected to the system DC / DC converter input (node 25) through a separate diode 12 and sense resistor 26. When the input power adapter 10 has an available primary power source and is connected to the system 30, the battery charger 32 provides the required power to the operating system 24 through the DC / DC converter 22. And at the same time, the battery 18 is charged. The battery charge current and the voltage on node 25 are
It is regulated by the battery charger 32. The battery charging current is detected by the detection register 34.
Battery charger 32 uses a feedback connection from current sense resistor 34 and a feedback connection from node 25. In addition, the total battery charger output current is sensed by the sense resistor 26 and limited to a safe value by using the feedback connection from the sense resistor 26 to the battery charger 32.
The battery charger 32 reacts by reducing the charging current. The feedback connection via the sense registers 26, 34 is described in more detail below.

Referring to FIG. 4, there is shown a detailed circuit diagram of the battery charger circuit 32 according to one embodiment of the present invention. Switching MOS transistors 40 and 42, Schottky diode 46, indicator 44, capacitor 48 and pulse width modulator 38 together form a controlled buck converter. In this embodiment, the duty cycle of the buck converter pulse is controlled by the pulse width modulator 38 through at least three feedback loops. The 3
The feedback loops are I) a voltage loop provided around the error amplifier 60, II) a battery charge current loop using the battery charge current sense amplifier 64 and the error amplifier 58, and III) an output current sense amplifier 62.
And a total output current limiting loop incorporating a comparator 56. The diodes 50, 52, 54 ensure that "the most negative value (ie the diode with the most reverse bias) passes to the PWM 38". This is the largest measure of error. Therefore, it provides control of the output parameter which has reached the limit value.

When the input power adapter 10 provides power to the charger input, the pulse width modulator 38 begins to generate pulses that drive the gates of the power MOS transistors 40,42. As a result, a voltage appears on the output of the charger. The duty cycle of the pulse depends on the feedback voltage received by the PWM 38 from the feedback loop. The duty cycle increases as long as none of the set limits is exceeded. And this raises the output voltage of the buck converter. The set limits are preferably defined as preset inputs, as described below. When the output voltage of the buck converter exceeds the battery voltage, circuit 80 switches to the ON state and the output voltage reaches node 25. This current is distributed between the system DC / DC converter 22 and the battery 18. The current flowing to the battery causes a voltage drop in the detection resistor 34. This voltage is sense amplifier 64
And is compared with the programmed value I _DAC by the error amplifier 58. When the charging current exceeds the programmed value I _DAC , the output of error amplifier 58 becomes negative and flows through diode 52 and reduces the PWM duty cycle (to keep the charging current at the programmed value). . Similarly, the error amplifier 60
Compares the battery voltage with a programmed value V _DAC and when the charging voltage exceeds the programmed value V _DAC , the duty cycle of the buck converter decreases. Similarly, the total output current of the buck converter causes a voltage drop on the sense resistor 26. This voltage drop is amplified by the sense amplifier 62 and compared by the error amplifier 56 with the preset value I out — _max . When the total output current exceeds the preset value, the output of the error amplifier 56 becomes negative,
And the signal flows through the diode 50, and
The duty cycle is reduced (to keep the total output current at the preset limit). This reduction causes a decrease in battery charging current. As is known, the battery's internal resistance is low, so the battery charging current is
It decreases very rapidly as the voltage decreases. Conversely, the current drawn by the system DC / DC converter 22 is only slightly affected by this voltage change. Therefore, the total current I _{TOT at} node 25 remains constant while the battery charge current decreases. Therefore, the current allocated to the system DC / DC converter 22 is increased. The total output current of the buck converter is
Up to preset limits are assigned to system 24.
Furthermore, if the system demands more power, the voltage will drop even further and the battery will
Couples with the buck converter when providing power. This feature allows the use of smaller and cheaper input power adapters.

The signal V _DAC is a programmed signal indicating the maximum voltage that can be safely delivered to the battery 18 (ie, the threshold value allowed by the battery for safe operation). The signal I _DAC is a programmed signal indicating the maximum current that can be safely delivered to the battery 18 (ie, the threshold value allowed by the battery for safe operation). In some cases (i.e., if battery 18 is a so-called "smart battery" that provides a signal indicative of the maximum allowable power of battery 18), battery 18 may provide signal V _DAC and signal I _DAC. And are supplied in digital form. Therefore, for the purpose of comparison in the error amplifiers 60, 58, as described above, V
A D / A converter (not shown) is provided to convert each of the _DAC and the I _DAC to an analog signal. other,
V _DAC and I _DAC can be generated by other programmable circuits (not shown), which are known in the art. Furthermore, the reference signal I
_{out_max} is another preset threshold value.
The preset threshold value indicates the maximum allowed current that the PWM is allowed to send to prevent overcurrent from being sent by the charger circuit 32. I
_{out_max} can be generated by a voltage divider circuit (not shown) or other current generating circuit known in the art.

"In this embodiment, the diode 12
Should preferably be replaced with the circuit 80. " Both the diode 12 (FIG. 3) and the circuit 80 have a reverse current from the battery 18 to the PWM.
Prevent reaching. However, the circuit 80
Only a very small forward voltage is needed to bring ON into the ON state. ”Circuit 80 has the additional advantage over the diode. As a result, the circuit 80
It has a very small voltage drop compared to a diode. Therefore, the circuit 80 causes very little loss in the system. The circuit 80 executes a process of cutting off a reverse current from the battery to the charger. Circuit 80
Comprises a MOS transistor 70 incorporating a body diode 72. The MOS transistor 70 is driven by the comparator 66. Comparator 66
Are designed to have a limited positive offset. The offset is provided by the bias source 68. While the voltage on the MOS drain is negative with respect to the source of the MOS, the output of comparator 66 is "H" and MOS transistor 70 is in the OFF state. When the MOS drain voltage exceeds the offset, the output of the comparator 66 becomes "L" and the MOS transistor 70 is turned on. As a result, the circuit 80 behaves like a diode, with a very low forward voltage drop.

The power supply system shown in FIG. 4 limits the total output current of the buck converter. Since the buck converter output voltage depends on the battery voltage, in the case of a fully charged battery this output voltage limiting method forces the buck converter to deliver less power than the buck converter's rating. Therefore, in addition to controlling the parameters shown in FIG. 4, another solution is to control and limit the buck converter output power.

FIG. 5 illustrates system 32 '. System 32 'is similar to the system of Figure 4, but with an additional power limiting loop. The voltage drop in the sense resistor 26 is proportional to the total output current I _OUT and the output current sense amplifier 6
Applies to both 2 and multiplier 82. Also, the output voltage V _OUT is sensed through a second connection to the multiplier.
By multiplying the total output current value by the output voltage value, the multiplier 82 provides as its output a voltage PWR_OUT proportional to the output voltage. Like the other loops, the PWR_OUT voltage is compared by the comparator 84 to the set limits. The amplified error drives the pulse width modulator 38 through the diode 86. The function of this diode is similar to that of the other diodes 50, 52, 54 described above with reference to FIG.

An exemplary circuit 82 for multiplying the output current value and the output voltage value of the buck converter is shown in FIG. The voltage drop across sense resistor 26 is applied to transconductance amplifier 88. This provides the current K × I _out . The current K × I _out is proportional to the voltage drop and hence the total output current. MOS transistor 90 divides this current with the same duty cycle as the buck converter. For that purpose, a duty signal is provided to the control line of transistor 90. The resulting current is integrated by an integrator circuit provided around the operational amplifier 92 using the integrated RC group 94. The output voltage of the integrator 92 is proportional to the total output power of the buck converter.

Another illustrative circuit 82 'for multiplying the output current value and the output voltage value is shown in FIG. This circuit is an amplifying differential stage.
Based on the well-known properties of. The output voltage at such a stage is approximately proportional to the product of the common source current (I = k × V _out ) and the differential input voltage. The differential amplifier stage shown in FIG. 7 has (each coupled to a reference voltage V _CC )
The common source transistors 98 and 100 are provided. The differential inputs are connected to the total current sense register 26. Therefore,
The output voltage provided by amplifier 96 is proportional to the buck converter output power.

It is therefore clear that "a buffer battery power supply circuit is provided which fulfills the purposes stated here". Those skilled in the art will appreciate that "the present invention may be modified and / or exchanged.
Or all such exchanges are considered to be within the scope of the invention as defined in the appended claims.
You will understand that.

For example, while the preferred embodiments shown in FIGS. 4 and 5 specifically mention the use of controlled buck converter circuits, those skilled in the art will appreciate that "buck converter circuits are known in the art." Can be replaced with any other controllable power supply. " Other power supplies, such as boost (boos
t) and buck-boost topologies and other similar circuit topologies. Such topologies may also be derived from frequency width modulation (FWM) circuits and / or other switching topologies.

Other variations are possible. For example, the diodes 50, 52, 54, 56 can be replaced equivalently with other reverse bias switches known in the art. The reverse bias switch includes, for example, a biased transistor circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a prior art power supply circuit topology.

FIG. 2 is a block diagram of another prior art power supply circuit topology.

FIG. 3 is a block diagram of a preferred embodiment of the power supply system of the present invention.

FIG. 4 is a detailed circuit diagram of the embodiment of FIG.

FIG. 5 is a detailed circuit diagram of another embodiment of the power supply system of the present invention.

FIG. 6 is a detailed circuit diagram of an example of a current-voltage multiplication circuit provided in the embodiment of FIG.

7 is a detailed circuit diagram of another example of the current-voltage multiplication circuit provided in the embodiment of FIG.

[Explanation of symbols]

10 ... Input power adapter 14 ... Battery charger 18 ... Battery 22 ... System DC / DC converter 24 ... Operating system 38 ... Pulse width modulator 82 ... Multiplier

Continuation of the front page (56) Reference JP-A-6-113477 (JP, A) JP-A-2-65630 (JP, A) JP-A-5-56566 (JP, A) JP-A-11-234915 (JP , A) Jitsukaihei 1-143254 (JP, U) US Patent 5734261 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02J 1/00 H02J ⁷ /00-7/36

Claims (28)

(57) [Claims] 1. A charger circuit for generating a duty cycle for delivering power to an operating system and a battery; a first feedback loop for sensing the total output current generated by the charger circuit; and the charger. A second feedback loop for sensing the current delivered by the circuit to the battery, the first feedback loop and the second feedback loop being an error circuit for generating an error signal to the charger circuit. And the charger circuit sends to the operating system and the battery.
The duty cycle for adjusting the total output current
To the first feedback loop or the second feedback loop.
The feedback loop generated in either one of the
An electric power supply system characterized by adjusting based on the value of an error signal . 2. The power supply system of claim 1, wherein the power supply system further comprises an input power source connected to the charger circuit. 3. The power supply system according to claim 1, wherein the charger circuit, the operating system, and the battery are connected in parallel. 4. The pulse circuit includes a pulse width modulator (PW) connected to the input power source.
M) circuit, wherein the PWM provides the duty cycle to adjust the input power source based on the error signal provided by the first feedback loop and the second feedback loop. The power supply system according to claim 2, wherein: 5. The first feedback loop includes a sensing register for sensing a total output current signal sent to the operating system, a first sense amplifier for amplifying the total output current signal, and a first sense amplifier. A first comparator for comparing the amplified total output current signal with a predetermined total output current threshold value to generate an error signal; and the first error signal flowing to the charger circuit. And a second switch for amplifying the current signal sent to the battery, the second feedback loop amplifying the current signal sent to the battery. A second sense amplifier for operating the amplified current signal sent to the battery to generate a second error signal. A second comparator for comparing with a current threshold value, and a second switch for allowing the second error signal to flow to the charger circuit, the first switch and the second switch. Is connected in parallel, and the largest signal of the first error signal and the second error signal is supplied to the charger circuit as the error signal, and the first switch and the second switch are connected. The power supply system of claim 1, wherein the power supply system is allowed to flow through. 6. The power supply system further comprises a third feedback loop, the third feedback loop comparing the battery voltage with a predetermined battery voltage threshold signal to generate a third error signal. A third comparator for permitting the third error signal to flow to the charger circuit, and the first switch, the second switch, and the third switch. Is connected in parallel, and the largest signal of the first error signal, the second error signal, and the third error signal is supplied to the charger circuit as the error signal. 6. The power supply system according to claim 5, wherein the power supply system is allowed to flow through the second switch and the third switch. 7. The power supply system receives the output current sent by the charger circuit and sends dc− to send power to the operating system.
The power supply system according to claim 1, further comprising a dc converter circuit. 8. The power supply system according to claim 1, wherein the power supply system further comprises a reverse current limiting circuit for limiting a current flowing from the battery to the charger circuit. 9. The power supply system of claim 8, wherein the reverse current limiting circuit comprises a diode having a forward bias in the direction of the total output current. 10. The reverse current limiting circuit is a transistor and a comparator connected to an input line and an output line of the transistor, and generates a control signal connected to a control line of the transistor. And a voltage source for biasing the transistor to a positive state, the transistor conducting when current flows from the input to the output. Supply system. 11. The power supply system of claim 5, wherein the predetermined total output current threshold value and the predetermined battery voltage threshold signal are generated by a programmable circuit. 12. The predetermined total output current threshold value and the predetermined battery voltage threshold signal are generated by a voltage divider circuit that divides the total output voltage and the voltage in the battery. The power supply system according to claim 6. 13. The power supply system further comprises: a power limit feedback loop, the power limit feedback loop for multiplying the total output current with a total output voltage to produce a total output power signal. A multiplier circuit; a power comparator for comparing the total output power signal with a predetermined power output threshold signal to generate a power output error signal; and the power output error signal to the charger circuit. A power switch for permitting flow, the first switch, the second switch, and the power switch are connected in parallel, the first error signal, the second error signal, and the power error The largest signal of the signals is the error signal supplied to the charger circuit and is the first switch and the second switch. Power supply system according to claim 5, characterized in that it is allowed to flow through the said power switch and. 14. The multiplier circuit has a transconductance amplifier for producing a total current signal, the duty cycle as a control line input from the charger circuit, and is proportional to the total output power. A transistor for dividing the total output signal according to the duty cycle for multiplying the total output current by the output voltage to generate a power current signal; and an output voltage signal proportional to the total output power. 14. The power supply system according to claim 13, further comprising an integrating circuit for generating the electric power. 15. The power supply system according to claim 13, wherein the multiplier circuit comprises a differential amplifier circuit for generating an output voltage proportional to the total output power. 16. An input power source, a charger circuit for generating a duty cycle for controlling the input power source for delivering controlled power to an operating system and a battery, and a charger circuit. A first feedback loop that senses the total output current generated and generates a first error signal based on the total output current and a preset threshold total output current signal; and a current sent to the battery by the charger circuit. A second feedback loop that generates a second error signal based on the current sent to the battery and a preset threshold battery current signal; and a total output power generated by the charger circuit, A third error based on the total output power and the preset threshold total output power signal. A third feedback loop for generating a signal, wherein the charger circuit operates the operating system and the battery based on the value of the first error signal or the value of the second error signal or the value of the third error signal. A power supply system characterized by adjusting the duty cycle to adjust the total output current and the total output power delivered to the. 17. The fourth feedback that detects the voltage sent to the battery and generates a fourth error signal based on the voltage sent to the battery and a preset threshold battery voltage signal. Further comprising a loop, wherein the charger circuit operates based on the value of the first error signal or the value of the second error signal or the value of the third error signal or the value of the fourth error signal. 17. The power supply system of claim 16, wherein the duty cycle is adjusted to adjust the total output current and the total output power delivered to the battery. 18. The first feedback loop comprises a first comparator for comparing the total output current with the preset threshold total output current signal, and the second feedback loop is sent to the battery. A second comparator for comparing the current with the preset threshold battery current signal, the third feedback loop including a second comparator for comparing the total output power with the preset threshold total output power signal. A third comparator, wherein the first comparator generates a first error signal, the second comparator generates a second error signal, and the third comparator generates a third error signal. The power supply system according to claim 16, wherein the power supply system is a power supply system. 19. The first error signal, the second error signal, and the third error signal are supplied to a switch, and the switch has the first error signal, the second error signal, or the third error signal. The power supply system according to claim 16, wherein the power supply system conducts based on the largest signal among the signals. 20. The third feedback loop further comprises a multiplier circuit for multiplying the total output current and the total output voltage and generating a signal proportional to the total output power. The power supply system according to claim 18. 21. The charger circuit includes a pulse width modulator (PW) connected to the input power source.
M) circuit and comprising a pulse width modulator circuit for generating the duty cycle based on the first error signal or the second error signal or the third error signal. 16. The power supply system according to 16. 22. The power supply system further comprises a reverse current limiting circuit for limiting a current flowing from the battery to the charger circuit, wherein the reverse current limiting circuit includes a transistor and a transistor. A comparator connected to an input line and an output line and for generating a control signal connected to the control line of the transistor, and a voltage source for biasing the transistor to a positive state. 17. The power supply system of claim 16, comprising: and a transistor conducting when a current flows from the input to the output. 23. A method of regulating the current delivered by a charger circuit to an operating system and a battery, the method comprising: a first error based on a total output current of the charger circuit and a preset threshold total output current. Detecting a signal, detecting a second error signal based on a current sent to the battery by the charger circuit and a preset threshold battery current signal, and detecting the first error signal or the second error signal. Providing one of them as a feedback signal to the charger circuit and adjusting the current delivered by the charger circuit based on the first feedback error signal or the second feedback error signal. A method characterized by the following. 24. The method detects a third error signal based on the total output current and the total output voltage of the charger circuit, and the first error signal or the second error signal or the third error signal. Providing one of the error signals as a feedback signal to the charger circuit, and supplying the current and / or voltage delivered by the charger circuit to the first feedback error signal or the second feedback error signal or the 24. The method of claim 23, further comprising the step of adjusting based on the third feedback error signal. 25. The method detects a fourth error signal based on a voltage sent by the charger circuit to the battery and a preset threshold battery voltage signal, and the first error signal or the second error signal. A signal or one of the fourth error signals as a feedback signal to the charger circuit, and the current and / or voltage delivered by the charger circuit is the first feedback error signal or the second feedback. 24. The method of claim 23, further comprising adjusting based on an error signal or the fourth feedback error signal. 26. The method further comprises multiplying the total output current of the charger circuit by the total output voltage to generate the third error signal, wherein the third error signal is 25. The method of claim 24, wherein the method is proportional to the total output power of the charger circuit. 27. The method of claim 23, wherein the method further comprises limiting reverse current flow from the battery to the charger circuit. 28. The method comprises: amplifying the total output current and comparing the total output current with the preset threshold total output current signal to generate the first error signal; and Amplifying the current sent by the charger circuit to the battery to produce a two error signal;
24. The method of claim 23, further comprising the step of comparing the current delivered to the battery with the preset threshold battery current signal.