JP5070779B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device. More specifically, the present invention particularly relates to a method of manufacturing a semiconductor device having a silicon germanium (SiGe) layer embedded in a silicon substrate on both sides of a gate electrode as a source / drain. The present invention relates to a method and a semiconductor device.

  In a semiconductor device including a MOS transistor, a technique for improving carrier mobility by applying stress to a silicon substrate is actively used. As one of such techniques, for example, in a p-type MOS transistor (PMOS), a silicon germanium (SiGe) layer having a lattice constant larger than that of silicon (Si) is used as the source / drain (S / D) of the transistor. A method has been proposed in which strain is generated by epitaxial growth and locally applying stress to the channel region (see, for example, Non-Patent Documents 1 and 2 below). This method is used for the current 90 nm generation and 65 nm generation technologies and is being advanced to mass production. Furthermore, it is considered as an important technology in the technological development for the 45 nm generation and beyond.

  On the other hand, there is also a method that utilizes the fact that the hole mobility of the Si substrate with the plane orientation (110) is higher than the hole mobility of the Si substrate with the plane orientation (100) conventionally used. According to this method, the performance of the PMOS can be improved only by using a Si substrate with a different plane orientation.

  From the above, combining the method of applying local stress to the channel region with the SiGe layer and the method of using the Si substrate with the plane orientation (110) is considered promising for the next-generation high-performance PMOS. Is being considered.

  A method for manufacturing the semiconductor device having such a structure will be described with reference to the cross-sectional view of FIG. First, an element isolation region (not shown) is formed on the surface side of a silicon substrate 11 having a plane orientation (110), and hard masks 14 and 15 are sequentially stacked on the silicon substrate 11 with a gate insulating film 12 interposed therebetween. A gate electrode 13 is formed. Thereafter, sidewalls 17 are formed on these sidewalls via insulating offset spacers 16. Up to the above, the process is performed in the same manner as a normal MOS process.

  Next, using the hard mask 15 and the sidewall 17 as a mask, so-called recess etching is performed to dig the surface of the silicon substrate 11 by etching, thereby forming a recess region 18 ′. At this time, by performing isotropic recess etching, the recess region 18 ′ extends to the lower side of the sidewall 17. As a result, the side wall of the recess region 18 ′ on the gate electrode 13 side has a slope, and the plane orientation (100) plane is naturally exposed on this slope.

  After the above, although illustration is omitted here, an S / D is formed by epitaxially growing a SiGe layer on the surface of the recess region 18 'dug by etching.

T. Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, International Electron Devices Meeting Technical Digest, 2003, p.978 S. Tyagi et al., “An advanced low power, high performance, strained channel 65 nm technology”, International Electron Devices Meeting Technical Digest, 2005, p.1070

  However, in the method for manufacturing a semiconductor device as described above, as shown in the TEM photograph of FIG. 6A and the enlarged TEM photograph of region A in FIG. 6B, the side wall on the gate electrode 13 side of the recess region 18 ′. The rate of epitaxial growth of the SiGe layer 19 on the surface of the surface orientation (100) exposed to the surface is faster than the rate of epitaxial growth of the SiGe layer 19 on the surface of the surface orientation (110). For this reason, the SiGe layer 19 is preferentially grown on the plane of the plane orientation (100), and the SiGe layer 19 is difficult to grow on the bottom of the recess region 18 ′ that becomes the bottom of the active region. For this reason, there is a problem that it is difficult to apply stress from the lateral direction to the channel region Ch formed in the silicon substrate 11 immediately below the gate electrode 13.

  In order to solve the above-described problems, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that effectively apply stress to a channel region from the lateral direction.

In order to achieve the above-described object, the semiconductor device manufacturing method of the present invention is characterized by sequentially performing the following steps. First, in the first step, a step of forming a gate electrode on a silicon (Si) substrate via a gate insulating film is performed. Next, in the second step, the Si substrate is dug down by anisotropic recess etching using the gate electrode as a mask to form a first recess region. Next, in a third step, a first sidewall is formed on the silicon substrate on both sides of the gate electrode. Next, in a fourth step, the silicon substrate is dug down to form a second recess region by anisotropic recess etching using the gate electrode and the first sidewall as a mask. Next, in a fifth step, a step of epitaxially growing a first mixed crystal layer made of atoms having different lattice constants from Si and Si up to the same height as the bottom surface of the first recess region on the surface of the second recess region. I do. Next, in the sixth step, the first sidewall is removed. Next, in a seventh step, silicon and silicon are formed of atoms having different lattice constants on the first recess region and the first mixed crystal layer, and the concentration of the atoms is set higher than that of the first mixed crystal layer. The second mixed crystal layer having a high concentration is epitaxially grown so as to be higher than the surface of the silicon substrate.

According to such a method of manufacturing a semiconductor device, in the second step and the fourth step , the Si substrate is dug down by anisotropic recess etching using the gate electrode and the first sidewall as a mask, and the first recess region is formed. to form a or the second recess region, the side walls of the gate electrode side of the recess region is processed substantially vertically. For this reason, compared with the case where the side wall has a slope, the mixed crystal layer embedded in the first recess region or the second recess causes a lateral stress on the channel region formed in the Si substrate immediately below the gate electrode. Easy to apply. Even when a Si substrate having a plane orientation (110) is used, the side walls on the gate electrode side of the first recess region and the second recess region are processed substantially vertically, so that the plane with the plane orientation (100) Exposure is suppressed. Thus, the mixed crystal layer having a planarized surface can be formed by epitaxially growing the mixed crystal layer on the surface of the first recess region or the second recess region . Therefore, the stress from the lateral direction can be effectively applied to the channel region.

The semiconductor device of the present invention is a semiconductor device in which a gate electrode is provided on a Si substrate via a gate insulating film, and the gate electrode side wall is substantially vertical so that the side wall on the gate electrode side is substantially vertical. Among the recess regions formed by increasing the degree of digging in the order of the one recess region and the second recess region and digging into the silicon substrate on both sides of the gate electrode, the second recess region is the same as that of the first recess region. A first mixed crystal layer made of atoms having different lattice constants from silicon and silicon is provided up to the same height as the bottom surface, and silicon is formed on the first recess region and the first mixed crystal layer. the silicon and the second mixed crystal layer was higher concentration than the concentration of the atoms consists different from the atomic first recess region lattice constant is provided to a height above the surface of the silicon substrate and It is characterized.

According to such a semiconductor device, the side walls on the gate electrode side of the first recess region and the second recess region are processed substantially vertically. It is easy to apply stress from the direction. Therefore, stress from the lateral direction can be effectively applied to the channel region.

  As described above, according to the method for manufacturing a semiconductor device and the semiconductor device of the present invention, since the stress from the lateral direction can be effectively applied to the channel region, the carrier mobility can be increased. The performance and quality of the semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  An example of an embodiment relating to a method for manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process cross-sectional views of FIGS. In the present embodiment, the configuration of the semiconductor device will be described in the order of the manufacturing process. Further, the same components as those described in the background art will be described with the same numbers.

First, as shown in FIG. 1A, a Si substrate 11 having a plane orientation (110) made of single crystal silicon is prepared, and an element isolation region (not shown) is formed on the surface side. At this time, for example, a groove is formed on the surface side of the Si substrate 11, and an element isolation region having an STI (shallow trench isolation) structure in which an insulating film made of, for example, a silicon oxide (SiO ₂ ) film is embedded in the groove is formed. .

Next, a gate electrode 13 made of, for example, polysilicon is patterned on the Si substrate 11 separated in the element isolation region via a gate insulating film 12 made of, for example, SiO ₂ . At this time, in order to make the gate electrode 13 into a fine pattern, the two-layer hard masks 14 and 15 are used, and the gate insulating film 12, the gate electrode 13, and the hard masks 14 and 15 are formed on the silicon substrate 11. After each material film is laminated, these laminated films are subjected to pattern etching. The gate insulating film 12 and the gate electrode 13 are removed as a dummy in a later process.

  Next, insulating side walls 17a made of, for example, TEOS (Tetraethoky Silane) are provided on the side walls of the gate insulating film 12, the gate electrode 13, and the hard masks 14 and 15 through spacers 16 made of, for example, silicon nitride (SiN). Form.

  Next, by recess etching using the gate electrode 13 as a mask, the surface of the Si substrate 11 is dug down to form a recess region. Here, a characteristic configuration of the present invention is to perform anisotropic recess etching, and here, two-stage anisotropic recess etching is performed.

  First, the surface of the Si substrate 11 is dug down by anisotropic recess etching using the hard mask 15 and the sidewalls 17a as masks to form recess regions 18a having a depth of 50 nm or less. Thereby, the side wall of the recess region 18a on the gate electrode 13 side is processed substantially vertically.

Next, as shown in FIG. 1B, sidewalls 17b made of, for example, SiN are formed on the Si substrates 11 on both sides of the sidewalls 17a. Subsequently, by using the hard mask 15 and the sidewalls 17b as a mask, the surface of the Si substrate 11 is dug down by anisotropic recess etching, so that the recess region 18a is further dug down to form the recess region 18b. As a result, the side wall of the recess region 18a on the gate electrode 13 side is processed substantially vertically to form the recess region 18 that is dug in sequence with the recess regions 18a and 18b. At this time, the side wall of the recess region 18 on the gate electrode 13 side is formed with a level difference corresponding to the film thickness of the side wall 17b. The anisotropic recess etching is performed using an NF ₃ Based etching gas.

  As described above, the side walls on the gate electrode 13 side of the recess regions 18a and 18b formed by the two-step anisotropic recess etching are processed substantially vertically, which has been described with reference to FIG. 5 in the background art. Thus, compared with the case where the side wall of the recess region 18 ′ on the gate electrode 13 side has an inclined surface, the channel region formed in the Si substrate 11 immediately below the gate electrode 13 is formed by the SiGe layer embedded in the recess region 18. It becomes easy to apply stress from the lateral direction. Further, since the slope is not exposed on the side wall of the recess region 18 on the gate electrode 13 side, the exposure of the plane orientation (100) plane is suppressed, so that the SiGe layer is epitaxially grown at a substantially uniform rate, as will be described later. It becomes possible.

Here, the depth d ₁ of the recess region 18a is 5 nm or more and less than 50 nm (5 nm ≦ d ₁ <50 nm), and the depth d ₂ of the recess region 18 is d ₁ or more and less than 120 nm (d ₁ ≦ d ₂ <120 nm). Further, the width d ₃ of the shoulder portion of the step on the side wall of the recess region 18 on the gate electrode 13 side is formed to be smaller than 40 nm. This prevents a short channel effect due to the first SiGe layer embedded in the recess region 18b being too close, and applies a lateral stress to the channel region formed in the Si substrate 11 immediately below the gate electrode 13. It can be applied effectively.

  Here, the side wall forming step and the anisotropic recess etching step are repeated twice. However, the present invention is not limited to this, and the side wall is formed by only one anisotropic recess etching. A recess region 18 without a step may be formed, or the recess region may be formed so that a plurality of steps are formed on the side wall by repeating the above steps three or more times. However, considering the prevention of the short channel effect as described above, the effect of applying stress, and the improvement of throughput, it is most preferable to repeat the above steps twice.

  Here, an example in which the anisotropic recess etching is performed for the first time in a state where the sidewall 17a is provided will be described. However, even if the recess etching is performed without providing the sidewall 17a. The present invention is applicable. However, in this case, in order to prevent the deterioration of the short channel effect due to the diffusion of impurities, when the SiGe layer is epitaxially grown in the recess region 18 in a later step, the impurity ions are not included.

  Next, as shown in FIG. 1C, a mixed crystal layer of Si and Si having different lattice constants is epitaxially grown on the surface of the recess region 18b, that is, the surface of the Si substrate 11 dug down. Here, since a PMOSFET is formed, a compressive stress is applied to the channel region sandwiched between the mixed crystal layers, and therefore, a SiGe layer (mixed layer) composed of silicon (Si) and germanium (Ge) having a lattice constant larger than that of silicon. Crystal layer) is grown epitaxially. At this time, the SiGe layer is epitaxially grown with boron as an impurity.

  At this time, first, the first SiGe layer 19a is epitaxially grown in the recess region 18b dug down by the second recess etching. At this time, since the surface (100) plane is not exposed on the gate electrode 13 side of the recess region 18b, the recess region 18b is buried with the first SiGe layer 19a because it is epitaxially grown at an equal rate. The surface is formed flat.

The film formation conditions for the first SiGe layer 19 include germanium hydride (GeH ₄ ) diluted with dichlorosilane (DCS), hydrogen chloride (HCl), and hydrogen (H ₂ ) as a film formation gas. ), Diborane (B ₂ H ₆ ) diluted with hydrogen (H ₂ ), the processing temperature is set to 600 ° C. to 900 ° C., and the processing pressure is set to 1.3 kPa to 13.3 kPa.

  Next, as shown in FIG. 2D, the sidewall 17b (see FIG. 1C) is removed to expose the side wall of the recess region 18a.

  Subsequently, as shown in FIG. 2E, a second SiGe layer 19b is epitaxially grown on the exposed surface of the recess region 18a and the first SiGe layer 19a. At this time, the surface of the recess region 18a on the side of the gate electrode 13 is not exposed to the plane orientation (100), and therefore, the recess region 18a is epitaxially grown at a uniform rate. The surface is formed in a flat state. The film formation conditions for the second SiGe layer 19b can be the same as the film formation conditions for the first SiGe layer 19a. As a result, the recess region 18 is filled with the SiGe layer 19 (mixed crystal layer) composed of the first SiGe layer 19a and the second SiGe layer 19b.

Here, in order to effectively apply a lateral stress to the channel region, the surface of the second SiGe layer 19b may be formed to be higher than the surface of the silicon substrate 11 with a margin. The preferred height is 50 nm or less. For the same reason, it is preferable that the Ge concentration of the second SiGe layer 19b is higher than that of the first SiGe layer 19a. In this case, the GeH ₄ gas flow rate is made higher than the film formation conditions of the first SiGe layer 19a, and the Ge concentration of the second SiGe layer 19b is increased.

  Thereafter, the Si layer 20 is formed on the second SiGe layer 19b. A silicide layer is formed on the Si layer 20 as will be described later.

  Next, as shown in FIG. 2F, by using the hard mask 15 and the offset spacer 16 as a mask, for example, by introducing an n-type impurity from an oblique direction, the depletion layer is expanded and the p-type impurity ion is introduced. Then, extension regions (not shown) are formed on the surface of the Si substrate 11 on both sides of the gate electrode 13.

Thereafter, as shown in FIG. 3G, sidewalls 17c made of, for example, SiN are formed on both sides of the gate electrode 13 via offset spacers 16, and sidewalls made of, for example, SiO ₂ are formed on both sides of the sidewall 17c. 17d is formed. Here, the two-layer sidewalls 17c and 17d are stacked, but a single-layer sidewall may be formed. However, in this case, in order to reduce the capacitance between the wirings, it is preferable to form a sidewall made of SiO ₂ instead of SiN.

  Next, as shown in FIG. 3H, when the boron concentration introduced into the SiGe layer 19 is not sufficient, the hard mask 15 and the sidewalls 17d are used as a mask to form boron in the SiGe layer 19 and the Si layer 20. To form S / D. Next, the Si layer 20 on both sides of the sidewall 17d is silicided to form a silicide layer 21.

Subsequently, as shown in FIG. 3I, the hard mask 15 made of SiO ₂ (see FIG. 3H) is removed by a cleaning process, and the hard mask 14 is exposed. At this time, the upper portion of the sidewall 17d made of SiO ₂ is also removed.

Next, as shown in FIG. 4J, an interlayer insulating film 22 made of, for example, SiO ₂ is formed so as to cover the entire area on the Si substrate 11 by, eg, CVD. Subsequently, the interlayer insulating film 22 is flattened until the surface of the hard mask 14 is exposed, for example, by a chemical mechanical polishing (CMP) method.

  Next, by removing the hard mask 14 (see FIG. 4J), the surface of the gate electrode 13 made of polysilicon (see FIG. 4J) is exposed. At this time, the offset spacers 16 on both sides of the hard mask 14 and the upper portions of the sidewalls 17 c are removed together with the hard mask 14. Subsequently, the gate electrode 13 and the gate insulating film 12 (see FIG. 4J) are removed, and a recess 23 exposing the surface of the Si substrate 11 is formed.

Next, as shown in FIG. 4M, for example, hafnium oxide (HfO) is formed on the interlayer insulating film 22 by, for example, atomic layer deposition (ALD) while covering the inner wall of the recess 23. ₂ ) A gate insulating film 24 made of a high-k material such as ₁ ) is newly formed.

  Subsequently, for example, a polysilicon or metal gate electrode film is formed on the gate insulating film 24 in a state where the recess 23 is embedded, and then the gate electrode film is formed by CMP until the surface of the interlayer insulating film 22 is exposed. The gate electrode 25 is formed in the recess 23 with the gate insulating film 24 interposed therebetween. As a result, the Si substrate 11 immediately below the gate electrode 25 becomes the channel region Ch.

  According to such a method for manufacturing a semiconductor device and the semiconductor device obtained thereby, the recess region 18 is formed by digging down the Si substrate 11 having the plane orientation (110) by anisotropic recess etching to form the recess region 18. The side wall on the gate electrode 13 side is processed substantially vertically. For this reason, compared with the case where this side wall has a slope, the SiGe layer embedded in the recess region 18 makes it easier to apply a lateral stress to the channel region formed in the Si substrate 11 immediately below the gate electrode 13. Further, since the side wall on the gate electrode 13 side of the recess region 18 is processed substantially vertically, exposure of the surface with the surface orientation (100) is suppressed. Accordingly, the SiGe layer 19 having a planarized surface can be formed by epitaxially growing the SiGe layer 19 on the surface of the recess region 18. Therefore, it is possible to effectively apply stress from the lateral direction to the channel region Ch. Therefore, the hole mobility can be increased, so that the performance and quality of the semiconductor device can be improved.

  In addition, according to the method for manufacturing a semiconductor device of this embodiment, a step is formed on the side wall of the recess region 18 on the gate electrode 13 side by repeating the sidewall formation step and the anisotropic recess etching step twice. The Thereby, both the effect of prevention of a short channel effect and the effect of application of stress can be produced.

  In the above embodiment, the method for manufacturing the PMOSFET has been described as an example, but the present invention can also be applied as a method for manufacturing the NMOSFET. In this case, a SiC layer made of silicon and carbon (C) having a lattice constant smaller than that of silicon is epitaxially grown as a mixed crystal layer in which the recess region 18 is embedded using the Si substrate 11 having a plane orientation (100). Further, an n-type impurity is used as the impurity. As a result, tensile stress is applied to the channel region immediately below the gate electrode 25. Even in this case, since the sidewall of the recess region on the gate electrode side is processed substantially vertically by anisotropic recess etching, the same effect as in the above embodiment can be obtained.

It is manufacturing process sectional drawing (the 1) for demonstrating embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for demonstrating embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 3) for demonstrating embodiment which concerns on the manufacturing method of the semiconductor device of this invention. FIG. 6 is a manufacturing process cross-sectional view (No. 4) for describing the embodiment of the method of manufacturing the semiconductor device according to the invention; It is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. It is a photograph for demonstrating a problem in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12, 24 ... Gate insulating film, 13, 25 ... Gate electrode, 18, 18a, 18b ... Recess region, 19 ... SiGe layer (mixed crystal layer), 19a ... 1st SiGe layer, 19b ... 1st 2 SiGe layers, 22 ... interlayer insulating film

Claims (6)

A first step of forming a gate electrode on a silicon substrate via a gate insulating film;
A second step of forming a first recess region by digging down the silicon substrate by anisotropic recess etching using the gate electrode as a mask;
Forming a first sidewall on the silicon substrate on both sides of the gate electrode;
A fourth step of forming a second recess region by digging down the silicon substrate by anisotropic recess etching using the gate electrode and the first sidewall as a mask;
A fifth step of epitaxially growing a first mixed crystal layer comprising silicon and atoms having different lattice constants on the surface of the second recess region to the same height as the bottom surface of the first recess region;
A sixth step of removing the first sidewall;
On the first recess region and the first mixed crystal layer, silicon and silicon are atoms having different lattice constants, and the concentration of the atoms is higher than that of the first mixed crystal layer. And a seventh step of epitaxially growing the mixed crystal layer so as to be higher than the surface of the silicon substrate. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device is a p-type field effect transistor, and the first mixed crystal layer and the second mixed crystal layer are made of silicon and germanium. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the plane orientation of the silicon substrate is (110). In the manufacturing method of the semiconductor device according to claim 1,
Performing a step of forming second sidewalls on both sides of the gate electrode between the first step and the second step;
In the second step, anisotropic recess etching is performed using the gate electrode provided with the second sidewall as a mask,
In the third step, the first sidewall is formed on the silicon substrate on both sides of the second sidewall,
In the fourth step, the second recess region is formed by digging down the silicon substrate by anisotropic recess etching using the gate electrode and the first sidewall as a mask. Method. In the manufacturing method of the semiconductor device according to claim 1,
After the seventh step,
Forming an insulating film on the second mixed crystal layer so as to cover the gate electrode, and removing the insulating film until a surface of the gate electrode is exposed;
Removing the exposed gate electrode and the gate insulating film as a dummy to form a recess exposing the silicon substrate in the insulating film;
And a step of newly forming a gate electrode in the recess through a gate insulating film. A semiconductor device in which a gate electrode is provided on a silicon substrate via a gate insulating film,
Formed by digging into the silicon substrate on both sides of the gate electrode with increasing the degree of digging in order from the gate electrode side in the order of the first recess region and the second recess region so that the side wall on the gate electrode side is substantially vertical. Among the recess regions thus formed, the second recess region is provided with a first mixed crystal layer made of atoms having different lattice constants between silicon and silicon up to the same height as the bottom surface of the first recess region. On the first recess region and the first mixed crystal layer, silicon and silicon are atoms having different lattice constants, and the concentration of the atoms is higher than that of the first recess region. The mixed crystal layer is provided up to a height above the surface of the silicon substrate.