JPH0561444A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To display a video signal with high horizontal scan frequency with satisfactory picture quality on a liquid crystal display panel. CONSTITUTION:First and second line memory 18, 19 on which the video signal of one horizontal period is written alternately by a clock SSCK1 for write as one line of the liquid crystal display panel 1, first and second drivers 8A, 8B for horizontal scan to which the video signals at every third line read out from those line memory 18, 19 by a clock SSCK 2 for readout with the frequency of 1/2 the clock SSCK1 for write and time-expanded are inputted simultaneously, respectively, and a driver 9 for vertical scan which supplies the video signals at every third line sampled and held with the drivers 8A, 8B to the liquid crystal display panel 1 with an original horizontal cycle are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device which supplies a liquid crystal display panel with a non-interlace type video signal having a high horizontal scanning frequency and which is used in, for example, a personal computer.

[0002]

2. Description of the Related Art Conventionally, for example, a liquid crystal display device which reproduces a color image by synthesizing red, green, and blue lights modulated by respective liquid crystal display panels for red, green, and blue, and projecting the enlarged light on a screen ( The liquid crystal projector) has a signal output circuit configuration as shown in FIG. 5 (only the liquid crystal display panel for blue is shown here for convenience of description).
Reference numeral 1 denotes a TFT active matrix type liquid crystal display panel in which a plurality of pixels are arranged in a matrix in the horizontal and vertical directions. The liquid crystal display panel 1 transmits incident blue light to a video signal (in this case, blue among the three primary color signals). It acts as a light valve that modulates in response to a signal. FIG. 6 shows an equivalent circuit of the liquid crystal display panel 1, 2, 3, 4,
Reference numeral 5 denotes a plurality of column electrodes (source bus lines), row electrodes (gate bus lines), TFTs and pixel electrodes, which are formed in a matrix on the side of the first insulating substrate (not shown), and 6 is a second electrode which faces them. A common electrode formed on the side of an insulating substrate (not shown) is used to display each pixel composed of a liquid crystal layer interposed between the common electrode 6 and each pixel electrode 5.
The line-sequential scanning by each column electrode 2 and row electrode 3 is performed. Here, 7 is an auxiliary capacitor provided in parallel with each pixel, and the source of each TFT 4 is the column electrode 2
Side, the drain is connected to the pixel electrode 5 side, and the gate is connected to the row electrode 3 side. For example, when a scanning voltage is applied to the row electrode 3 of the first line, the first line connected to it is connected. Each TFT 4 is turned on, each column electrode 2 is connected to each pixel electrode 5 on the first line, and a signal voltage (that is, a video signal) is applied to each pixel on the first line. .. Therefore, it is possible to display a video signal for one field on the liquid crystal display panel 1 by repeating such an applying operation sequentially from the first line in a horizontal cycle for each line. Further, this applying operation is performed for each field. That is, the image is reproduced by repeating the vertical cycle.

For example, when the equivalent circuit for one pixel of the liquid crystal display panel 1 is viewed (see FIG. 7), the row electrode 3 has a TF.
The scanning voltage VG (for example, V
ON) is added in a predetermined section to bring it into a selected state, the signal voltage VS (for example, + v) of the column electrode 2 at that time is applied to the pixel through the TFT 4. Then, since the scanning voltage VG (for example, Voff) for sufficiently turning off the TFT 4 is applied to the next section row electrode 3, the signal voltage VS (+ v) is held by the capacitance of the liquid crystal. become. (See FIGS. 8A and 8B). Then, when the same pixel line is again selected in the next field, the polarity of the signal voltage VS of the row electrode 3 is inverted and, for example, -v, the signal voltage VS (-v) is applied to the pixel. Will be held similarly. Therefore, when this operation is repeated, it becomes the same as the case where the rectangular wave having the amplitude v is applied to the pixel as shown in FIG. Further, at this time, the electrode Vc of the common electrode 6 is set to the center voltage VD (DC) of this rectangular wave.
8D, the voltage applied to the liquid crystal becomes the rectangular wave voltage VLC having the effective value v as shown in FIG. 8D, and the liquid crystal display panel is appropriately driven (AC drive).

Reference numerals 8 and 9 denote horizontal and vertical scanning drivers for the liquid crystal display panel 1, and a horizontal scanning driver (source driver) 8 outputs a video signal to each column electrode 2 of the liquid crystal display panel 1 for vertical scanning driver. (Gate driver)
Reference numeral 9 is adapted to sequentially output a scanning voltage to each row electrode 3 of the liquid crystal display panel 1. Specifically, the horizontal scanning driver 8 is operated based on a horizontal cycle sampling start clock SPD which is a horizontal system clock, and the horizontal scanning driver 8 operates at a timing of the sampling clock CLD corresponding to the number of pixels in the horizontal direction of the liquid crystal display panel 1 for one horizontal period. The video signal is sampled and held within one horizontal period as one line of the liquid crystal display panel 1, and then output to each column electrode 2 of the liquid crystal display panel 1 via, for example, a buffer circuit. Then, the vertical scanning driver 9 is operated based on the vertical cycle capture start clock SPS which is a vertical system clock, and sequentially outputs the scan voltage to each row electrode 3 of the liquid crystal display panel 1 at the timing of the horizontal cycle capture clock CLS. Then, the video signal of one line unit from the horizontal scanning driver 8 is sequentially supplied (acquired) to each line of the liquid crystal display panel from the first line.

Reference numeral 10 is a video input terminal to which a video signal (in this case, three primary color signals of red, green and blue) is input, and 11 is a circuit for preventing application of a DC voltage component to the liquid crystal display panel 1 (that is, AC driving). In order to achieve this, the video interface circuit that inverts the polarity of the video signal input to the video input terminal 10 for each horizontal period and field based on the polarity inversion signal FRP and outputs the inverted signal, and 12 inverts the polarity from the video interface circuit 11 and outputs the inverted signal. Drive circuit for outputting the video signal (for blue) to a level required for driving the liquid crystal display panel 1 and outputting it to the horizontal scanning driver 8. Reference numerals 13 and 14 indicate horizontal and vertical synchronization signals HD and VD are input respectively to the horizontal direction. , A vertical synchronization input terminal, 15 is a horizontal clock (SP) required for driving control of the liquid crystal display panel 1 based on the horizontal and vertical synchronization signals HD and VD.
D, CLD), vertical system clocks (SPS, CLS), control clock CS1, polarity inversion signal FRP, and the like. Therefore, according to such a configuration, the video signal input to the input terminal 10 is first made to have a polarity and level suitable for driving the liquid crystal display panel 1, and then a horizontal scanning driver for one line of the liquid crystal display panel 1. At 8, the video signal in one horizontal period is sampled and held as one line, and the sampled and held video signal for one line is simultaneously supplied to all pixels in each line of the liquid crystal display panel. Will be displayed.

[0006]

However, when a non-interlace type video signal of a personal computer or the like is displayed on the liquid crystal display device having such a signal output circuit configuration, the horizontal signal is generated in one field (1/60 second). Number of scanning lines 480
Since the full-line display of the book is performed, the horizontal scanning frequency becomes high (in this case, 31.5 KHZ), which is about twice that of the normal NTSC video signal.
Therefore, as in the conventional configuration, the video signal for one horizontal period is sampled and held within one horizontal period by the horizontal scanning driver as one line of the liquid crystal display panel and then supplied to the liquid crystal display panel. Time is N
Since it becomes half of that in the case of displaying the TSC system video signal, that is, the charging time for the signal holding capacitor for each pixel in the horizontal scanning driver is halved and sufficient charging is performed. Therefore, there is a problem that the image quality is deteriorated. The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device capable of displaying a video signal having a high horizontal scanning frequency with good image quality.

[0007]

In order to achieve the above object, the present invention provides a liquid crystal display device in which a video signal having a high horizontal scanning frequency is sample-held and supplied to a liquid crystal display panel line by line for display. Means is provided for making the sample and hold time of the video signal for one line supplied to the display panel longer than the horizontal period. Specifically, the video signal is a non-interlaced video signal or a high-definition video signal, and the means writes a video signal for one horizontal period alternately as a line of the liquid crystal display panel at a predetermined writing clock. Line memory and a pair of horizontal scanning drivers to which the time-extended video signals of every two lines which are simultaneously read from both line memories with a read clock having a frequency of 1/2 of the write clock are inputted respectively. And a vertical scanning driver that supplies the video signal for every two lines sampled and held by the two horizontal scanning drivers to the liquid crystal display panel in the original horizontal cycle for each line.

[0008]

According to this structure, a video signal having a high horizontal scanning frequency is once converted into a parallel signal for every two lines whose horizontal period is doubled, and the sample and hold by the horizontal scanning driver is performed in the signal state. Since this is performed, the sampling frequency is reduced and a sufficient time for charging the signal holding capacitor of the signal voltage sampled for each pixel is obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A case in which a non-interlaced video signal of a personal computer is input will be described below with reference to the drawings as an embodiment of the present invention. The same parts as those of the conventional one are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, in order to make the sample hold time of the video signal for one line supplied to the liquid crystal display panel 1 longer than the horizontal period (31.75 μs) (in this case, doubled). 1 has a signal output circuit configuration as shown in FIG. That is, reference numeral 16 in FIG. 1 denotes a non-interlaced video signal (for blue) having a horizontal scanning frequency of 31.5 KHZ input to the video input terminal 10 at a frequency f.
A / D converter that converts from analog to digital by sampling with ck clock SSCK1 (for conversion),
Reference numeral 17 is a control clock CS1 from the control circuit 15.
Based on the upper switch 17A and the lower switch 17
A switch circuit in which B is alternately turned on in a horizontal cycle, 18,
Reference numeral 19 denotes a video signal for one horizontal period (31.75 μs) digitally converted by the A / D converter 16 as one line of the liquid crystal display panel 1 alternately written through the switch circuit 17, that is, a clock SSCK1 of frequency fck.
In the first and second line memories arranged in parallel for writing (for writing), the line memories 18 and 19 alternately write the video signal in one horizontal period at a frequency fc of 1/2.
The clocks SSCK2 (for reading) of k / 2 are time-extended and read simultaneously. For example, A
The video signals A, B, C, D ... In the horizontal period, which are continuously output from the / D converter 16, are alternately distributed to the first and second line memories 18 and 19 by the switch circuit 17 and sequentially written. For example, as shown in FIG. 2, when the video signal A of the first one horizontal period of one field is written in the first line memory 18, the video signal B of the next second one horizontal period is written in the second line memory 19. At the same time as the writing of the video signal C of the third horizontal period into the first line memory 18,
The reading of the video signals A and B for two lines previously written from 19 is started, and the third and fourth video signals C and D are started.
Is written, that is, as a parallel signal for every two lines whose horizontal period is doubled. Reference numerals 20 and 21 convert the parallel video signals for every two lines read from the first and second line memories 18 and 19 into the original analog at the timing of the clock (for conversion) of 1/2 frequency fck / 2. First and second D / A converters,
11A and 11B are polarity inversion signals FRP and / FRP (180 ° position shifts) so that the analog-converted video signals for every two lines are inverted on each line of the liquid crystal display panel 1 for each horizontal period and each field. The first and second video interface circuits 12A and 12B, which invert the polarities based on the FRP) and output, output the video signals for every two lines whose polarities have been inverted to a level required for driving the liquid crystal display panel, respectively. The first and second driving circuits 8A and 8B are arranged in parallel for two lines of the liquid crystal display panel 1 to which the video signals for every two lines from the first and second driving circuits 12A and 12B are simultaneously input. In the second horizontal scanning driver, the horizontal scanning drivers 8A and 8B each have a sampling start clock SPD having a horizontal period (31.75 μs × 2) that is twice as long as the original. Each is actuated simultaneously corresponding to the number of pixels in the horizontal direction of the liquid crystal display panel 1 on the basis of (in this case, 1/2 frequency fck) sampling clock CLD
At a timing of 1, the video signals for every two lines are sampled and held in a horizontal period twice as long as the original, and then output to the respective column electrodes 2 of the liquid crystal display panel 1 line by line alternately in the original horizontal period. ing. In this case, the control circuit 15 controls the horizontal system clock (SPD) necessary for controlling the drive of the liquid crystal display panel 1 based on the horizontal and vertical synchronization signals HD and VD.
1, CLD1, LP), vertical clock (SPS, CL
S), system clocks (SSCK1, SSCK)
2), polarity inversion signals FRP, / FRP, etc. are generated and output.

Therefore, in such a configuration, the non-interlace type video signal having a high horizontal scanning frequency input to the video input terminal 10 is temporarily transferred to the first and second line memories 1.
In 8 and 19, the horizontal period is converted into a parallel signal for every two lines which is doubled, and in the parallel signal state, every two lines by the first and second horizontal scanning drivers 8A and 8B. Since the sample hold is performed within the horizontal period twice that of the original, the sample hold time is doubled and the first and second horizontal scanning drivers 8 are
A sufficient charging time for the signal holding capacitor for each pixel in A and 8B will be secured, the sampling clock will be half the frequency, and unnecessary radiation will be suppressed. Incidentally, FIG. 3 shows a specific configuration of the first and second horizontal scanning drivers 8A and 8B.
B is a sampling start clock SPD1 having a horizontal cycle
Sampling clock CLD which is operated simultaneously based on
First and second analog memories that sample and hold video signals at the timing 1 respectively, that is, charge the signal holding capacitors for each pixel with the signal voltage at that time and sequentially output from left to right, The analog memory 22A,
22B each have a memory capacity for one line. When the analog memories 22A and 22B sample and hold one-line video signals, the reference numerals 23A and 23B have a horizontal cycle twice as long as the one-line video signals output from the analog memories 22A and 22B. Latch pulse L
A latch circuit that simultaneously latches by P, so that the latch outputs of the latch circuits 23A and 23B are alternately supplied to each column electrode 2 of the liquid crystal display panel 1 line by line via the switch circuit 24 in the original horizontal cycle. Is becoming Therefore, when the scanning voltage is sequentially output to each row electrode 3 of the liquid crystal display panel 1 by the vertical scanning driver 9, the video signals A, B, C, D, ... In one horizontal period are displayed on the first line of the liquid crystal display panel. It will be taken in sequentially with the second line. Here, without using the switch circuit 24, the latch outputs from the first and second latch circuits 23A and 23B may be alternately applied line by line as shown in FIG.
The case where the sample hold time is doubled has been described above, but the present invention is not limited to this. For example, three line memories and horizontal scanning drivers are arranged in parallel so that the sample hold time is tripled. You can The case of a non-interlaced video signal has been described, but the same applies to the case of a high-definition video signal with a high horizontal scanning frequency. Further, although the case of the liquid crystal projector has been described, for example, R, G, B three primary color signals are supplied to a single liquid crystal display panel provided with color filters having an R, G, B mosaic arrangement structure or a delta arrangement structure. The same applies to the case, and in the case of the delta arrangement structure, the sampling clocks of the horizontal scanning drivers are shifted according to the delta arrangement.

[0011]

As described above, according to the liquid crystal display device of the present invention, the sample hold time of the video signal for one line supplied to the liquid crystal display panel can be made longer than the horizontal period thereof. Especially, the sample and hold of the video signal with a high horizontal scanning frequency will be surely performed,
It is possible to display a high-quality image with good contrast. Since the frequency of the sampling clock can be reduced accordingly, adverse effects on the screen and the like due to unnecessary radiation of the sampling clock can also be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration example for realizing the present invention.

FIG. 2 is a diagram for explaining writing / reading to / from the line memory.

FIG. 3 is a diagram showing a specific configuration example of the horizontal scanning driver.

FIG. 4 is a diagram showing another configuration example.

FIG. 5 is a diagram showing a conventional circuit configuration example.

FIG. 6 is an equivalent circuit diagram of the liquid crystal display panel.

FIG. 7 is an equivalent circuit diagram of the one pixel.

FIG. 8 is a voltage waveform diagram for explaining the operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 8A, 8B Horizontal scanning driver 9 Vertical scanning driver 16 A / D converter 18, 19 First and second line memories 20, 21 First and second D / A converter

Claims (4)

[Claims] 1. A liquid crystal display device for sampling and holding a video signal having a high horizontal scanning frequency and supplying it to a liquid crystal display panel line by line to display the sampled video signal for one line supplied to the liquid crystal display panel. A liquid crystal display device, characterized in that means is provided for making the time longer than the horizontal period. 2. The liquid crystal display device according to claim 1, wherein the video signal is a non-interlaced video signal. 3. The liquid crystal display device according to claim 1, wherein the video signal is a high-definition video signal. 4. A pair of line memories in which a video signal for one horizontal period is alternately written at a predetermined writing clock as one line of a liquid crystal display panel, and the means for writing from one of these line memories is used as the writing clock. A pair of horizontal scanning drivers to which the time-extended video signals for every two lines are simultaneously read by the reading clock of the frequency of / 2, and sampled and held by the two horizontal scanning drivers. 2. The liquid crystal display device according to claim 1, further comprising a vertical scanning driver that supplies the video signal for each line to the liquid crystal display panel for each line in the original horizontal cycle.