JPH0646096A - Digital demodulator - Google Patents

Abstract

PURPOSE:To make the size small and to reduce the power consumption by configuring an orthogonal detector with small sized digital circuits only and to eliminate the need for an analog IF circuit. CONSTITUTION:This demodulator is provided with an A/D converter circuit 102 converting a modulation wave signal into digital data, weighting memories 105,108 weighting an output of the A/D converter circuit 102, and a moving mean type digital filter means receiving the digital signal outputted from the weighting memories 105,108 and two systems of independent weighting memories and moving mean type digital filter means are provided, the one system outputs an I component modulation signal and the other system outputs a Q component modulation signal. Then nodes of the digital filter means are set to undesired portions of the signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator.

[0002]

2. Description of the Related Art Conventionally, in a digital communication device, a carrier signal is modulated by a digital information signal (baseband signal) in order to improve transmission efficiency.
Information signals are being transmitted. As such a modulation method, an amplitude modulation method (A in which the amplitude of a carrier signal is changed according to a digital baseband signal (modulation signal))
SK: Amplitude Shift Keyin
g), a frequency modulation method (FSK: Frequency Shift) that shifts the frequency of the carrier wave according to the modulation signal.
t Keying), a phase modulation method (PSK: Phase Shi) that changes the phase of a carrier wave according to a modulation signal.
ft Keying), a quadrature amplitude modulation method (QAM: Quadrature Amplitude) that independently changes the amplitude and phase of a carrier wave according to a modulation signal.
e Modulation) and various other methods are used.

The carrier signal (modulation wave signal) S (t) thus modulated by the modulation signal can be generally expressed as follows.

[0004]

[Equation 1]

As is clear from the above equation, the modulated wave signal can be represented by the sum of two orthogonal components, and the baseband signal can be demodulated by a demodulation circuit such as a quadrature detector. The first term in the above equation is generally referred to as a quadrature phase (Q phase) component of the modulated wave signal, and the second term is generally referred to as an in-phase (I phase) component of the modulated wave signal.

A conventional circuit for demodulating such a modulated wave signal will be described with reference to FIG. In FIG. 2, 1 is an input terminal to which a received signal is supplied, 2 is a distributor for distributing the received signal supplied from the input terminal 1, 3 is a carrier signal generating circuit for generating a carrier signal, and 4 is a distributor 2. A mixer for multiplying the received signal distributed by the carrier signal generator circuit 3 with the received signal distributed by the distributor 2 and a π / 2 phase shift circuit by the π / 2 phase shift circuit 6. A second mixer for multiplying the generated carrier signal, 7 is a first filter for removing an unnecessary portion of the output from the first mixer 4, and 8 is a first filter for removing an unnecessary portion of the output from the second mixer 5. 2 filters, 9 is a first analog / digital conversion circuit that converts the output from the first filter 7 into a digital signal, and 10 is a second analog-digital conversion circuit that converts the output from the second filter 8 into a digital signal
It is an analog / digital conversion circuit.

The received signal (modulated wave signal) input to the input terminal 1 is distributed by the distributor 2 and then supplied to the first mixer 4 and the second mixer 5. The first mixer 4 multiplies the received signal by the carrier signal from the carrier signal generation circuit 3 to extract an in-phase component (I-phase component). Of the output, unnecessary portions are extracted by the first filter 7. To be removed. The second mixer 5 multiplies the received signal and the carrier signal having a π / 2 phase shift to extract a quadrature phase component (Q phase component), and an unnecessary portion of the output is fed to the second filter 8. Be removed.
The signals thus extracted are converted into digital signals and then supplied to the subsequent circuit. FIG. 3 shows the input / output state of the mixer.

[0008]

The above-mentioned conventional analog quadrature detector is not easy to be integrated into an IC because it is composed of analog elements such as a mixer, a phase shift circuit and a filter.
Further, even if it can be integrated into an IC, it is technically and economically very difficult to put it in one IC together with a signal processing unit composed of a digital circuit connected to the subsequent stage. Furthermore, since two analog / digital conversion circuits with large power consumption are used, there is a problem in that it is not suitable for devices such as portable devices that use a battery as a power source in terms of power consumption.

Further, in the conventional quadrature detector, when an unnecessary component in a band close to a required signal component such as an adjacent channel signal component or an adjacent channel signal component is removed by a filter, a high-order with sharp frequency characteristics is obtained. You need a filter,
It is difficult to realize such a filter, and even if it can be realized, it is difficult to reduce the size.
It is an object of the present invention to configure a quadrature detector only with a small-scale digital circuit, to achieve miniaturization and low power consumption.
It is another object of the present invention to configure a demodulator that can easily remove an unnecessary component in a band close to a required signal component such as an adjacent channel signal component.

[0010]

In view of the above problems, the present invention has an analog / digital conversion means for converting a modulated wave signal into digital data, and a weighting means for weighting the output of the analog / digital conversion means. A digital demodulator comprising: a shift register section for inputting a digital signal output from the weighting section; and a moving average type digital filter section comprising an addition section.

According to the present invention, each of the weighting means and the moving average type digital filter means has two systems, and one system outputs a modulation signal of an in-phase component (I component) and the other system. Is a quadrature component (Q component) modulated signal. Further, according to the present invention, the weighting means is configured to alternately perform weighting of two systems, and further comprises selection means for alternately distributing the output of the weighting means to the two moving average type digital filter means. In this digital demodulator, one system outputs a modulated signal of an in-phase component (I component) and the other system outputs a modulated signal of a quadrature component (Q component).

Further, in the present invention, the analog / digital conversion means converts the modulated wave signal into the center frequency N of the modulated wave signal.
It is converted into digital data at a frequency of (an integer greater than or equal to 2) times and inputted to the weighting means of two systems, and each of the weighting means has an amplitude value obtained by equally dividing a sine wave in one system or The value is weighted with a value that is multiplied by a constant, and the other system is weighted with an amplitude value when the sine wave that is out of phase with the one system by π / 2 is divided into N equal parts or a value that is a constant multiple of the value. , The number of data added to each output is KN / 2
(K is a natural number) are input to the moving average type digital filter means, and the I component modulated signal and Q
It is a digital demodulator characterized by obtaining a component modulated signal.

Further, according to the present invention, the analog / digital converting means converts the modulated wave signal into the center frequency N of the modulated wave signal.
It is converted into digital data at a frequency of (an integer greater than or equal to 2) times, input to one weighting means, the weighting means alternately weights two systems, and in one system, the sine wave is divided into N equal parts. The time amplitude value or a value obtained by multiplying the value by a constant is used for weighting, and in the other system, π /
A sine wave whose phase is shifted by 2 is divided into N equal parts or weighted with a value obtained by multiplying the value by a constant, and each output is selected so that the number of added data is K · N / 2 (K is a natural number). ) Are input to the moving average type digital filter means to obtain an I component modulation signal and a Q component modulation signal from two sequences.

Further, according to the present invention, the analog / digital converting means changes the modulated wave signal to 2 times the center frequency of the modulated wave signal.
It is converted into digital data at a frequency equal to or less than twice, and input to the weighting means of two systems, and each of the weighting means equally divides a sine wave into 2 · M / K (both M and K are natural numbers) in one system. The amplitude value at the time is weighted with a value obtained by multiplying the value by a constant, and in the other system, the amplitude value when the sine wave whose phase is shifted from the one system by π / 2 is divided by 2 · M / K or The values are weighted by a constant multiple, and the respective outputs are input to the moving average type digital filter means in which the number of added data is M, and the I-component modulated signal and the Q-component modulated signal from the two series are obtained. It is a digital demodulator characterized by being obtained.

Further, according to the present invention, the analog / digital converting means changes the modulated wave signal to 2 times the center frequency of the modulated wave signal.
It is converted into digital data at a frequency equal to or less than twice and inputted to one weighting means, and the weighting means alternately weights two systems, and one system outputs a sine wave of 2 · M.
/ K (both M and K are natural numbers) or weighted with a value obtained by multiplying the amplitude value by a constant multiple, and in the other system, a sine wave whose phase is shifted by π / 2 from the one system is 2 · M / K
The weighted value is divided by the amplitude value at the time of equal division or a value obtained by multiplying the value by a constant, and each output is selected and input to the moving average type digital filter means in which the number of added data is M. The digital demodulator is characterized by obtaining an I component modulated signal and a Q component modulated signal.

Furthermore, according to the present invention, the sampling frequency of the analog / digital converting means is 2 · M, which is the center frequency of the modulated wave signal sampled and frequency-converted.
It is a digital demodulator characterized by being / K times.
The present invention also provides a demodulator for demodulating a modulated signal,
Addition data including sampling means for sampling the demodulated signal at a frequency L (an integer of 2 or more) times the frequency of the channel interval, and a shift register portion and an addition portion to which a digital signal is input from the sampling means. The digital demodulator is characterized by comprising a moving average type digital filter means whose number is J · L (J is a natural number).

[0017]

According to the present invention, a modulated wave signal is converted into digital data, the digital data is weighted, and the weighted data is input to a moving average type digital filter whose filter characteristic section corresponds to an unnecessary portion of the data. I decided to do it. In addition, weighting is performed on two systems so that the signals are input to two systems of moving average type digital filters, and the in-phase component (I component) is output from one and the quadrature component (Q
Component) is output.

[0018]

1 is a block diagram showing a first embodiment of the present invention, in which 101 is an input terminal to which a modulated wave signal is supplied, and 102.
Is an analog / digital conversion circuit that converts the modulated wave signal supplied from the input terminal 101 into a digital signal, and 103 performs counting based on a clock signal having the same frequency as the sampling frequency, and the counted value represents one cycle of a sine wave. It is a counter that is reset when it reaches a value, and is a means for outputting phase information of a sine wave. 104 is a clock signal generator for generating a clock signal having the same frequency as the sampling frequency, and 105 is the analog / digital conversion circuit 1.
The output signal from 02 is supplied as the upper address, and the sine wave phase information from the counter 103 is supplied as the lower address, and the data obtained by multiplying the sine wave by the modulated wave signal sampled based on the specified address (that is, the counter). Value obtained by multiplying the amplitude of the sine wave in the phase supplied from 103 and the amplitude of the sampled modulation wave signal)
A first memory for weighting for deriving a shift register 106, a shift register constituting a moving average type digital filter for shifting and delaying data, and 107 a shift register 1
Adder forming a moving average type digital filter for adding and outputting data from 06, and 108 is an analog / analog
The output signal from the digital conversion circuit 102 is supplied as an upper address, and the sine wave phase information from the counter 103 is supplied as a lower address. The modulated wave signal sampled based on the specified address and the first memory 105 are supplied.
Second memory for weighting which derives the data obtained by multiplying the sine wave of the above and the sine wave whose phase is shifted by π / 2, 109 is a shift register for delaying the data from the second memory 108, and 110 is from the shift register 109. Is an adder that adds and outputs the data.

Next, the operation will be described. First, consider the case where the sampling frequency is set to be twice the input signal or more. First, a process (multiplication process) up to multiplication of a modulated wave signal and a sine wave signal having the same frequency as the center frequency of the modulated wave signal will be described. FIG. 4 is a concept of the multiplication processing unit of the digital demodulator according to the present invention. In FIG. 4, A indicates the configuration of the multiplication processing unit of the conventional analog quadrature detector.
In this case, the multiplication signal is a digital signal (I component is MI, Q
Two analog / digital conversion circuits are used after the mixer in order to convert the components into MQ. B of FIG.
Is a circuit in which the circuit of A is replaced with a digital circuit,
A digital multiplier is used instead of the mixer, and a sine wave data generation circuit is used instead of the analog oscillator.
In this configuration, since it is necessary to input a digital signal to the multiplier, the modulation signal is directly converted into a digital signal by the analog / digital conversion circuit. 4B is the same as the digital signal obtained from the analog / digital conversion circuit of FIG. 4A, since the processing of A is only replaced by digital processing.

At this time, the output of the sine wave data generation circuit becomes data as shown in FIG. FIG. 5 shows an example in which the sampling frequency of the analog / digital conversion circuit of FIG. 4B is assumed to be four times the center frequency of the modulated wave signal. Since the sine wave data generation circuit generates the digital signal at the same timing as when the modulation wave signal is converted into the digital signal in the analog / digital conversion circuit, it represents the sine wave of the center frequency of the modulation wave signal. The digital signal is output at that interval. In other words, if the sampling frequency of the analog / digital conversion circuit is N times the modulation wave signal (referred to as N times oversampling), the sine wave data generation circuit can output the amplitude values at the points where the sine wave is divided into N sequentially. Good. In the example of FIG. 5, the amplitude value at the point where the sine wave is divided into four is output. The amplitude value of the sine wave may be arbitrarily set so that the data has a simple value. When the sine wave data is given to the multiplier 1 and the multiplier 2, it is necessary to change the phase by π / 2. For this reason, when generating sine wave data, two systems with π / 2 different phases are independently generated,
Give to each multiplier. C in FIG. 4 is obtained by replacing the multiplier and the sine wave data generation circuit with a weighting circuit, and the weighting factors are a1 to a4 and b1 to b4 in FIG. in this way,
The multiplication process can be configured by one analog / digital conversion circuit and a weighting circuit.

The operation of the actual weighting circuit will be described with reference to FIG. The input signal input from the input terminal 101 is converted into a digital signal by the analog / digital conversion circuit 102 at a sampling frequency N times as high as the input signal, and then supplied as an upper address of the first memory 105 and the second memory 108. It Further, the lower address of the first memory 105 and the second memory 108 is supplied with the phase information of the sine wave counted in the cycle of the sampling frequency.

The first memory 105 and the second memory 108 have different configurations, for example, as shown in FIG. Note that FIG. 6 shows data when the counter 103 counts a sine wave into four equal parts (that is, when N is 4), and digital data A indicating a received signal.
It goes without saying that if is n bits, it has 2 ⁿ different values.

Now, the value of the counter 103 is 2 in decimal.
Assuming that the output data from the analog / digital conversion circuit 102 at that time is A, the digital data A (upper address) and the count value of the counter 103 “10” (lower The data (A × a3) stored corresponding to the address is derived from the first memory. On the other hand, this address is also supplied to the second memory, and the multiplication value (A ×) of the amplitude value of the sine wave whose phase is shifted by π / 2 from the sine wave of the first memory and the digital data A.
b3) is derived from the second memory. Thus, the multiplication process is performed by the weighting circuit.

Next, the filter processing will be described. In the present invention, a digital filter as shown in FIG. 7A is used as the low pass filter instead of the conventional analog filter. This filter is composed of a shift register that shifts data and an adder that adds the output of each stage of the shift register. Transfers new data one after another in the shift register, The result of addition is output as the output of the filter.
In the embodiment of FIG. 1, the shift registers 106 and 109 and the adders 107 and 110 correspond to this. The result of this addition is
Since it is an average value of M data, it is also called a moving average. The frequency characteristic of such a moving average type digital filter is shown in B of FIG. When the number of addition data of the digital filter is M, the point where the attenuation becomes ∞ (infinity) every ft / M (ft: transfer frequency of shift register) (that is,
Section) is possible. For example, in this embodiment, since the transfer frequency ft of the shift register is the sampling frequency fs, it is possible to make a section every fs / M.

FIG. 8 shows a state in which the data obtained by the above-described multiplication processing is input to this filter. In this example, since the sampling frequency fs is four times as high as the input signal, an unnecessary component of the multiplied data is generated at a half of the sampling frequency as shown in A of FIG. Since this overlaps with the node of the moving average type digital filter when M = 4 = N, when the multiplication data is input to the digital filter, the unnecessary component can be attenuated to a level where there is no practical problem. Generally, when the input signal is sampled at a frequency of N times and the multiplication processing is performed, the unnecessary component is 2
-It occurs at the position of fs / N. Therefore, in order to remove this with a moving average type digital filter, as shown in FIG. 9, it suffices to use a digital filter having addition data of an integer K times N / 2. The description so far has been made on the assumption that N = 4 and M = 2 · N / 2 = 4.

The weighting factor is a1, as shown in FIG.
a2, b1, b4 are 1 and a3, a4, b2, b3
In the case of dividing a sine wave having -1 into four equal parts as described above, the sign circuit is used to invert the positive and negative depending on the value of the counter as shown in FIG. Can also be configured. Further, although the moving average type is used for the digital filter, when the characteristic of the filter is arbitrary, it is sufficient to multiply the constant of the filter before inputting it from the shift register to the adder as shown in FIG.

As described above, according to the present invention, the quadrature detector can be constituted by digital circuits such as an analog / digital conversion circuit, a shift register, an adder and a memory, and in particular, 4
When performing double oversampling, a coding circuit may be used instead of the memory. Up to now, the description has been given assuming that the sampling frequency is at least twice the input signal, but next, the case where the input signal is sampled at a frequency not more than twice the input signal (hereinafter referred to as subsampling) will be described. Generally, when sampling an analog signal, when the sampled digital signal is represented on the frequency axis, all components are folded back in a frequency range of 0 to fs / 2 (fs: sampling frequency) as shown in FIG. Here, the sampling frequency is 2 times the center frequency of the input signal.
Since it is less than double, the center frequency of the input signal becomes fs / 2 or more. As an example, the frequency range of the input signal is N '.
It is assumed that the range is from fs to N ′ · fs + fs / 2 (N ′ is a natural number). In this case, the input signal has a frequency different from that before being sampled by being folded back within 0 to fs / 2 as shown in FIG. If the center frequency of the input signal is fω (fω ≧ fs / 2) and the center frequency of the sub-sampled signal is fa,

[0028]

[Equation 2]

It becomes That is, the sampled digital signal becomes a modulated wave signal whose center frequency is fa (called aliasing). Since the frequency of the frequency-modulated modulated wave signal is fs / 2 or less, it can be handled in the same manner as in the case described above.

Now, assuming that the modulated wave signal is input to an apparatus having the same configuration as that of FIG. 1 in which the added data is M digital filters, the unnecessary components of the signal are attenuated, as shown in FIG. The node may be set to match 2fa (the center frequency of the unnecessary component after the multiplication process). The Kth digital filter (in FIG. 13,
K = 1,2,4) is the same as 2fa.

[0031]

[Equation 3]

It is sufficient to satisfy Therefore, from Equation 2

[0033]

[Equation 4]

The relationship is as follows. Furthermore, in order to perform the multiplication process according to Equation 3, weighting may be performed with the amplitude value obtained by equally dividing the sine wave into 2 · M / K. Also, when N '= 0,
It corresponds to the above description. Here, when the relationship between the case of N times oversampling and the case of sampling at a frequency equal to or lower than twice the input signal is summarized, the former and the latter have the same device configuration, and the relationship between the sampling frequency and the modulation signal frequency is The only difference is the way the sine wave is divided into equal parts for weighting.

Now, as an example of sampling at a frequency not more than twice the frequency of the input signal, the frequency of the input modulated wave signal is 90.45 MHz (fω = 90.45 × 1).
0 ⁶ ) and the sampling frequency is 1.8 MHz (fs =
Consider the case of 1.8 × 10 ⁶ ). At this time,

[0036]

[Equation 5]

And N '= 50. Further, the modulated wave signal is 90.45-1.8 × 50 as shown in FIG.
= 0.45 MHz. 1.8 / 0.45 = 2
Since M / K = 4, the converted modulated wave signal hits the position of ¼ of the sampling frequency. Further, the multiplication process causes an unnecessary component to occur at a position of 1/2 the sampling frequency. Since 2 · M / K = 4, when the number of added data of the digital filter is M = 4, K = 2.

Thus, although the digital demodulator according to the present invention is realized, there is a method in which one weighting memory (or code circuit) is used as shown in FIG. In this case, in the weighting memory 26, as shown in FIG. 16, for one digital data A, the amplitude value of one sine wave and the other π / 2.
The amplitude values of the sine waves that are out of phase are alternated. In FIG. 15, reference numeral 21 is an input terminal, 22 is an analog / digital conversion circuit, and 23 is a counter that is reset by twice the number obtained by equally dividing a sine wave. Reference numeral 24 is a clock signal generator, 25 is a driver circuit for doubling the clock signal of the clock signal generator 24, 26 is a weighting memory, and 27 is a weighting memory 26.
A selector for allocating the output of I to the I component and the Q component, 28
Is a shift register, and 29 is an adder.

First, the analog / digital conversion circuit 22 converts the input signal into a digital signal by the clock signal of the clock signal generator 24. The counter 23 is counted twice by the driver circuit 25 in one clock, and the weighting memory 26 alternately outputs two systems as shown in FIG. Then, the selector 27 outputs 2 of the weighting memory 26.
The output of the system is alternately distributed to the I component and the Q component, and the operation is realized by one weighting circuit. The shift register outputs the I component and the Q component in synchronization.

Next, FIG. 17 shows a second embodiment. The second embodiment shows a demodulator having a configuration capable of easily removing unnecessary components such as adjacent channel signal components and adjacent channel signal components which appear at frequencies with channel intervals. When demodulation is performed by the circuit having the configuration shown in the conventional example, the signal components of the adjacent channel and the adjacent channel may appear as unnecessary components in the demodulated signal. This state is shown in A of FIG. in this case,
When trying to remove this unnecessary component, a steep filter is required, which is difficult to realize. Therefore, the nodes of the moving average type digital filter are made to correspond to unnecessary components. The number of added data of the moving average type digital filter is M, and it is set so that f _ch = J · fs / M as shown in B of FIG. Since the sampling frequency fs is set to L (integer of 2 or more) times the frequency f _ch of the channel interval, the number of addition data of the moving average type digital filter is M.
= J · L. Thus, a demodulator that can easily remove the unnecessary component of the adjacent channel signal can be configured.

The received signal (modulated wave signal) input to the input terminal 1 is distributed by the distributor 2 and then supplied to the first mixer 4 and the second mixer 5. The first mixer 4 multiplies the received signal and the carrier signal from the carrier signal generation circuit 3 to extract an in-phase component (I-phase component), and extracts an unnecessary component in a band apart from the modulated signal from the output. It is removed by the 1 low-pass filter 33. The first low-pass filter 33 does not remove unnecessary components in the band near the modulation signal, such as adjacent channel signal components. The output of the first low-pass filter 33 is sampled at a frequency L times (an integer of 2 or more) the channel interval frequency and converted into digital data by the first analog / digital conversion circuit. This digital data output has a transfer frequency that is the same as the sampling frequency and is input to a moving average type digital filter with J.L. Unnecessary components are removed. The second mixer 5 multiplies the received signal and the carrier signal with a π / 2 phase shift to obtain a quadrature phase component (Q phase component).
Of the output, and unnecessary portions are removed by the second low-pass filter 34 and the moving average type digital filter as described above. The signal thus extracted is supplied to the subsequent circuit.

Next, a third embodiment, which is a combination of the first and second embodiments, will be described. The first embodiment has a configuration in which an unnecessary component appearing at a frequency twice the center frequency of the modulated wave signal during the multiplication processing is removed. In the second embodiment,
The configuration was such that unnecessary components appearing in adjacent channels, adjacent channels, etc. were removed. In the third embodiment, these two configurations are combined to form a digital demodulator that simultaneously removes an unnecessary component that appears at a frequency twice the center frequency of the modulated wave signal and an unnecessary component that appears in an adjacent channel. .

The structure of the demodulator is the same as that of the first embodiment as shown in FIGS. First, consider the case where the sampling frequency is set to be twice the input signal or more.
The input signal input from the input terminal 101 is N of the input signal.
After being converted into a digital signal by the analog / digital conversion circuit 102 at a sampling frequency that is doubled and L times the channel interval frequency, it is supplied as an upper address of the first memory 105 and the second memory 108. Further, in the lower addresses of the first memory 105 and the second memory 108,
The phase information of the sine wave counted in the cycle of the sampling frequency is supplied, and the multiplication processing as described above is performed. The outputs obtained by the multiplication process are transferred to the shift registers 106, 10
9 and adders 107 and 110 to each moving average type digital filter. In the moving average type digital filter, when the number of added data is M, as described in the section, fs /
Can be placed every M. If we try to match this node to the adjacent channel signal component, the J-th node should come to fs / L.

[0044]

[Equation 6]

Is set. 2 of the center frequency of the modulated wave signal
If you try to match a node with an unnecessary component of double frequency,

[0046]

[Equation 7]

The relationship must be From equation 6, M = J · L, so if this is substituted into equation 7,

[0048]

[Equation 8]

Therefore, if the relationship between the moving average type digital filter and the sampling frequency is set as in the above equation, the unnecessary component of the frequency twice the center frequency of the modulated wave signal, the adjacent channel and the adjacent channel signal are unnecessary. The components can be removed at the same time. This state is shown in FIG.

Next, consider the case where the sampling frequency is set to be twice the center frequency of the input signal or less. As described above, when an analog signal is sampled, when the sampled digital signal is represented on the frequency axis, all components are folded back in the frequency range of 0 to fs / 2 as shown in FIG. Since the sampling frequency is not more than twice the center frequency of the input signal, the center frequency of the input signal is fs / 2 or more. Here, the frequency range of the input signal is from N ′ · fs to N ′ · fs + fs / 2.
(N 'is a natural number). In order to bring the node of the moving average type digital filter to the adjacent channel signal component, as described above, fs / L = J · f
It may be s / M. Further, in order to remove the unnecessary component after the multiplication process, the formula 3 may be satisfied. Therefore,

[0051]

[Equation 9]

With the structure satisfying the above condition, it is possible to remove the unnecessary component of the frequency twice the center frequency of the sampled modulated wave signal and the unnecessary components of the adjacent channel signal and the adjacent channel signal. This state is shown in FIG. Thus, the operation according to the present invention is achieved. In the present embodiment, the present invention is configured by hardware, but it goes without saying that it can be realized by replacing a part of the hardware with software.
Furthermore, it should be added that this embodiment can be modified as necessary.

[0053]

According to the present invention, a modulated wave signal is converted into digital data, the digital data is weighted,
Since the weighted data is input to a moving average type digital filter whose filter characteristic section corresponds to an unnecessary part of the data and demodulated, the quadrature detector can be configured with only a small digital circuit, so the signal processing unit The device including the device can be realized by one IC, and the device can be downsized and the power consumption can be reduced. Further, if frequency conversion is performed by sampling, a high-frequency signal can be directly handled, so that it is not necessary to use an analog IF circuit.

Further, since unnecessary components in a band close to a required signal component such as an adjacent channel signal component and an adjacent channel signal component are matched with the filter characteristic section of the moving average type digital filter, a simple structure is provided. Unnecessary components can be removed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a diagram showing an example of input / output states of a mixer.

FIG. 4 is a diagram showing a concept of multiplication processing.

FIG. 5 is a diagram showing an example of sine wave data.

FIG. 6 is a diagram showing an example of contents of a memory.

FIG. 7 is a diagram showing characteristics of a digital filter.

FIG. 8 is a diagram showing an input and an output of a digital filter.

FIG. 9 is a diagram showing an example of an output of a digital filter.

FIG. 10 is another embodiment of the present invention (code circuit).

FIG. 11 is another embodiment of the present invention (arbitrary digital filter).

FIG. 12 is a diagram showing a state of a sub-sampled signal.

FIG. 13 is a diagram showing the principle of subsampling.

FIG. 14 is a diagram showing an example of an operation when sub-sampling is performed.

FIG. 15 is another embodiment of the present invention.

FIG. 16 is an example of the memory contents of another embodiment of the present invention.

FIG. 17 is a block diagram showing a second embodiment of the present invention.

FIG. 18 is a diagram showing the principle of the second embodiment of the present invention.

FIG. 19 is a diagram showing the principle of the third embodiment of the present invention (the sampling frequency is at least twice the center frequency of the modulated wave signal).

FIG. 20 is a diagram showing the principle of the third embodiment of the present invention (the sampling frequency is not more than twice the center frequency of the modulated wave signal).

[Explanation of symbols]

 101 input terminal 102 analog / digital conversion circuit 103 counter 104 clock signal generator 105 first weighting memory 106 shift register 107 adder 108 second weighting memory 109 shift register 110 adder 1 input terminal 2 distributor 3 carrier signal generation Circuit 4 1st mixer 5 2nd mixer 6 Phase shift circuit 7 1st filter 8 2nd filter 9 1st analog / digital conversion circuit 10 2nd analog / digital conversion circuit 21 Input terminal 22 Analog / digital conversion circuit 23 Counter 24 Clock Signal generator 25 Driver circuit 26 Weighting memory 27 Selector 28 Shift register 29 Adder 30 First code circuit 31 Second code circuit 32 Multiplier 33 First low-pass filter 34 Second low-pass filter

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masahiro Narita 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (17)

[Claims] 1. An analog / digital conversion means for converting a modulated wave signal into digital data, a weighting means for weighting an output of the analog / digital conversion means, and a digital signal output from the weighting means are inputted.
A digital demodulator comprising: a shift register section and a moving average type digital filter means including an addition section. 2. Each of the weighting means and the moving average type digital filter means has two systems, one system outputs a modulated signal of an in-phase component (I component), and the other system outputs a quadrature component (I component). The digital demodulator according to claim 1, wherein a modulated signal of Q component) is output. 3. The analog / digital conversion means converts the modulated wave signal into digital data at a frequency N (integer of 2 or more) times the center frequency of the modulated wave signal, and inputs the digital data to the two weighting means. Then, each of the weighting means weights the amplitude value when the sine wave is equally divided into N in one system or a value obtained by multiplying the value by a constant, and in the other system, the phase is equal to the phase of the one system by π / 2. The shifted sine wave is divided into N equal parts, or weighted with an amplitude value or a value obtained by multiplying the value by a constant,
The number of data added to each output is KN / 2 (K is a natural number)
3. The digital demodulator according to claim 2, wherein the moving average type digital filter means, which is a single number, is inputted to obtain an I component modulation signal and a Q component modulation signal from two sequences. 4. The analog-to-digital conversion means converts the modulated wave signal into digital data at a frequency N (integer of 2 or more) times the center frequency of the modulated wave signal and L (integer of 2 or more) times the channel interval. Input to the weighting means of two systems, and each of the weighting means weights the amplitude value when the sine wave is equally divided into N in one system or a value obtained by multiplying the value by a constant, and the other In the system, the sine wave whose phase is shifted by π / 2 from the one system is weighted by the amplitude value when the N-divided sine wave or the value obtained by multiplying the value by a constant, and each output has the added data number KN. / 2 = J · L (K and J are natural numbers) are input to the moving average type digital filter means to obtain an I component modulated signal and a Q component modulated signal from two sequences. The digital demodulator according to claim 2. 5. The analog / digital conversion means converts the modulated wave signal into digital data at a frequency not more than twice the center frequency of the modulated wave signal, inputs the digital data to two systems of the weighting means, and outputs each of the weighting means. The weighting means weights the amplitude value when the sine wave is equally divided into 2 · M / K (both M and K are natural numbers) or a value obtained by multiplying the value by a constant in one system, and in the other system, A sine wave whose phase is shifted by π / 2 is weighted with an amplitude value obtained by equally dividing 2 · M / K or a value obtained by multiplying the value by a constant, and each output has an addition data number of M.
3. The digital demodulator according to claim 2, wherein the moving average type digital filter means, which is a single number, is inputted to obtain an I component modulation signal and a Q component modulation signal from two sequences. 6. The digital demodulation according to claim 5, wherein the sampling frequency of the analog / digital conversion means is 2 · M / K times the center frequency of the modulated wave signal sampled and frequency-converted. vessel. 7. The analog / digital conversion means converts the modulated wave signal into digital data at a frequency not more than twice the center frequency of the modulating wave signal and at a frequency L (integer of 2 or more) times the channel interval, and 2 Inputting to the weighting means of the system, each of the weighting means divides the sine wave in one system into 2 · J · L / K (both J and K are natural numbers) equal to the amplitude value or a constant multiple. The other system is weighted by the amplitude value when the sine wave whose phase is shifted by π / 2 from the one system is divided by 2 · J · L / K, or the value obtained by multiplying the value by a constant. And the number of data added to each output is J
The digital demodulator according to claim 2, wherein the moving average type digital filter means, which is L in number, is inputted to obtain an I component modulated signal and a Q component modulated signal from two streams. 8. The sampling frequency of the analog / digital conversion means is 2 · J · L / K times the center frequency of the modulated wave signal sampled and frequency-converted. Digital demodulator. 9. The weighting means is configured to alternately perform weighting of two systems, and a selection means for alternately distributing the output of the weighting means to the moving average type digital filter means having two systems is provided. 2. The digital demodulator according to claim 1, wherein the system outputs the modulated signal of the in-phase component (I component) and the other system outputs the modulated signal of the quadrature component (Q component). 10. The analog / digital conversion means comprises:
The modulated wave signal is converted into digital data at a frequency N (integer of 2 or more) times the center frequency of the modulated wave signal, input to one weighting means, and the weighting means alternately weights two systems. , One system is weighted with an amplitude value when the sine wave is divided into N equal parts or a value obtained by multiplying the value by a constant, and in the other system, a sine wave whose phase is shifted by π / 2 from the one system is divided into N parts. The moving average type digital filter means is weighted by the amplitude value of the divided value or a value obtained by multiplying the value by a constant, each output is selected, and the number of added data is K · N / 2 (K is a natural number). And input from two series I
10. The digital demodulator according to claim 9, wherein a component modulated signal and a Q component modulated signal are obtained. 11. The analog / digital conversion means comprises:
The modulated wave signal is converted into digital data at a frequency that is N (integer of 2 or more) times the center frequency of the modulated wave signal and L (integer of 2 or more) times the channel interval, and is input to one of the weighting means. The weighting means alternately weights two systems, one system is weighted by an amplitude value when a sine wave is divided into N equal parts or a value obtained by multiplying the value by a constant, and the other system is weighted by the one system. A sine wave whose phase is shifted by π / 2 is weighted with an amplitude value when the sine wave is divided into N equal parts or a value obtained by multiplying the value by a constant, and each output is selected to add K.
It is characterized in that N / 2 = J · L (K and J are natural numbers) are input to the moving average type digital filter means to obtain an I component modulated signal and a Q component modulated signal from two sequences. The digital demodulator according to claim 9. 12. The analog / digital conversion means,
The modulated wave signal is converted into digital data at a frequency equal to or less than twice the center frequency of the modulated wave signal and input to one of the weighting means, and the weighting means alternately weights two systems. Sine wave is 2 · M / K (M, K
(Both are natural numbers) weighted with an amplitude value when equally divided, or with a value obtained by multiplying the value by a constant, and in the other system
A sine wave whose phase is shifted by / 2 is weighted with an amplitude value when the sine wave is equally divided by 2 · M / K or a value obtained by multiplying the value by a constant, and each output is selected and the number of added data is M. Inputting to the moving average type digital filter means, I
10. The digital demodulator according to claim 9, wherein a component modulated signal and a Q component modulated signal are obtained. 13. The digital demodulator according to claim 12, wherein the sampling frequency of the analog / digital converting means is 2 · M / K times the center frequency of the modulated wave signal sampled and frequency-converted. vessel. 14. The analog / digital conversion means comprises:
The modulated wave signal is converted into digital data at a frequency that is less than or equal to twice the center frequency of the modulated wave signal and L (an integer greater than or equal to 2) times the channel interval, and the digital data is input to one of the weighting means. The two systems are weighted alternately, and in one system, the sine wave is equally divided by 2 · J · L / K (both J and K are natural numbers) or weighted by a value obtained by multiplying the value by a constant, and the other is The system of π /
A sine wave with a phase difference of 2 is weighted by the amplitude value when it is equally divided by 2 · J · L / K or a value obtained by multiplying this value by a constant, and each output is selected to add J · L. 10. The digital demodulator according to claim 9, wherein the moving average type digital filter means, which is a single unit, is inputted to obtain an I component modulated signal and a Q component modulated signal from two streams. 15. The sampling frequency of the analog / digital conversion means is 2.times.J.L / K times the center frequency of the sampled and frequency-converted modulated wave signal. Digital demodulator. 16. A demodulator for demodulating a modulated signal,
Sampling means for sampling the demodulated signal at a frequency of L (an integer of 2 or more) times the channel interval, and a shift register portion and an addition portion to which a digital signal is input from the sampling means, and the number of added data is A digital demodulator, comprising J · L (J is a natural number) moving average type digital filter means. 17. The demodulator has two systems of outputs, one of which outputs a modulation signal of an in-phase component (I component) and the other of which outputs a modulation signal of a quadrature component (Q component). 17. The digital demodulator according to claim 16, wherein: