JPH08107105A - Method for patterning silicon material layer - Google Patents

Abstract

PURPOSE: To provide a method of patterning of the Si material wiring such as polycrystalline silicon and the like to be formed on the base insulating film having a high step without forming residue and excessive side wall protecting film. CONSTITUTION: The reaction product 7, which is grown in a large quantity when main etching is conducted and remains in plasma, is over-etched while the reaction product 7 is being removed by high speed evacuation. The above- mentioned reaction product may be removed before overetching by purging using inert gas. Accordingly, an excessive side-wall protective film 6 is not deposited, by the redissociation of the reaction product 7 which remains when overetching. As a result, string-like residue does not remain on a stepped part, and also a gate insulating film 2 is not thinned off by a wet processing to be performed for removal of excessive side-wall protective film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for patterning a silicon-based material layer such as polycrystalline silicon used for internal wiring of a semiconductor device, and particularly when it is required to have a high selection ratio with respect to a base insulating film. The present invention relates to an effective patterning method for a silicon-based material layer.

[0002]

2. Description of the Related Art As the design rules of semiconductor devices such as LSI are miniaturized from half micron to quarter micron, the demand for microfabrication technology such as dry etching is becoming more severe. As an example, the thickness of the gate insulating film of the MOS transistor is 10n.
In the patterning of a gate electrode made of a silicon-based material such as polycrystalline silicon, which is being thinned to about m, a dry etching method capable of achieving a high selection ratio with respect to an underlying gate insulating film is required.

For this reason, in the recent processing of gate electrodes, ECR plasma, helicon wave plasma, etc., 1 × 10
^A general method is to use a plasma etching apparatus having a high-density plasma generation source of ¹⁰ / cm ³ or more, employ a Cl-based or Br-based etching gas, and perform patterning under low ion incident energy conditions. Seen in terms of the binding energy between two atoms, this is Si- which forms the gate insulating film.
O bond (800 kJ / mole) and Si-N bond (43
Relative to the bond energy of 9 kJ / mole), the Si-Cl bond (406 kJ / mole) that constitutes the reaction product of etching.
mole) and Si-Br bond (368 kJ / mole)
This is because the binding energy of is smaller than that of the gate insulating film under low ion energy conditions. By using Cl-based or Br-based etching gas, a high selection ratio of 30 or more can be achieved. As an example, a high selective ratio etching method for a polycrystalline silicon layer using HBr gas is disclosed in US Pat. No. 4,502,915 and JP-A-2-224241.

Usually, in patterning of a silicon material-based layer including processing of a gate electrode, main etching with high ion energy and low selection ratio including breakthrough of a natural oxide film and a high selection ratio with an underlying insulating film are performed. A two-step etch consisting of achieving low ion energy overetch is used. In this over-etching process, the substantial etching rate of the underlying insulating film is a very small value of 2 nm / min or less,
During the over-etching process, the base insulating film is hardly etched and the film is hardly reduced.

By the way, during the over-etching process, silicon halide, which is a reaction product generated during the main etching process of the previous process, remains on the inner wall and space of the etching chamber. The reaction products are SiCl _x , SiO _x Cl _y , SiBr _x and S.
iO _x Br _{y and the} like, and a part of these is re-dissociated by high-density plasma and deposited on the substrate to be processed. The mechanism of such re-dissociative deposition has been reported in, for example, Proceedings of the 41st Joint Lecture on Applied Physics (Spring Annual Meeting 1994) p573, Lecture No. 30a-ZF-8. Since this re-dissociated deposit is a substance of SiO _x type, it is naturally not etched under the over-etching condition with a high selection ratio, and acts to hinder the etching of the silicon material type layer. Therefore, the etching rate of the silicon material layer is determined by the competitive conditions of the deposition reaction of the re-dissociative deposit and the etching reaction.

For this reason, the deposition reaction of the re-dissociation deposit becomes dominant on the side surface portion and the step side surface portion of the pattern where the number of incident ions during etching is small, and as the etching time elapses, the thickness of the re-dissociation deposit of SiO _x system becomes gradually increased. The side wall protection film is accumulated and formed. FIG. 5A to FIG. 5B and FIG. 6C to FIG. 6C are schematic cross-sectional views illustrating this state in the order of steps of a conventional method for patterning a silicon-based material layer.
FIG. 5 (a ′) to (b ′) and FIG. 6 showing (d) and a schematic cross-sectional view of the plasma etching apparatus corresponding to each step.
This will be described with reference to (c ') to (d').

A gate insulating film 2 and an element isolation region 3 are formed on a semiconductor substrate 1 such as Si on which an active element (not shown) such as an impurity diffusion layer is formed, and a silicon material made of n ⁺ polycrystal silicon or the like. A system layer 4 and a resist mask 5 for patterning are formed. This sample shown in FIG. 5A is a substrate to be processed. This processed substrate 15 is shown in FIG.
It is set on the substrate stage of the ECR plasma etching apparatus 10 shown in (a ′).

Next, main etching of the Si-based material layer 4 is performed by high-energy and low-selection-ratio main etching. 5 (b) and 5 (b ') show an intermediate stage of this main etching. A side wall protection film 6 is adhered and formed on the side surfaces of the resist mask 5 and the patterned silicon-based material layer 4 by decomposition products of the resist mask 5 and etching reaction products, which contributes to improvement of anisotropy. On the other hand, the above-mentioned reaction product 7 to be exhausted exists in the plasma 7.

After the main etching is completed and the silicon-based material pattern 4P is formed, the over-etching is performed under the condition of low ion energy and high selection ratio, and the residue 4R of the Si-based material layer in the step portion of the element isolation region 3 is removed. Etc. are removed. This state is shown in FIGS. 6 (c) and 6 (c '). At this stage, the reaction product 7 remaining in the plasma is re-dissociated by the high-density plasma, and the SiO _x side wall protective film 6 is left on the side surface of the residue 4R and the silicon-based material pattern 4P.
Further deposit and grow on the side surface.

FIGS. 6 (d) and 6 (d ') show the stage after the over-etching is completed and the residue 4R of the silicon-based material layer is newly etched off. When the side wall protective film 6 is formed thick on the side surface of the residue 4R of the silicon-based material layer, this serves as an etching mask, and the residue 4R of the silicon-based material layer remains in a string shape on the side surface of the element isolation region 3. The string-like residue 4R remains in a streak shape on the step portion and is conductive, which causes a short circuit between the wirings. Further, if the side wall protective film 6 is thickly deposited on the side surfaces of the resist mask 5 and the silicon-based material pattern 4P, it has a good result in preventing the undercut, but this must be finally removed. Since the sidewall protection film 6 is a SiO _x based material comprising previously SiO _x system or Cl As mentioned, a halogen atom Br, etc., out the substance of the SiO _x type taken into the air to be treated substrate after etching Is converted to. Therefore, it can be removed by wet etching with a dilute HF aqueous solution or the like. However, when the film thickness of the side wall protection film 6 is large, the processing time of this wet process becomes long, resulting in a film thickness loss of the gate insulating film, which may lead to deterioration of device characteristics.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to generate a residue in patterning a silicon-based material layer such as polycrystalline silicon. It is an object of the present invention to provide a method for patterning a silicon-based material layer that can realize a high selection ratio with respect to the underlying insulating film.

Another object of the present invention is to provide a method of patterning a silicon-based material layer which can produce a highly reliable semiconductor device without a device failure due to a short circuit between wirings or damage to a gate insulating film. is there. Other problems of the present invention will be made clear by the description of the present specification and the description of the accompanying drawings.

[0013]

A method of patterning a silicon-based material layer of the present invention is proposed in order to solve the above-mentioned problems.
A method for patterning a silicon-based material layer, which comprises patterning by plasma etching including a first etching step having a high etching rate and a second etching step having a high selection ratio, wherein an exhaust rate of an etching gas in the second etching step. Is set to be higher than the exhaust rate of the etching gas in the first etching step. The first etching step corresponds to just etching, and the second etching step corresponds to an over-etching step.

The exhaust rate of the etching gas in the second etching step is preferably 1000 l / sec or more.

Another method of patterning a silicon-based material layer according to the present invention is also proposed to solve the above-mentioned problems. The silicon-based material layer on the insulating film is formed with a high etching rate. 1. A method of patterning a silicon-based material layer, comprising: patterning by plasma etching including an etching process of No. 1 and a second etching process of high selectivity, wherein the patterning method is performed between the first etching process and the second etching process. In addition, the method further comprises a purging step with an inert gas. That is, after the main etching is completed, the inside of the etching apparatus is replaced with an inert gas, and then an over-etching step is performed. As the inert gas, a rare gas such as He, Ar, Xe and Kr, N ₂ , O ₂ or dry air may be used.

The etching gas used in the present invention is
It is desirable to contain any one of Cl-based gas, Br-based gas, and I-based gas. Here, the Cl-based gas includes Cl ₂ , HCl, BCl ₃ , CCl ₄ and SiC.
Any gas containing Cl atoms such as l ₄ can be used. Also B
Examples of the r-based gas include Br ₂ , HBr BBr ₃ , and CBr.
Gases containing Br atoms such as ₄ and SiBr ₄ can optionally be used. Further, as I-based gas, I ₂ , HI, B
Gases containing I atoms such as I ₃ , CI ₄ and SiI ₄ can optionally be used. These gases may be used alone or in combination. Further, H ₂ , N ₂ , O ₂ or a rare gas may be mixed and used as an additive gas.

The silicon material layer used in the present invention contains Si as a constituent element or a main constituent element such as polycrystalline silicon, amorphous silicon, refractory metal silicide and refractory metal polycide. Of course, n-type and p-type impurities may be included.

[0018]

The point of the present invention is that the re-dissociative deposition species due to the reaction products deposited on the substrate to be processed during over-etching are removed as much as possible from the inside of the etching chamber, and over-etching is performed.

The reaction products remaining in the chamber during the over-etching stage are mainly generated during the main etching with a high etching rate. This is because in the over-etching process in which the exposed area of the layer to be etched is small, the etching rate may be small and the amount of reaction products generated is small. Therefore, in order to prevent the influence of the residual reaction product generated during the main etching on the overetching in the next step, it is most effective to remove the residual reaction product quickly while performing the overetching. For this purpose, over-etching may be performed at an effective pumping speed of 1000 l / sec or more.

On the other hand, in the main etching process, the retention of the reaction product in the etching chamber is necessary to form a side wall protective film and prevent side etching. For this reason, it is desirable that the exhaust rate of the etching gas is lower than that during overetching, for example, a low exhaust rate of about 200 l / sec.

In order to continuously perform etching with different pumping speeds, an apparatus in which a gate valve connects an etching apparatus having a large pumping vacuum pump and an etching apparatus having a small pumping vacuum pump may be used. However, more realistically, for example, a vacuum pump having a large exhaust amount of about 3000 l / min and an etching apparatus having a conductance valve for controlling the exhaust amount may be used, and the exhaust amount may be switched by controlling the conductance valve.

By the way, the concept of high-speed exhaust etching using a large displacement pump is disclosed in, for example, Japanese Unexamined Patent Publication No. 5-167226.
There is a disclosure or a report in the gazette and the 1992 Dry Process Symposium Proceedings p49-54. However, neither of the technical ideas of the present invention is found in which the evacuation rate is switched between the main etching step and the overetching step to control the residence time of the reaction product.

Due to equipment restrictions, an etching apparatus that is not equipped with a large displacement vacuum pump, or an etching apparatus that is not equipped with a sufficient pumping speed adjustment, will affect etching after the main etching is completed. Purge the chamber with no inert gas to eliminate residual reaction products. If over-etching is performed from this stage, it is possible to prevent the influence of the residual reaction product generated during the main etching on the over-etching in the next step. Purging with an inert gas can be removed in a much shorter time than simply removing the etching gas and evacuating the residual reaction products. Since the inert gas may be replaced with the residual reaction product, it is not necessary to turn it into plasma. If the so-called cycle purge, in which the purging of the inert gas and the evacuation of the vacuum are repeated a plurality of times, the above-mentioned effect is further enhanced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings to be referred to below, parts having the same functions as those in the drawings referred to in the description of the prior art are designated by the same reference numerals.

Example 1 First, the plasma etching apparatus used in this example will be described with reference to FIG. As an example, the plasma etching apparatus shown in FIG. 3 includes a turbo molecular pump 17 and a dry pump 18, which have a large displacement of 5000 l / min.
And, for example, 100 l / min to 3000 l / m
A vacuum exhaust system is configured by the conductance valve 16 and the like whose effective exhaust speed is variable within the range of in. The plasma etching apparatus main body 10 is the same as the conventional one, and a microwave generated by a magnetron (not shown) is introduced into the etching chamber via the microwave waveguide 11 and the quartz bell jar 12, and the solenoid coil 13 is generated. The ECR mode plasma is excited by the interaction with the magnetic field. The substrate 15 to be processed is set on the substrate stage 14 in the etching chamber.

Next, a method of patterning a silicon-based material layer according to the present embodiment will be described in the order of the steps shown in FIGS. 1A to 1B and FIGS. 2C to 2D, and each step. 1 (a ')-(b') and FIG. 2 (c ')-showing a schematic cross section of a plasma etching apparatus corresponding to FIG.
This will be described with reference to (d ').

The substrate to be processed shown in FIG. 1A is obtained by thermally oxidizing a semiconductor substrate 1 made of Si or the like on which an active element group such as an impurity diffusion layer (not shown) is formed, and a gate insulating film 2 having a thickness of 10 nm and An element isolation region 3 is formed, a silicon-based material layer 4 made of an n ⁺ polycrystalline silicon layer is deposited to a thickness of 400 nm under the following LPCVD conditions, and further, a negative chemically amplified resist and KrF excimer laser lithography are used. For example, the resist mask 5 is formed to have a width of 0.35 nm. SiH ₄ 500 sccm PH ₃ 0.3 sccm Gas pressure 100 Pa Substrate temperature 500 ° C. Silicon-based material layer 4 has a step difference of about 200 nm reflecting the thickness of element isolation region 3. This substrate 15 to be processed is set in a plasma etching apparatus having a large pumping vacuum pump shown in FIG.

Main etching of the silicon-based material layer 4 and
Then, as an example, plasma etching is performed under the following conditions.
Give. Cl₂ 75 sccm O₂ 5 sccm Gas pressure 0.4 Pa Microwave power 850 W (2.45 GHz) RF bias power 80 W (13.56 MHz) Substrate temperature to be treated 20 ° C. Exhaust rate 200 l / sec In this etching step, FIG. ) And Figure 1
As shown in (b '), the layer to be etched and the etching gas are
Reaction product 7 of SiCl_xAnd SiO _xCl
_ySide wall protective film made of decomposition products of the resist mask 5
6 is being patterned on the side surface of the resist mask 5 and patterning
An anisotropic etchant is formed by being attached to the side surface of the silicon-based material layer 4.
Contribute to ching. In the plasma 19 of etching gas
Also, these reaction products 7 are present.

Immediately before the underlying gate insulating film 2 is exposed by patterning of the silicon-based material layer 4, or 1
When the part is exposed, the following over-etching conditions are switched. At this stage, as shown in FIGS. 2C and 2C ′, the residue 4R of the silicon-based material layer remains in the step portion of the element isolation region 3. Under this over-etching condition, a large evacuation rate is adopted as compared with the main etching condition, so that a large amount of reaction products 7 generated during the main etching and remaining in the plasma are promptly removed and the amount thereof is small. . HBr 120 sccm O ₂ 4 sccm Gas pressure 1.0 Pa Microwave power 850 W (2.45 GHz) RF bias power 60 W (13.56 MHz) Processed substrate temperature 20 ° C. Pumping speed 3000 l / sec

In this over-etching process, the residue 4R
And the rest of the silicon-based material layer 4 is SiBr _x.
Since reaction products such as SiO _{x and} Br _y are formed and quickly removed, they are not redeposited excessively on the substrate to be processed. Further, by adopting the Br-based gas and adopting the RF bias power which is lower than that in the main etching, the selection ratio with respect to the gate insulating film 2 was 200 or more. Therefore, the gate insulating film is not damaged. In addition, the gas pressure is set higher than that in the main etching, and the etching conditions take isotropicity into consideration, so that the residue 4R is completely removed and does not remain in a string shape. FIG. 2D and FIG. 2D show a state in which the over-etching is completed and the evacuation rate is lowered again.

Finally, the resist mask 5 is removed by ashing or a stripping solution, and the side wall protection film 6 is lightly etched with a dilute HF aqueous solution to complete the silicon material pattern 4P. According to the present embodiment, by setting a high evacuation rate during overetching, it is possible to prevent excessive deposition of reaction products and prevent deterioration of device characteristics due to string-like residues and reduction of the gate insulating film. Becomes

Example 2 This example is an example in which the same substrate as in Example 1 was patterned by inserting a purging step with an inert gas by an ordinary plasma etching apparatus having no large displacement pump. 4A to 4C, which are schematic cross-sectional views illustrating a method of patterning a silicon-based material layer according to the present embodiment in the order of steps, and a schematic cross-section of a plasma etching apparatus corresponding to each step. (A ')-(c')
Will be described with reference to.

The substrate to be processed and the main etching conditions adopted in this embodiment are the same as in the previous embodiment, and the steps up to the main etching are shown in FIGS. 1 (a)-(b) and FIG.
(A ')-(b') will be replaced, and redundant description will be omitted. However, the plasma etching apparatus used in this example is a normal apparatus having a vacuum pump with an exhaust rate of several hundred l / sec.

In the present embodiment, after the main etching is completed and before the next over-etching step, an inert gas is purged under the following conditions. He 100 sccm Gas pressure 0.5 Pa Microwave power 0 W RF bias power 0 W Substrate temperature 20 ° C. Pumping speed 200 l / sec In this purging step, no microwave was applied and plasma was not generated. Most of the reaction product 7 remaining in the etching chamber is replaced with He and is removed. 4A and 4B are schematic cross-sectional views of the substrate to be processed and the plasma etching apparatus during the purging step.
It shows in (a ').

Subsequently, as an example, the over-etching condition is switched under the following conditions. During this over-etching, the amount of the reaction product 7 generated in a large amount during the main etching and remaining in the plasma is small. HBr 120 sccm O ₂ 4 sccm Gas pressure 1.0 Pa Microwave power 850 W (2.45 GHz) RF bias power 60 W (13.56 MHz) Processed substrate temperature 20 ° C. Pumping speed 200 l / sec

In this over-etching process, the residue 4R
And the rest of the silicon-based material layer 4 is SiBr _x.
And reaction products such as SiO _x Br _y are formed and removed. Although the exhaust rate is as low as 200 l / sec, the amount of new reaction product 7 is small and the amount of reaction product 7 remaining during the main etching is small. 6 does not redeposit. Further, by adopting the Br-based gas and adopting the RF bias power which is lower than that in the main etching, the selection ratio with the gate insulating film 2 is also 200 or more, and the gate insulating film is not damaged. In addition, the gas pressure is set higher than that in the main etching, and the etching conditions take isotropicity into consideration, so that the residue 4R is completely removed and does not remain in a string shape. FIG. 4C and FIG. 4C ′ show a state in which the overetching is completed and the exhaust speed is lowered.

Finally, the resist mask 5 is removed by ashing or a stripping solution, and the side wall protective film 6 is lightly etched with a dilute HF aqueous solution to complete the silicon material pattern 4P. According to the present embodiment, a normal plasma etching apparatus without a large displacement pump is adopted, and a purge process with an inert gas is inserted before overetching to prevent the deposition of an excessive side wall protective film and to prevent the string. It is possible to prevent the generation of a particulate residue and the reduction or damage of the gate insulating film.

The present invention has been described above with reference to the two examples, but the present invention is not limited to these examples.

For example, if a step of purging the inside of the etching chamber with an inert gas is inserted before the overetching step under the large displacement condition in Example 1, the removal of the residual reaction product is more thorough. Will be things.

Although the silicon-based material wiring or the silicon-based material layer is made of n ⁺ polycrystalline silicon, the constituent elements or main constituents of Si such as amorphous silicon, refractory metal silicide and refractory metal layer polycide are shown. The present invention can be applied to a conductive material as an element and a laminated material thereof. These material layers are
Both are materials that easily generate string-like residues due to excessive deposits due to re-dissociation of reaction products.

Although Cl ₂ has been described as a representative example of the Cl-based gas and HBr has been described as the representative of the Br-based gas, an etching gas containing Cl, Br or I as a constituent atom can be appropriately used as described above. is there.

In each of the above-mentioned embodiments, prevention of residues and film reduction of the gate insulating film when anisotropically etching the silicon-based material wiring into a rectangular shape has been described. In addition to this purpose, the present invention can be applied to the case of patterning a silicon-based material wiring in a forward tapered shape. In this case,
It is possible to obtain a forward taper-shaped silicon-based material wiring by adopting a condition in which the sidewall protective film is deposited abundantly, for example, a condition in which the mixing ratio of the O ₂ gas in the etching gas in the above-described embodiment is increased. Also in this case, it is possible to prevent the string-like residue in the step portion. Such a forward tapered wiring is useful for a lower layer electrode / wiring of a CCD image pickup device or the like to improve step coverage of an interlayer insulating film or an upper wiring.

A substrate bias application type ECR plasma etching apparatus was used as the etching apparatus, but a parallel plate type RIE apparatus or a magnetron RIE apparatus may be used. Helicon wave plasma etching equipment, TCP (Tr
Transformer Coupled Plasma)
Etching equipment, ICP (InductivelyCo)
If a high-density plasma etching device such as an up plasma etching device is used, it is expected that further uniformity in the substrate to be etched, low damage, high etching rate, and the like can be expected.

[0044]

As is apparent from the above description, according to the present invention, when patterning a layer to be etched made of a silicon-based material layer, no residue is generated and a high selection ratio with respect to the underlying insulating film is obtained. It has become possible to provide a practicable method for patterning a silicon-based material layer.

Further, according to the present invention, it is possible to provide a method for patterning a silicon-based material layer capable of manufacturing a highly reliable semiconductor device without a device defect due to a short circuit between wirings or damage to a gate insulating film. became.

Due to these effects, it becomes possible to form the silicon-based material wiring used for the semiconductor device having a high step due to the adoption of the multilayer wiring with high reliability, and the present invention is applied to the manufacturing process of the highly integrated semiconductor device. The contribution is great.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating the first half of a method for patterning a silicon-based material wiring according to a first embodiment of the present invention in the order of steps, wherein (a) shows a silicon-based material layer and a silicon-based material layer on a base having steps. With the resist mask formed,
(A ') is a state in which this substrate to be processed is set in a plasma etching apparatus, (b) is a state in which a silicon-based material layer is being patterned, and (b') is a large amount of reaction products in the plasma of etching gas. It is a state that exists in.

FIG. 2 is a schematic cross-sectional view illustrating the latter half of the method for patterning a silicon-based material wiring of Example 1 to which the present invention is applied in the order of steps, and FIG. 2 (c) shows a residue of the silicon-based material layer removed by overetching. The state of
(C ') is a state in which reaction products are slightly present in the plasma of the etching gas by high-speed exhaust, (d) is a state in which the patterning of the silicon-based material layer is completed,
(D ') is the state of the plasma etching apparatus after the patterning is completed.

FIG. 3 is a schematic cross-sectional view of a large-displacement plasma etching apparatus used in Example 1 to which the present invention is applied.

FIG. 4 is a schematic cross-sectional view illustrating the latter half of the method for patterning a silicon-based material wiring according to the second embodiment of the present invention in the order of steps, in which (a) is inactive after main etching of the silicon-based material layer. Gas is being purged, (a ') is a state in which a reaction product is slightly present in the chamber due to inert gas purging, and (b) is a silicon-based material layer residue removed by overetching. (B ') showing a state of reaction products in plasma during over-etching, (c) showing a state of patterning the silicon-based material layer, (c')
Is the state of the plasma etching apparatus after the patterning is completed.

FIG. 5 is a schematic cross-sectional view illustrating the first half of a conventional method for patterning a silicon-based material layer in the order of steps, (a)
Is a state in which a silicon-based material layer and a resist mask are formed on a base having steps, and (a ′) is a state in which the substrate to be processed is set in a plasma etching apparatus,
(B) is a state in which the silicon-based material layer is being patterned, and (b ') is a state in which a large amount of reaction products are present in the plasma of the etching gas.

FIG. 6 is a schematic cross-sectional view for explaining the latter half of the conventional method for patterning a silicon-based material layer in the order of steps, (c)
Is a state in which an excessive side wall protective film is deposited by re-dissociation of reaction products when the residue of the silicon-based material layer is over-etched, and (c ′) is a large amount of reaction products in the plasma during over-etching. Remains, (d)
The state where the patterning of the silicon-based material layer is completed and the string-like residue is left on the step side surface, and (d ′) is the state of the plasma etching apparatus after the patterning is completed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Element isolation region 4 Silicon-based material layer 4P Silicon-based material pattern 4R Residue 5 Resist mask 6 Sidewall protective film 7 Reaction product 10 Plasma etching device 11 Microwave waveguide 12 Berja 13 Solenoid coil 14 Substrate stage 15 Substrate to be processed 16 Conductance valve 17 Turbo molecular pump 18 Dry pump 19 Plasma

Claims (7)

[Claims] 1. A method for patterning a silicon-based material layer, which comprises patterning a silicon-based material layer on an insulating film by plasma etching including a first etching step with a high etching rate and a second etching step with a high selection ratio. The method of patterning a silicon-based material layer, wherein the exhaust rate of the etching gas in the second etching step is higher than the exhaust rate of the etching gas in the first etching step. 2. The method for patterning a silicon-based material layer according to claim 1, wherein the exhaust rate of the etching gas in the second etching step is 1000 l / sec or more. 3. The method for patterning a silicon-based material layer according to claim 1, wherein the etching gas contains any one of Cl-based gas, Br-based gas, and I-based gas. 4. The silicon-based material layer is polycrystalline silicon,
The method for patterning a silicon-based material layer according to claim 1, wherein the method is at least one selected from the group consisting of amorphous silicon, refractory metal silicide and refractory metal polycide. 5. A method for patterning a silicon-based material layer, which comprises patterning a silicon-based material layer on an insulating film by plasma etching including a first etching step with a high etching rate and a second etching step with a high selection ratio. A method of patterning a silicon-based material layer, further comprising a purging step with an inert gas between the first etching step and the second etching step. 6. The method for patterning a silicon-based material layer according to claim 5, wherein the etching gas contains any one of Cl-based gas, Br-based gas, and I-based gas. 7. The silicon-based material layer is polycrystalline silicon,
6. The method for patterning a silicon-based material layer according to claim 5, wherein the method is at least one selected from the group consisting of amorphous silicon, refractory metal silicide, and refractory metal polycide.