JPS5846440A - Microprogram control system - Google Patents

Abstract

PURPOSE:To execute two microprograms (muP) effectively in parallel by using a mechanism which performs execution control from the 1st-level muP to the 2nd- level muP and address modification from the 2nd-level muP to the 1st-level muP for control over the two-level muP. CONSTITUTION:When a stop indication (STPIN)37 is outputted from a microprogram muP with the 1st level, a stop restarting control part 25 outputs a stop signal 38 to inhibit the update of a level address selector 12. For the restarting of the muP with the 1st level, the stop signal 38 is reset from a stop restarting control part 25 by the restart indication 39 of a muP with the 2nd level. At this time, an address selector 11 is modified according to the address modification field 40 of the muP with the 2nd level. Microinstructions outputted from a control storage 11 are supplied to a level microinstruction register 16. Then, microinstructions from a control storage 21 are supplied to a level microinstruction register 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control scheme between a first level microprogram and a second level microprogram in a two-level microprogram control scheme.

Conventionally, two-level microprogram control systems include a system in which the order control function and the designation of micro operations are separated, and a system in which a horizontal microprogram is controlled by vertical microinstructions. However, in the former method, the control storage capacity for storing order control information is required for the number of steps in the microprogram, and it is also necessary to obtain a branch address from the microoperation specification section to determine the address when there is a branch. There are some drawbacks that arise.

In addition, in the latter method, the horizontal microprogram section at the second level controls the retrieval of the vertical microinstructions at the second level from the control memory. The drawback was that it was impossible to execute them in parallel.

An object of the present invention is to solve the above-mentioned drawbacks by performing stop and restart control between microprograms and modifying the execution address of the microprogram at the second level according to the execution result at the second level. By reducing the number of words in Lebel's control memory and reducing the address width of the sequence section, the amount of hardware in the control section is reduced, and branch address control and control between microprograms are easy, and parallel execution of programs increases processing power. The purpose is to provide a microprogram control method.

The microprogram control system of the present invention has an L&2 level microprogram control system in which the microprogram is set to two levels, and includes an execution instruction field for instructing the execution of the second level microprogram in the control memory of the second level; The second level has an execution address field that specifies the execution start address of the microprogram at the second level, a sequence control field that controls the execution order of the second level's own microprogram, and a stop instruction field that stops the microprogram at the second level. has a sequence control field for controlling the execution order of the second level's own microprogram in its control memory, and an address modification field for modifying the address of the microprogram at the second level, and a sequence control field for the microprogram at the second level. means for controlling the execution order of the second rubel microprogram according to the specification of
means for controlling the execution order of the second-level microprogram according to the specification of the sequence control field of the second-level microprogram; means for setting an execution start address in the microprogram to a second level microprogram address;
The execution of the microprogram of the second level is interrupted by the stop instruction in the stop instruction field in the microprogram of the second level, and the microaddress of the second level is modified by the address modification field of the microprogram of the second level. The present invention is characterized by comprising means for restarting the microprogram of the second level from the modified address in response to a restart instruction in a restart instruction field in the second level microprogram.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The second level control memory (CMI) 11 and the second level control memory (0M2) 21 are a second level control memory address register (CMAR,1) 12 and a second level control memory address register (CMAR2) 22, respectively. Retrieve information from control memory according to the content indicated. CMARI(12
) contains the second level address selector (8EL1) 13, the second level program counter (PCI) 14, the subroutine stack (8TK) i5, and the second level jump address 6 (JUMPI) 31, which contains the second level sequence control field. (snQl) 32 is selected and latched. CMAI-L2 (21) includes
The second level address selector (8kJh2) 23, the M2 level program counter (PO2) 24, and the execution start address (
What is specified in the second level sequence control field (SEQ2) 35 and the execution instruction field (EXIN) 36 from the microprogram of the second level between EXAD) 33 and second level jump address (JUMP2) 34 is Selected and lunched.

Stop command (8TPI) from the microprogram of the first rubel
N) When 37 is issued, the stop/resume control unit (STCNT'
) 25, a stop signal (STOP) 38 is issued, and C
Prohibits updating of MARl(12). The restart of the second level microprogram is performed by the second level microprogram restart instruction (START) 39.
5 to 5 TOP38 will be released.

At this time, according to the address modification field (ADMOD) 40 of the second level microprogram, CMARx (1
1) is modified. The microinstruction taken out from CMI (11) is entered into the second level microinstruction register (CMI 几1) 16, and the microinstruction taken out from 0M2 (21) is put into the second level microinstruction register (CMIR2) 26. Decoders (1) ECI) 17, (DEC2) 2
7 to create a gate control signal.

FIG. 2 is a flowchart showing an embodiment of the microprogram according to the present invention.
The part on the right side is the micro-operation unit executed in CM 1. Also the third
This figure shows the contents of the control memory of the level 2, and FIG. 4 shows the contents of the control memory of the second level.

Suppose that address (a) of CMI is read.At this time, 0
Execution of the microprogram at address [a] of M2 is instructed, and l'1l=l'13 is executed in Cλi1.

Since the CMI sequence control is +1 and there is no stop instruction, the next address [a+1] is read. 0M
Execute function SUB at address (b) of 2. In 1-1-1C, R
2=R2+R5 is executed. CMl's 7-kunsu control is +1 and there is no stop instruction, so the next address (a+2)
The address is read and R4=R2+1 is executed. At this time, since the execution instruction field of CM2 does not provide an execution instruction, the CM2 execution address in CM1 becomes meaningless. However, since the previous [b] address execution button and the sequence control field of 0M2 are set to +1, addresses (b+1) will be executed consecutively. Here, since a stop instruction has been issued, execution at address [α+3] is stopped. In 0M2, the function SUB is (b-1-n
:] Since the instruction is to execute up to the (b+n)th step, it will be executed up to the (b+n)th step regardless of whether CM1 is stopped.

When 0M2 executes address [b+n], a restart instruction is issued, so that [α+3] is read and execution of address [α+3] begins. Here, the micro-operations of CMl are N
With OP (No 0 operation), no operation is specified and the microprogram at address C in 0M2 is executed.

Here, the sequence control field of CMl is con
In d2, since the condition of Cm■2 is satisfied, address modification from 0M2 is allowed, and if the condition is false, the address is modified with the content specified by the address modification field +10, and [
α+13) address is executed.

If the condition is true, address [α+4] is executed.

In this way, the stop/resume control mechanism can easily implement functions that require different processing times between two microprograms, and is highly efficient in parallel processing. Flexibility and ease of change are achieved.

The present invention provides stop and restart control, execution control of a second level microprogram from the second level microprogram, and a mechanism for modifying the address of one phycroprogram from the second level to the second level. By using this, a microprogram of the first chapter can be easily created, and the number of memorized words can also be reduced.
Parallel processing of two microprograms is effectively realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a flowchart showing an embodiment of the microprogram in the IFI (fC) of the present invention, and Figure 3 is a block diagram showing an embodiment of the microprogram in the IFI (fC) of the present invention. Diagram showing the contents of Lebel's control memory, No. 4
The figure also shows the contents of the second level control memory. 10-11...No. 1 Lebel's control memory (CMI),
12...Control storage address register (CMARI) of the 1st level, 13...2nd level address selector (SELL), 14...2nd level program counter (PCI) , 15... Subroutine stack (STK), 16... Second level microinstruction register (cMHt
i), 17... decoder (DECI), 2
1... Second level control memory (0M2), 22
...Second level control storage address register (C
MAR2), 23... Second level address selector (SEL2), 24... Second level program counter (PO2), 25... Stop/resume control unit (STCNT), 26... Second level microinstruction register (CMIR, 2), 2
7...Decoder (DEC2), 31...
・Second level jump address (JUMPI), 32・
...Second level sequence control field (SE
QI), 33...Address (EXAD') of the start of execution from the microprogram of the th level, 3
4...--Second level jump address (JUMP
2), 35... Second level sequence control field (8EQ2), 36... Execution instruction field (EXIN) from the microprogram of the second level
, 37... Stop instruction (STPIN) from the microprogram of the th level, 3B... Stop signal (
S'l0P), 39... Second level microprogram restart instruction (STAR, T), 40...
...Second level microprogram address modification field (ADMOD).

Claims (1)

[Claims] In a two-level microprogram control system with two levels of microprograms, an execution instruction field for instructing the execution of a second-level microprogram is provided in the control memory of the second level, and an execution start address of the second-level microprogram is stored in the control memory of the second level. It has an execution address field for specifying, a sequence control field for controlling the second level's own microprogram execution order, and a stop instruction field for stopping the microprogram at the second level,
The second level control memory has a sequence control field for controlling the execution order of the second level's own microprograms, and an address modification field for modifying the address of the second level's microprogram. means for controlling the execution order of the second level microprogram according to the specification of the sequence control field; and means for controlling the execution order of the second level microprogram according to the specification of the sequence control field of the second level microprogram. means for setting the execution start address in the microprogram of the second level to the second level microprogram address according to the execution instruction field of the microprogram of the second level; The stop instruction in the stop instruction field interrupts the execution of the microprogram at the second level, and the address modification field of the second level microprogram modifies the microaddress at the second level. A microprogram control system characterized by comprising means for restarting a second level microprogram from the qualified address in response to a restart instruction in a restart instruction field within the microprogram.