JPS6011950A - Memory system of double structure - Google Patents

Abstract

PURPOSE:To improve the reliability of a memory system by confirming that the data output of a memory is normal, then writing the normal data automatically to another memory. CONSTITUTION:When the data of a using memory 1 is judged to be wrong by an error detecting part 4, the memory 1 is switched to a spare memory 2. The data output given from the memory 2 is sent to the part 4 and confirmed that it is normal. Then a processing control part 7 gives an indication to a memory switching part 3 to turn the memory 1 into a data writable state with an indication of a microprogram stored in a semifixed memory 8. Then an indication is given to a data switching part 9 to obtain a state where the input data can be supplied to a data writing register 13. Then the normal data is shifted to the register 13 from a data reading register 12 and then written to the address of the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a memory recovery system after error processing in a small capacity memory duplication system for an electronic computer.

(b) Background of the technology In recent years, small-capacity memories such as the local storage of computers have been duplicated into a storage memory and a spare memory, which prevents errors from occurring in data read from a specific address in one memory. If detected, a redundant memory system is used in which the machine check process switches to the fl, l> memory and reads data from the same specific address as mentioned above in the memory and confirms that the data is error-free before use. Improves memory system reliability.

However, in the conventional duplex system, the address of one memory that outputs the erroneous data was changed by 9 times to the address of the other memory and was left unattended, so from the point of view of the data at that address, the address of the other memory However, duplication was lost. The present invention focuses on this problem and prevents the reliability of the memory system from decreasing by writing normal data again to the address where the error data was output.

(C) Prior Art and Problems FIG. 1 shows a system diagram of a dual memory system according to the prior art.

In FIG. 1, l is the current memory, and 2 is the backup memory. When there is a command to read data at address (xl), Xl is input from 100 to the address register 11, and the current memory specified by the address register 11 is Data (address (X+)) is read and the data is set in the data read register 12.

The data set in the data read register 12 is sent to the error detection section 4, where an error determination is made.

If the error detection unit 4 makes an error determination, the determination signal is sent to the processing control unit 5, and the processing control unit 5 specifies the memory switching unit 3 to change the readable memory from the current memory 1 to the spare memory 2. Address of spare memory (Xl) (X
=X2), the data is set in the data read register 12. The data set in the register 12 is checked for errors in the data using the same process as described above.

After switching to the spare memory 2, the spare memory 2 continues to be readable as long as there is no error in the data output of the spare memory 2, but if an error is detected in the data output of the spare memory 2, the current memory 1 Memory switching is then performed using a process similar to that described above.

The above-mentioned processing control 50 function receives the judgment signal from the error detection section 4 according to instructions from a microprogram stored in the semi-permanent storage device 6, determines a processing procedure, and controls each section. Register 13 is a register used when inputting data into memories 1 and 2 at an initial stage, and 300 indicates the input end of the input.

200 indicates the read data output end of this system.

In the dual memory system based on the conventional technology described above, if there is an error in memory data, the memory will be switched, but the address where the error data was output (the above-mentioned current memory address (X+)) will be unusable and will be used as a backup. There is a problem that address (xz)L of memory 2 cannot be used and is not duplicated, reducing the reliability of the memory system.

(d) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a system in which there is an error in the data output of one memory, and after switching to the other memory, normal data is written again to one memory, reducing the reliability of the duplex memory system. The purpose is to prevent

(e) Structure of the Invention In a duplex memory system, the present invention detects an error in the data output of one memory and switches to the other memory, and then confirms that the data output of the other memory is normal. This system automatically saves the normal data to one memory, and satisfactorily achieves the above-mentioned purpose.

(f) Embodiment of the Invention FIG. 2 shows an entire system diagram of an embodiment of the duplex memory system according to the present invention. Reference numerals in FIG. 2 that are the same as those in FIG. 1 have the same functions as in FIG.

Reference numeral 7 denotes a processing control section whose internal components are almost the same as the processing control section 6 shown in FIG. 1, except that a function for controlling the data switching section 9 according to the present invention is added. This 8-digit semi-permanent storage device also has an internal structure of approximately four rods compared to the semi-permanent storage device 6 of FIG. 1, but differs in that a memory recovery process is added to the microprogram due to an accident.

In FIG. 2, when the data at the address (Xl) of the current memory 1 retrieved by the data read instruction is determined to be an error by the error detection unit 4, the error signal is transmitted to the error detection unit 4.
More processing AI1! The memory switching unit 3 processes the program according to the program sent to the control unit 7 and stored in the semi-permanent storage device 8.
11, the data at the address (Xl) of the spare memory 2 is transferred to the data reading register 12 by the address register 11, and the error detection unit 4 is instructed to change the address (Xl) from the memory 1 to the spare memory 2. Have students check the lyrics of the B1 data.

Although the above is similar to the prior art, the subsequent processing is the content of the present invention.

The data output from the switched spare memory is sent to the error detection unit 4 as described above, and is checked and confirmed to be normal.The data output is sent to the error detection unit 4 and is then checked by the processing control unit according to instructions from the microprogram stored in the second half fixed storage device 8. 7 instructs the memory switching unit 3 to switch the current memory 1 to a state in which data can be written, and instructs the data switching unit 9 to switch to a state in which input data can be input to the data writing register 13; the data reading register 12; The normal data is transferred to the data write register 13 and the address (xl) is specified to the address register 11.
Write normal data to address (X+) of current memory 1.

As described above, the address (Xl) of the current memory 1 stores normal data and the duplication of the own memory is maintained.

(g) Effects of the Invention According to the present invention, in a dual memory system consisting of a current memory and a spare memory, even if there is an error in the read data of one memory and the data is switched to the other memory, the data in one memory is Since normal data is immediately and automatically written, memory redundancy is always maintained and memory reliability is ensured, which has a great effect on improving the reliability of electronic computers1.

[Brief explanation of drawings]

FIG. 1 shows a system diagram of a 24-white himemory stem according to the prior art, and FIG. 2 shows a system diagram of an embodiment of a duplex memory system according to the present invention. The same reference numerals indicate the same objects throughout the figures; 1 is the current memory, 2 is the spare memory, and 3 is the memory switching unit. 4 is a digit error detection section, and 5 is a processing control section based on the prior art. 6 is a semi-permanent storage 4AN according to the prior art; 7 is a processing control unit according to the present invention; 8 is a semi-permanent storage device repair according to the present invention; 9
Figure 2 is a data cutting section according to the present invention.

Claims (1)

[Claims] In a redundant computer memory system that has a working memory and a spare memory and performs memory switching by detecting errors in read data, an error occurs in the read data from a specific address in either the working memory or the spare memory. If there is an error, switch to the other memory, read the data from the specific address of the memory, confirm that there is no error in the data, and then check that there is no error in the specific address of the one memory that outputs the error data. A dual memory system characterized in that data from a specific address of the other memory is automatically written.