JPS62166456A - Information processor - Google Patents

Abstract

PURPOSE:To perform processing without losing any data even in case of main memory trouble by making part or the whole of a main memory duplex. CONSTITUTION:This information processor has a function which makes the main memory 7 duplex in page units and also has an address conversion table 2 for converting one logical address into a different physical address (real address). Data are normally written in both primary and secondary memories and read of the primary memory firstly. Consequently, if trouble occurs when the memory 7 to be made duplex is accessed, the secondary memory can be reread at a readout request and the process is carried on even in case of the trouble of the memory 7.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to an information processing device using a virtual storage method.

Regarding location.

[Background of the invention] 15 Conventional measures against main memory failure.

Since then, error detection and correction (ECC) functions have become popular.

It is used. Furthermore, in the event of a fixed failure, the connection will be made.

Part of the buffer memory is used as replacement memory.

A technique (Japanese Unexamined Patent Application Publication No. 1983-ss734) is also known.

However, the conventional technology has a 1-bit error.

Correctable data errors such as 2-bit errors.

This is useful when an error occurs, but other main notes.

This has the disadvantage that a failure (address error, error 5 of !1 btt or more) cannot be repaired.゛ [Object of the Invention] The object of the present invention is to provide a main memory in part or in its entirety.

By duplicating the memory, it can also be used in the event of a main memory failure.

An object of the present invention is to provide an information processing device capable of processing without losing data.

[Summary of the invention]

The information processing device of the present invention has a function of duplicating each page on the main memory, and for each logical address, there are 15 different physical addresses (real addresses). Convert to

have a table with Normally, writing is done in primer 1c.

Reads are performed on both secondary memories.

No row from primary memory, failure in read operation.

When this occurs, the secondary memory is replaced with a memo.

It is characterized by being used as a [Embodiments of the Invention] The present invention will be described below with reference to the drawings. Fig. 1 shows a schematic diagram of the system configuration of the present invention.1
is a register with a local memory address generated by the program, and 2 is a logical register.

Address to convert address 101 to real address.

This is a conversion table. Here, 102 indicates that the page exists on the main memory. V (1, 103' indicates the page real address for the primary memory, and 1o1f' indicates that the page is duplicated on the main memory.

The bit v1.105 indicating this is valid only when V1=1 and is the real page address for secondary memory.4.5
are the access address registers of the primary memory and secondary memory found by searching the address conversion table 2, 3 is the store data register, and 6 is the memory control register.

The device 7 is the main memory.

FIG. 2 shows the relationship between Vo and vl. .

When V,=O, the page is absent. VO=I TV,
The case of =200 indicates that the page is not duplicated on the main memory. In the case of V,=V1=1°, the page is duplicated in the main memory.

= 300
301 is a memory access generation circuit, and 301 is an output of vl.

Force holding latch, 302 requests to main memory: 31
2 is a rhythmist code indicating the content of the request.

It is de. 303 indicates a store request, V1=11#
When the value is 10, the AND circuit 305 is established and the memory becomes the main memory.

308 instructs to write store data 311 to memory addresses 309 and 310 at 11#
become.

It is. 401 doubles the store data in the main memory.

A register indicating that the request is a write request.

401 is a request to the main memory, and 402 is a request.

String code, 404, 405 are primary, seven cans,
.

Dali memory address 406 is store data register.

It's a star. 407 is request code decoding.

In da, output 408 of 407 is read request, 4o9
゜ indicates a write request. 410 is.

The OR circuits 411 and 412 are AND circuits. 41
35 is a main memory access control unit, and 414 is a main memory.

These are read data registers. When memory duplication request 401='1# in a write request.

Addresses 404 and 405 are AND circuits 411 and 41
2 is.

Since it holds, it is stored independently in the main memory (415, 41610
) sent. At the same time, the control unit 413

Control information for heavy writing is issued to the main memory.

Read data from main memory using only .

If a failure occurs during read processing, instruction processing is performed.

The unit 300 sets the 304 to the main memory.

Reissue the read request. The memory to read from.

If it is duplicated, V1 = ' 1 #, so select.

The secondary memory address is determined by the lid circuit 307.

is selected, and when rereading, the secondary memory is accessed.

〔Effect of the invention〕

According to the present invention, if a failure occurs when accessing the main memory 5 of the duplication target area, the readout is performed.

Since the secondary memory read can be re-executed in the request, it is possible to continue processing even in the case of a main memory failure.

Furthermore, rather than duplicating the entire area, some important areas can be designated and duplexed, which has the effect of reducing hardware costs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing 15 meanings of valid bits VO+Vl in an address translation table, and FIG. 102...Indicates that the page exists on main memory. Bit,
2゜103...Page real address for primary memory = 104...Double display bit, 105...Page real address for secondary memory 1. 21. 30. Control # device) Bo8 3o2. 3+2 3o'/
JIQ 3ur −'−−−−−−1−−−
-------Co1 401 Ichi2 403
4o4 #4CX5'EG1

Claims (1)

[Claims] 1. A main memory, an address conversion table that generates first and second physical addresses that indicate different memory areas on the main memory for one logical address, and the main memory. a check circuit that checks data read from the main memory, and when reading data from the main memory, first reads data in an area specified by the first physical address, and the check circuit detects an abnormality in the data; and a control circuit that reads data in an area indicated by the second physical address. 2. The information processing apparatus according to claim 1, wherein the address conversion table includes a flag indicating whether or not the second physical address is invalid. 3. In claim 2, the control circuit:
When writing data to the main memory, if the flag indicates that the second physical address is invalid, the information processing device writes the data to an area designated by the first physical address. 4. In claim 2, when the control circuit writes data to the main memory, the flag is set to the second
When the physical address indicates that the physical address is valid, the information processing device writes data to both areas indicated by the first and second physical addresses, respectively.