KR100715701B1 - Circuit for recovering a clock and data using a phase detector using a 4x-over sampling scheme and method therof - Google Patents

Abstract

According to the present invention, a clock / data recovery circuit using a 4x oversampling phase detector generates a multi-phase clock having a clock period and a clock interval in consideration of the speed of the input data in order to oversample the 4x input data. 4 times oversampling the input data in correspondence to a multi-phase clock, and logic processing in a set manner using the 4 times oversampled data to output an output clock phase of 1/2 times the input data phase and the data rate. To restore the data.

Clock Recovery Circuit, 4x Oversampling, Phase Detector, D-Flip Flop, UP / DOWN Signal

Description

CIRCUIT FOR RECOVERING A CLOCK AND DATA USING A PHASE DETECTOR USING A 4X-OVER SAMPLING SCHEME AND METHOD THEROF}             

1 is a schematic diagram of a clock / data recovery circuit using a 4X oversampling phase detector in accordance with an embodiment of the present invention.

2 is a schematic diagram illustrating a four-speed phase detector structure.

3 is a timing diagram illustrating a multi-phase clock output from the clock generator of FIG. 2.

FIG. 4 is a state table showing data states that can be input to the up / down controller of FIG. 2 when data and clocks are locked; FIG.

FIG. 5 is a state table illustrating a synchronization state between data and a clock output from the up / down controller of FIG. 2; FIG.

FIG. 6 schematically illustrates the internal structure of the up / down controller of FIG.

7 schematically illustrates an oversampling interval for one bit in accordance with an embodiment of the invention.

8 is a timing diagram illustrating a relationship between input data, reconstructed data, and a reconstructed clock when reconstructing clocks and data by using a 4X oversampling phase detector according to an embodiment of the present invention.

FIG. 9 is a timing diagram showing a relationship between the decompression data and the decompression clock of FIG. 8; FIG.

<Description of the symbols for the main parts of the drawings>

110; Clock generator 120; 1: 4 samplers

130: parallel D-flip flop 140: up / down controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock / data recovery circuit and a control method thereof. In particular, the present invention relates to a clock / data reconstruction using a phase detector (PD) using a 4X-over sampling method. A data recovery circuit and a control method thereof are provided.

In general, the clock / data recovery circuit may not be able to support the data transfer rate because the clock / data recovery circuit may not support the data transfer rate. In particular, the clock / data recovery circuit may not be able to support the data transfer rate. I have a problem. Thus, the problem occurs because the operation speed of the clock / data recovery circuit does not support the data transfer rate. In particular, data distortion occurs because the bandwidth of the channel does not support the data transfer rate during high-speed data transfer. In general, oversampling is used to solve the problem.

The clock / data recovery circuit using the oversampling scheme selects an appropriate value from among oversampled data, but the clock / data recovery circuit using a phase picking scheme and the oversampled value. This is divided into a clock / data recovery circuit using a phase tracking data recovery method that performs data recovery while performing phase tracking through feedback.

 A clock / data recovery circuit using the phase tracking data recovery method will be described.

The clock / data recovery circuit using the phase tracking data recovery method receives only data from an external source and must recover the actual data and the clock using only the input data. Since only the data input from the outside has to recover the data and clock, sufficient data transition, fast locking time, and stability are required.

As described above, in the clock / data recovery circuit using the phase tracking data recovery scheme, a synchronization process between the input data and the multi-phase clock for oversampling is necessary.

 In the clock / data recovery circuit using the phase tracking data recovery method, since only the data is received from the outside and the clock and data are recovered, the chip area can be reduced and power consumption can be reduced.

However, in the clock / data recovery circuit using the phase tracking data recovery method, since only the data is received and the clock and data are restored, data having a continuous value of '1' or data having a continuous value of '0' is used. In order to restore the data, a predetermined pattern may be inserted and input during data input, or a preamble sequence may be transmitted at the initial data input.

Inserting the configuration pattern or transmitting the preamble sequence results in an increase in chip area and power consumption.

In addition, in the clock / data recovery circuit using the phase tracking data recovery method, since only the data is received to recover the clock and the data, the number of oversampling must also be increased to detect the correct data transition and to restore the continuous data. However, the increase in the number of oversampling is a factor that increases the area of the chip when considering the block generating the multi-phase clock.

In the proposed clock / data recovery circuit to date, it is generally preferable to use a 3X (3X) oversampling scheme, and it has already been proved that a relatively stable result is obtained.

In particular, recently, a clock / data recovery circuit using a feedback tracking phase tracking data recovery scheme using a double speed (2X) oversampling scheme has been proposed. In the clock / data recovery circuit using the feedback tracking phase tracking data recovery method using the double speed over sampling method, the clock / data recovery circuit using the phase tracking data recovery method using the normal double speed over sampling method may be used. When using the double-speed oversampling method, it is difficult to detect whether the data is transitioned and an error occurs when restoring the data by jitter, but the feedback method is used, but the complexity of the feedback method is applied. Has a problem that is high.

Thus, there is a need for a new clock / data recovery circuit that has gains in complexity, chip area, power consumption and reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a clock / data recovery circuit and a control method thereof using a phase tracking data recovery scheme having a minimum complexity.

Another object of the present invention is to provide a clock / data recovery circuit and a control method thereof using a phase tracking data recovery scheme that guarantees maximum stability.

A clock / data recovery circuit using the 4x speed oversampling phase detector according to the present invention for achieving the above object comprises a clock period and a clock interval in consideration of the speed of the input data in order to oversample the input data at 4x speed. A clock generator for generating a multi-phase clock having: A quadruple oversampler phase detector comprising a 1: 4 sampler that quadruple oversamples the input data corresponding to the multi-phase clock; A phase frequency detector for equalizing the frequency of the VCO output clock with the reference clock signal at 1/2 the data rate; First and second charge pumps connected to outputs of the quadruple oversampler phase detector and phase frequency detector to adjust a voltage for adjusting the frequency of the VCO; A lock detector which locks the first and second charge pumps by detecting whether the frequency is the same by comparing a reference clock signal and an output signal for initially holding a frequency of input data; And a D-flip-flop for generating reconstructed data, wherein the 1: 4 sampler oversamples two consecutive bits of data of the input data at four times in synchronization with the multi-phase clock.

A control method of a clock / data recovery circuit using a 4x oversampling phase detector according to the present invention for achieving the above object is a control method of a clock / data recovery circuit using a 4x speed oversampling phase detector. Generating a multi-phase clock having a clock period and a clock interval in consideration of the speed of the input data in order to oversample the input data at 4 times; A second step of oversampling 2 consecutive bits of data of the input data in synchronization with the multi-phase clock; A third step of maintaining the same state for a predetermined period of the previous half of oversampling data among the four times oversampled data and outputting the same; A fourth process of outputting the following half of oversampling data among the four times oversampled data while maintaining the same state for the set period; A fifth step of performing a logic operation on the output signals in the third and fourth processes in a preset manner, and then adjusting up or down the period of the multi-phase clock according to a result of the logic operation; Include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

The present invention proposes a clock / data recovery circuit using a phase tracking data recovery scheme and a control method thereof. In particular, the present invention recovers clock and data using a phase detector (PD) using a 4X-over sampling method in a clock / data recovery circuit using a phase tracking data recovery method. A circuit and a control method thereof are proposed.

FIG. 1 is a diagram schematically illustrating a clock / data recovery circuit using a 4X oversampling phase detector according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the data recovery circuit is composed of two loops, a frequency adjusting loop and a phase adjusting loop. In other words, the frequency of the reference clock (Ref_CLK) signal and the voltage controlled oscillator (VCO) 70 output clock, which is 1/2 of the data rate, is changed using a phase frequency detector (PFD) 10. The frequency adjustment loop and the input data to be equal are phase loops for adjusting the phase through the quadruple speed oversampler phase detector 50.

In the frequency loop, if information indicating that the VCO frequency and the reference frequency are the same through the PFD 10, the charge pump 20a, and the filter 30 is detected, that is, the oversampled data output from the 4X oversampling phase detector 50 Is given as four consecutive values such as '1111' or '0000', the charge pump 20a, which is a voltage control device of the frequency loop, is operated through a lock detector 40 implemented as a finite state machine (FSM). The VCO 70 is operated by changing the control voltage of the VCO until the phase coincides with the phase loop. The data is recovered by using a clock signal whose phase of the input data and the VCO clock match. In this case, the frequency of the VCO 70 is set to 1/2 of the input data rate and uses a double-edge D flip-flop 60 that catches data twice on the rising and falling edges of the clock.

2 is a block diagram of a phase detector used;

As shown, a clock generator 110, a 1: 4 sampler 120, a parallel D-flip-flop 130, and an up / down controller 140, and the parallel D-flip-flop 130 is composed of two D-flip-flops (131, 133).

First, in order to oversample input data, for example, 1.2 [Gbps] input data, the multiphase clock has 625 [MHz] and the interval between clocks is generated at 200 [ps]. Should be.

Accordingly, the clock generator 110 has 625 [MHz] and has a total of eight clocks, that is, clk 0, clk 0_b, clk 1, clk 1_b, and clk 2 so that the interval between clocks is 200 [ps]. A total of eight clocks of clk 2_b, clk 3, and clk 3_b are generated and output to the 1: 4 sampler 120 and the parallel D-flip flop 130. Here, the clock generator 110 is implemented as a voltage controlled oscillator having a ring structure, and is the same component as the VCO 70 of FIG. 1.

The 1: 4 sampler 120 oversamples 1.2 [Gbps] input data, that is, differential data, at 4 times the clock corresponding to the clock output from the clock generator 110.

In this case, the 1: 4 sampler 120 samples two consecutive bits of data in order to obtain information about the transition and synchronization of the input data and the clock generated by the clock generator 110. The sampler 120 has a total of eight clocks output from the clock generator 110, that is, clk 0, clk 0_b, clk 1, clk 1_b, clk 2, clk 2_b, clk 3, and clk. A total of eight clocks of 3_b are input, and the 1: 4 sampler 120 samples eight sampling data corresponding to the eight clocks and outputs the sampling data to the parallel D-flip flop 130.

Four of the eight sampling data output from the 1: 4 sampler 120 are input to the D-flip flop 131, and the remaining four sampling data are input to the D-flip flop 133. The D-flip flop 131 operates in synchronization with the clock clk 2_b output from the clock generator 100, and the D-flip flop 133 is synchronized with the clock clk 2 output from the clock generator 110. It works.

Since the D-flip flop 131 and the D-flip flop 133 are set in the rising edge manner, the D-flip flop 131 and the D-flip flop 133 remain the same for one period with respect to the data input from the 1: 4 sampler 120.

Therefore, the output signal of the parallel D-flip-flop 130 is a differential signal, resulting in 16 oversampling data, namely D0, D0_b, D1, D1_b, D2, D2_b, D3, D3_b, D4, D4_b, D5, D5_b, D6, D6_b, D7, and D7_b are outputted to the up / down controller 140.

The up / down controller 140 performs a logical operation on the input data and generates an up / down signal corresponding to the result of the logical operation.

As a result, the current amount of the charge pump is adjusted according to the up / down signal output from the up / down controller 140.

In FIG. 2, a clock / data recovery circuit using a phase detector using a 4x oversampling method according to an exemplary embodiment of the present invention has been described. Next, the output from the clock generator 110 of FIG. 2 is described with reference to FIG. 3. The multi-phase clock will be described.

3 is a timing diagram illustrating a multi-phase clock output from the clock generator 110 of FIG. 2.

The multi-phase clock shown in FIG. 3 is a multi-phase clock for oversampling 1.2 [Gbps] input data at 4 times, with a clock period of 625 [MHz] and 200 [ps] between clocks. Four bits of oversampling data are generated by oversampling one bit of input data at four times the corresponding multi-phase clock.

In FIG. 3, the multi-phase clock output from the clock generator 110 of FIG. 2 has been described. Next, when the data and the clock are locked with reference to FIG. 3, the up / down controller 140 of FIG. 2 is locked. The data states that can be input to the following will be described.

FIG. 4 is a state table illustrating data states that can be input to the up / down controller 140 of FIG. 2 when data and a clock are locked.

T shown in FIG. 4 represents a data pattern inputtable to the up / down controller 140, and F shown in FIG. 4 represents a data pattern impossible to input to the up / down controller 140. FIG.

That is, as shown in FIG. 5, when oversampling data is equal to '0010', '1' is impossible to generate when the oversampling is correctly performed. As a result, only eight data patterns of the sixteen data patterns illustrated in FIG. 4 become data patterns input to the up / down controller 140.

In FIG. 4, the data state that can be input to the up / down controller 140 of FIG. 2 when the data and the clock are locked has been described. Next, the data and the clock output from the up / down controller 140 will be described with reference to FIG. 5. The synchronization state of the liver will be described.

FIG. 5 is a state table illustrating a synchronization state between data and a clock output from the up / down controller 140 of FIG. 2.

In FIG. 5, it is possible to determine a boundary between data between the oversampling data D3 and the oversampling data D4. In FIG. 4, a lock state indicates a state in which data and a clock are synchronized, and a data> clock state indicates a state in which data is faster than a clock, and a data <clock state. Indicates a state where the clock is faster than the data. The oversampling data D0 to D3 represent oversampling data for one preceding data among two consecutive data, and the oversampling data D4 to D7 are over for one subsequent data among two consecutive data. Indicates sampling data.

As a result, all data can be regarded as differential data, which must increase the frequency of the clock if the data is faster than the clock, and decrease the frequency of the clock if the data is slower than the clock.

Accordingly, the up / down controller 140 of FIG. 2 outputs an up signal or a down signal depending on the relationship between the data and the clock, that is, whether the data is faster than the clock or the clock is faster than the data. The up signal and the down signal become signals for adjusting the amount of current in the charge pump.

In FIG. 5, a synchronization state between data and a clock output from the up / down controller 140 of FIG. 2 has been described. Next, an internal structure of the up / down controller 140 of FIG. 2 will be described with reference to FIG. 6. Let's explain.

FIG. 6 is a diagram schematically illustrating an internal structure of the up / down controller 140 of FIG. 2.

Referring to FIG. 6, the up / down controller 140 includes a plurality of NAND logic gates 511, 513, 515, and 517, and a plurality of OR logic gates 519, 521. When the value according to the synchronization state between the eight data and the clock as described in FIG. 4 is input to the up / down controller 140, that is, the oversampling data D0 to D3 are overwritten to the NAND logic gates 511 and 513. Sampling data D4 through D7 are input to NAND logic gates 515 and 517.

The NAND logic gate 511 performs a NAND logic operation on the input oversampling data to the OR logic gate 519, and the NAND logic gate 513 performs a NAND logic operation on the input oversampling data to the OR logic. Outputs to the gate 521, the NAND logic gate 515 performs NAND logical operation on the input oversampling data, and outputs the result to the OR logic gate 519, and the NAND logic gate 517 inputs the oversampling data. NAND performs a logical operation on the OR logic gate 521.

Then, the OR logic gate 519 inputs the signals output from the NAND logic gate 511 and the NAND logic gate 515 and performs OR logic operation on the signals output from the NAND logic gate 511 and the NAND logic gate 515. A signal output from the NAND logic gate 513 and the NAND logic gate 517 is inputted, and OR-calculated to output a DOWN signal.

In FIG. 6, an internal structure of the up / down controller 140 of FIG. 2 has been described. Next, an oversampling interval for one bit according to an embodiment of the present invention will be described with reference to FIG. 7.

7 is a diagram schematically illustrating an oversampling interval for one bit according to an embodiment of the present invention.

Referring to FIG. 7, the oversampling interval is 200 [ps] when the 4x oversampling method is used, and the oversampling interval is 160 [ps] when the 5x oversampling method is used. Is used, the oversampling interval is 266.6 [ps]. That is, when using the 4x oversampling method, the oversampling interval is 200 [ps]. When oversampling more than 4 times or less than 4 times for one bit, the clock / data recovery method proposed by the present invention can be used. It becomes impossible.

In FIG. 7, an oversampling interval for one bit according to an embodiment of the present invention has been described. Next, a clock using a phase detector using a quadruple speed oversampling scheme according to an embodiment of the present invention will be described with reference to FIG. 8. And when restoring data, the relationship between input data, restoration data, and a restoration clock is demonstrated.

8 is a timing diagram illustrating a relationship between input data, reconstructed data, and a reconstructed clock when a clock and data are reconstructed using a phase detector using a 4x oversampling scheme according to an exemplary embodiment of the present invention.

As shown in FIG. 8, when the clock and the data are recovered by using the phase detector using the 4X oversampling method according to the embodiment of the present invention, it can be seen that the input data and the restored data are almost exactly matched. It can be seen that the recovery clock also has an interval of 200 [ps].

8 illustrates the relationship between the input data, the reconstruction data, and the reconstruction clock when the clock and the data are reconstructed by using the phase detector using the quadruple speed oversampling method according to an embodiment of the present invention. A relationship between the decompression data and the decompression clock of FIG. 7 will be described with reference to FIG. 9.

FIG. 9 is a timing diagram illustrating a relationship between the decompression data and the decompression clock of FIG. 8.

As shown in Fig. 9, it can be seen that the synchronization is almost exactly matched between the actual recovered data and the recovered clock.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention recovers clock and data by using a phase detector using a 4x oversampling method in a clock / data recovery circuit using a phase tracking data recovery method, thereby providing input data and a clock using only a relatively simple logical operation. It has the advantage of being able to synchronize exactly.

In addition, the present invention has the advantage that it is possible to detect a continuous '1' or a continuous '0' data without the addition of additional circuitry and a separate set pattern. In addition, the present invention can generate an up or down signal through a logic operation to turn off the charge pump when the data and the clock are synchronized, so that the charge pump after the data and the clock are synchronized is provided in addition to the leakage current caused by the transistor. There is an advantage that the power consumption can be minimized because no other power consumption occurs.

Claims (9)

A clock generator for generating a multi-phase clock having a clock period and a clock interval in consideration of the speed of the input data in order to oversample input data at 4 times the speed; A quadruple oversampler phase detector comprising a 1: 4 sampler that quadruple oversamples the input data corresponding to the multi-phase clock; A phase frequency detector for equalizing the frequency of the VCO output clock with the reference clock signal at 1/2 the data rate; First and second charge pumps connected to outputs of the quadruple oversampler phase detector and phase frequency detector to adjust a voltage for adjusting the frequency of the VCO; A lock detector which locks the first and second charge pumps by detecting whether the frequency is the same by comparing a reference clock signal and an output signal for initially holding a frequency of input data; And D-flip-flop to create reconstruction data; And the 1: 4 sampler oversamples the data of the 2 consecutive bits of the input data at 4 times in synchronization with the multi phase clock. 4. The method of claim 1, wherein the 4X oversampler phase detector Input the preceding 1/2 oversampling data of the 4x oversampled data in the 1: 4 sampler, and over the preceding 1/2 of the input 4x oversampled data for a preset period. A first D-flip flop for maintaining and outputting the same state with respect to the sampling data; Inputs 1/2 oversampling data that is trailing among the 4x oversampled data in the 1: 4 sampler, and oversamples 1/2 that is trailing among the 4x speed oversampled data during the set period. A second D-flip flop for maintaining and outputting the same state for the data; After performing a logic operation in a preset manner by inputting the signals output from the first D-flip flop and the second D-flip flop, the period of the multi-phase clock is up or down according to a result of the logic operation. Up / down controller for adjusting by adjusting; Clock / data recovery circuit using a 4x over-sampling phase detector characterized in that it comprises a. The method of claim 2, And the clock generator is implemented as a voltage controlled oscillator having a ring structure. delete The method of claim 2, The up / down controller; First and second NAND logic gates configured to input a signal output from the first D-flip flop to perform a NAND logic operation; Third and fourth NAND logic gates configured to input a signal output from the second D-flip flop to perform a NAND logic operation; A first OR logic gate configured to input an output signal from the first NAND logic gate and a third NAND logic gate to perform an OR logic operation to output the up signal; And a second OR logic gate configured to input the signals output from the second NAND logic gate and the fourth NAND logic gate to perform an OR logic operation to output the down signal. Clock / data recovery circuit using. The clock / data recovery circuit of claim 1, further comprising a filter at an output terminal of the first and second charge pumps. In a control method of a clock / data recovery circuit using a quadruple speed oversampling phase detector, Generating a multi-phase clock having a clock period and a clock interval in consideration of the speed of the input data in order to oversample the input data at the 4x speed; A second step of oversampling 2 consecutive bits of data of the input data in synchronization with the multi-phase clock; A third step of maintaining the same state for a predetermined period of the previous half of oversampling data among the four times oversampled data and outputting the same; A fourth process of outputting the following half of oversampling data among the four times oversampled data while maintaining the same state for the set period; A fifth step of performing a logic operation on the output signals in the third and fourth processes in a preset manner, and then adjusting up or down the period of the multi-phase clock according to a result of the logic operation; A control method of a clock / data recovery circuit using a 4x oversampling phase detector, characterized in that it comprises a. delete The method of claim 7, wherein After performing a logic operation on the output signals in the third process and the fourth process in a predetermined manner, the fifth process of adjusting the period of the multi-phase clock up or down according to the result of performing the logic operation A sixth step of performing a NAND logic operation by inputting a signal output in the third step; A seventh step of performing a NAND logic operation by inputting a signal output in the fourth step; And an eighth process of performing an OR logic operation on the signals output in the sixth and seventh steps in advance to output the signals as the up signal or the down signal. Method of controlling a clock / data recovery circuit using a phase detector.

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