KR102178473B1 - Thin Film Transistor Substrate And Display Using The Same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate, and a display device using the same. The thin film transistor substrate according to the present invention includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is disposed on a substrate and includes a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode. The second thin film transistor is disposed on the substrate and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode overlaps the polycrystalline semiconductor layer with the gate insulating film therebetween. An intermediate insulating film containing a nitride film is disposed on the first gate electrode. The second gate electrode is disposed on the intermediate insulating film covering the first gate electrode. An oxide layer covering the second gate electrode is disposed on the intermediate insulating layer. The oxide semiconductor layer is disposed on the oxide film so as to overlap the second gate electrode. The first source electrode and the first drain electrode are disposed between the intermediate insulating film and the oxide film. The second source electrode and the second drain electrode are disposed over the oxide semiconductor layer.

Description

Thin Film Transistor Substrate And Display Using The Same

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate, and a display device using the same.

As the information society develops, demands for display devices for displaying images are increasing in various forms. The display device field has rapidly changed to a flat panel display device (FPD) that is thin, light, and capable of large area, replacing a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED).

In the case of an active liquid crystal display device, an organic light emitting display device, and an electrophoretic display device, a thin film transistor substrate including a thin film transistor allocated in a pixel region arranged in a matrix manner is disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. An organic light-emitting display device displays an image by forming an organic light-emitting device on the pixels themselves arranged in a matrix manner.

The organic light emitting diode display is a self-luminous device that emits light by itself, and has a fast response speed, and has great luminous efficiency, luminance, and viewing angle. In particular, the organic light emitting diode display (OLEDD) using the characteristics of an organic light emitting diode with excellent energy efficiency includes a passive matrix type organic light emitting diode display (PMOLED) and It is broadly classified as an active matrix type organic light emitting diode display (AMOLED).

As personal electronic devices become more active, display devices are also being developed as products having excellent portability and/or wearability. As described above, in order to be applied to a portable or wearable device, a display device implementing low power consumption is required. There is a limit to realizing low power consumption with technologies related to display devices developed so far.

An object of the present invention is to provide a thin film transistor substrate including two or more types of thin film transistors on the same substrate and a display device using the same as an invention conceived to solve the problems of the prior art. Another object of the present invention is to provide a thin film transistor substrate in which two or more types of thin film transistors are formed through an optimized manufacturing process and a minimized mask process, and a display device using the same.

In order to achieve the above object, a display device according to the present invention includes a first thin film transistor, a second thin film transistor, an intermediate insulating film, and an oxide film. The first thin film transistor includes a polycrystalline semiconductor layer, a first gate electrode disposed over the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode. The second thin film transistor includes a second gate electrode, an oxide semiconductor layer disposed on the second gate electrode, a second source electrode, and a second drain electrode. The intermediate insulating layer is disposed on the first gate electrode and includes a nitride layer. The oxide film is disposed on the intermediate insulating film and covers the second gate electrode. The oxide semiconductor layer is disposed on the oxide film so as to overlap the second gate electrode. The first source electrode, the first drain electrode, and the second gate electrode are disposed between the intermediate insulating layer and the oxide layer. The second source electrode and the second drain electrode are disposed over the oxide semiconductor layer.

For example, it further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, it further includes a gate insulating film covering the polycrystalline semiconductor layer. The first gate electrode is disposed on the gate insulating film and overlaps the polycrystalline semiconductor layer.

For example, the second thin film transistor is a switch element for selecting a pixel. The first thin film transistor is a driving element that drives the organic light emitting diode of a pixel selected by the second thin film transistor.

For example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs a data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs scan pulses to the gate wiring. Any one of the first thin film transistor and the second thin film transistor is included in one of the multiplexer and the gate driver.

For example, the first source electrode is connected to one side of the polycrystalline semiconductor layer through a source contact hole penetrating the intermediate insulating layer and the gate insulating layer. The first drain electrode is connected to the other side of the polycrystalline semiconductor layer through a drain contact hole penetrating the intermediate insulating film and the gate insulating film. The second source electrode is in contact with one side of the oxide semiconductor layer. The second drain electrode is in contact with the other side of the oxide semiconductor layer.

For example, the first source electrode and the first drain electrode include the same material as the second gate electrode.

As an example, the second gate electrode is connected to the gate wiring including the same material as the first gate electrode through a gate contact hole penetrating the intermediate insulating layer.

For example, the second source electrode is connected to a data line including the same material as the second gate electrode through a data contact hole penetrating the oxide layer.

As an example, the intermediate insulating layer further includes a lower oxide layer.

For example, a nitride film is disposed on the lower oxide film.

Further, the display device according to the present invention includes a first semiconductor layer, a gate insulating film, a first gate electrode, an intermediate insulating film, a second gate electrode, a first source electrode, a first drain electrode, an oxide film, a second semiconductor layer, and a second semiconductor layer. And a source electrode and a second drain electrode. The first semiconductor layer contains a polycrystalline semiconductor material. The gate insulating film covers the first semiconductor layer. The first gate electrode overlaps the first semiconductor layer on the gate insulating layer. The intermediate insulating layer covers the first gate electrode and includes a nitride layer. The second gate electrode, the first source electrode, and the first drain electrode are disposed on the intermediate insulating layer. The oxide film covers the second gate electrode, the first source electrode, and the first drain electrode. The second semiconductor layer is disposed on the oxide layer so as to overlap the second gate electrode, and includes an oxide semiconductor material. The second source electrode and the second drain electrode are disposed on the second semiconductor layer.

For example, the first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in the first thin film transistor. The second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in the second thin film transistor.

For example, it further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, the second thin film transistor is a switch element for selecting a pixel. The first thin film transistor is a driving element that drives the organic light emitting diode of a pixel selected by the second thin film transistor.

For example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs a data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs scan pulses to the gate wiring. Any one of the first thin film transistor and the second thin film transistor is included in one of the multiplexer and the gate driver.

For example, the first source electrode is connected to one side of the first semiconductor layer through a source contact hole penetrating the intermediate insulating layer and the gate insulating layer. The first drain electrode is connected to the other side of the first semiconductor layer through a drain contact hole penetrating the intermediate insulating film and the gate insulating film. The second source electrode is in contact with one side of the second semiconductor layer. The second drain electrode is in contact with the other side of the second semiconductor layer.

For example, the first source electrode and the first drain electrode include the same material as the second gate electrode.

For example, the second gate electrode is connected to a gate wiring including the same material as the first gate electrode disposed on the gate insulating layer through a gate contact hole penetrating the intermediate insulating layer.

For example, the second source electrode is connected to a data line including the same material as the second gate electrode disposed on the intermediate insulating layer through a data contact hole penetrating the oxide layer.

As an example, the intermediate insulating film further includes a lower oxide film.

For example, a nitride film is disposed on the lower oxide film.

The thin film transistor substrate and the display device using the same according to the present invention may have a characteristic that two different types of thin film transistors are formed on the same substrate, and the other thin film transistor compensates for the disadvantages of one thin film transistor. In particular, by providing a thin film transistor having a low-speed driving characteristic, it is possible to provide a display device suitable for portable and/or wearable devices by reducing power consumption.

1A is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention.
1B is a cross-sectional view illustrating a connection structure between a data line and a source electrode, and a gate line and a gate electrode in FIG. 1A.
2 is a flow chart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to the first embodiment of the present invention.
3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including thin film transistors of different types according to a second embodiment of the present invention.
4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a second embodiment of the present invention.
5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.
6 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a third embodiment of the present invention.
7 is a block diagram schematically showing a configuration of a display device according to a first application example of the present invention.
8 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device of a horizontal electric field type according to a second application example of the present invention.
9 is a cross-sectional view of the thin film transistor substrate shown in FIG. 8 taken along line II′.
10 is a plan view showing a structure of one pixel in an active matrix organic light emitting diode display according to a third application example of the present invention.
FIG. 11 is a cross-sectional view showing the structure of an active matrix organic light emitting diode display taken along line II-II' in FIG. 10;
12 is an enlarged plan view showing a schematic structure of an organic light emitting diode display according to a fourth application example of the present invention.
FIG. 13 is a cross-sectional view showing the structure of an organic light emitting diode display according to the prior art, taken along line III-III' in FIG. 12;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numerals throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of preparation of the specification, and may be different from the names of parts of an actual product.

A thin film transistor substrate for a flat panel display device according to the present invention includes a first thin film transistor disposed in a first region and a second thin film transistor disposed in a second region on a glass substrate. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner. Display elements for a display function are disposed in the display area. The non-display area is disposed around the display area, and driving elements for driving display elements formed in the display area may be disposed.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first thin film transistor and the second thin film transistor may be disposed far apart. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel region, the first thin film transistor and the second thin film transistor may be disposed adjacent to each other.

Polycrystalline semiconductor materials have high mobility (100cm2/Vs or more), low energy consumption, and excellent reliability, so they can be applied to gate drivers and/or multiplexers (MUX) for driving devices that drive thin film transistors for display devices. have. Alternatively, it is preferable to apply it as an in-pixel driving thin film transistor in an organic light emitting diode display. Since the oxide semiconductor material has a low off-current, it is suitable for a switching thin film transistor that has a short On time and a long Off time. In addition, since the off current is small, the voltage sustaining period of the pixel is long, which is suitable for a display device requiring low speed driving and/or low power consumption. As described above, by simultaneously placing two different types of thin film transistors on the same substrate, it is possible to obtain a thin film transistor substrate exhibiting an optimum effect.

When forming a semiconductor layer from a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to first form a polycrystalline semiconductor layer that performs a process under severe conditions, and then to form an oxide semiconductor layer later. To this end, it is preferable that the first thin film transistor including the polycrystalline semiconductor material has a top-gate structure, and the second thin film transistor including the oxide semiconductor material has a bottom-gate structure.

In addition, in the manufacturing process, the polycrystalline semiconductor material deteriorates in properties when vacancy is present, so a process of filling the voids with hydrogen through a hydrogenation process is required. On the other hand, in the oxide semiconductor material, since voids that are not covalently bonded can serve as carriers, a process of stabilizing the voids to a certain extent is required. These two processes can be performed through a subsequent heat treatment process at 350°C to 380°C.

In order to perform the hydrogenation process, a nitride film containing a large amount of hydrogen particles is interposed on the polycrystalline semiconductor material. Since the nitride film contains a large amount of hydrogen in the material used in its manufacture, the laminated nitride film itself also contains a significant amount of hydrogen. In the heat treatment process, hydrogens are diffused into the polycrystalline semiconductor material. As a result, the polycrystalline semiconductor layer can achieve stabilization. During the heat treatment process, an excessive amount of hydrogens should not be diffused into the oxide semiconductor material. Therefore, it is preferable to interpose an oxide film between the nitride film and the oxide semiconductor material. After performing the heat treatment process, the oxide semiconductor material remains unaffected by hydrogen, so that device stabilization may be achieved.

In the following description, for convenience, the first thin film transistor is a thin film transistor for a driving element formed in a non-display area, and the second thin film transistor is a thin film transistor for a display element disposed in a pixel area of the display area. However, the present invention is not limited thereto, and in the case of an organic light emitting diode display, both the first thin film transistor and the second thin film transistor may be disposed in the pixel area of the display area. In particular, a first thin film transistor including a polycrystalline semiconductor material may be applied to a driving thin film transistor, and a second thin film transistor including an oxide semiconductor material may be applied to a switching thin film transistor.

<First embodiment>

A first embodiment of the present invention will be described with reference to FIGS. 1A and 1B. 1A is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention. 1B is a cross-sectional view illustrating a connection structure between a data line and a source electrode, and a gate line and a gate electrode in FIG. 1A. Here, a description will be given centering on a cross-sectional view capable of clearly showing the characteristics of the invention, and for convenience, a plan structure is not shown in the drawings.

Referring to FIG. 1A, a thin film transistor substrate for a flat panel display device according to a first embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on a substrate SUB. The first and second thin film transistors T1 and T2 may be disposed to be spaced apart or adjacent to each other. Alternatively, two thin film transistors may be overlapped and disposed.

A buffer layer BUF is stacked on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, it is described as a single layer for convenience. In addition, a light blocking layer may be further provided selectively only in a necessary portion between the buffer layer BUF and the substrate SUB. The light shielding layer may be formed for the purpose of preventing external light from flowing into the semiconductor layer of the thin film transistor disposed thereon.

A first semiconductor layer A1 is disposed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the first thin film transistor T1. The channel region is defined as a region where the first gate electrode G1 and the first semiconductor layer A1 overlap. Since the first gate electrode G1 overlaps the central portion of the first semiconductor layer A1, the central portion of the first semiconductor layer A1 becomes a channel region. Both sides of the channel region are regions doped with impurities and are defined as a source region SA and a drain region DA.

When the first thin film transistor T1 is a thin film transistor for a driving element, it is preferable to have characteristics suitable for performing high-speed driving processing. For example, a P-MOS or N-MOS type thin film transistor may be used, or a C-MOS type thin film transistor including both may be provided. It is preferable that the P-MOS, N-MOS and/or C-MOS type thin film transistors include a polycrystalline semiconductor material such as poly-silicon. In addition, in the case of the first thin film transistor T1, it is preferable to have a top-gate structure.

A gate insulating layer GI is stacked on the entire surface of the substrate SUB on which the first semiconductor layer A1 is disposed. The gate insulating layer GI may be formed of silicon nitride (SiNx) or silicon oxide (SiOx). In the case of the gate insulating layer GI, it is preferable to have a thickness of about 1,000 Å to 1,500 Å in consideration of stability and characteristics of the device. When the gate insulating layer GI is formed of silicon nitride (SiNx), a large amount of hydrogen may be included in the gate insulating layer GI in a manufacturing process. Since these hydrogens may diffuse out of the gate insulating layer GI in a subsequent process, it is preferable to form the gate insulating layer GI of a silicon oxide material.

In the first semiconductor layer A1 including a polycrystalline silicon material, hydrogen diffusion may exhibit a positive effect. However, a negative effect may be exerted on the second thin film transistor T2 having different properties from the first thin film transistor T1. Accordingly, when thin film transistors using different materials are formed on the same substrate as in the present invention, it is more preferable to use silicon oxide (SiOx) that does not have a special effect on the device. In some cases, unlike the case described in the first embodiment, the gate insulating layer GI may be formed to be about 2,000 Å to 4,000 Å thick. In this case, when the gate insulating layer GI is formed of silicon nitride (SiNx), the degree of diffusion of hydrogen may be severe. Accordingly, in consideration of various cases, it is preferable that the gate insulating film GI is formed of silicon oxide (SiOx).

A first gate electrode G1 is disposed on the gate insulating layer GI. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1. The central portion of the first semiconductor layer A1 overlapping the first gate electrode G1 is defined as a channel region.

An intermediate insulating layer ILD is stacked on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. The intermediate insulating layer ILD is preferably formed of a nitride layer SIN including an inorganic nitride material such as silicon nitride (SiNx). The nitride film SIN is deposited to perform a hydrogenation treatment on the first semiconductor layer A1 including polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process.

A first source electrode S1, a first drain electrode D1, and a second gate electrode G2 are disposed on the intermediate insulating film ILD. The first source electrode S1 contacts the source region SA, which is a side of the first semiconductor layer A1, through the source contact hole SH penetrating the intermediate insulating layer ILD and the gate insulating layer GI. The first drain electrode D1 contacts the drain region DA that is the other side of the first semiconductor layer A1 through the drain contact hole DH penetrating the intermediate insulating layer ILD and the gate insulating layer GI. Meanwhile, the second gate electrode G2 is disposed in the region of the second thin film transistor T2. The first source electrode S1, the first drain electrode D1, and the second gate electrode G2 are formed on the same layer with the same material and with the same mask, thereby simplifying the manufacturing process.

An oxide film SIO is stacked on the intermediate insulating film ILD on which the first source electrode S1, the first drain electrode D1, and the second gate electrode G2 are formed. It is preferable that the oxide film SIO includes an inorganic oxide material such as silicon oxide (SiOx). Since the oxide layer SIO has a structure stacked on the nitride layer SIN, hydrogen emitted from the nitride layer SIN is prevented from being excessively diffused into the semiconductor material of the second thin film transistor by a subsequent heat treatment process.

It is preferable that hydrogen emitted from the intermediate insulating layer ILD made of the nitride layer SIN diffuses into the first semiconductor layer A1 disposed thereunder with the gate insulating layer GI interposed therebetween. On the other hand, it is preferable to prevent the hydrogen emitted from the nitride film SIN from being diffused into the semiconductor material of the second thin film transistor T2 formed thereon. Therefore, it is preferable that the nitride film SIN is stacked on the gate insulating film GI close to the first semiconductor layer A1. In some cases, it is preferable that the nitride film SIN selectively covers the first thin film transistor T1 including the first semiconductor layer A1 and is not disposed in a region where the second thin film transistor T2 is disposed.

In addition, in consideration of the manufacturing process and hydrogen diffusion efficiency, the intermediate insulating film ILD made of the nitride film SIN is preferably laminated to a thickness of 1,000 Å to 3,000 Å. In addition, in order to have a large amount of hydrogen in the nitride film SIN diffuse into the first semiconductor layer A1, but to have as little influence as possible to the second semiconductor layer A2, the thickness of the oxide film SIO is the gate insulating film GI It is preferable that it is thicker than ). In particular, the oxide layer SIO is for controlling the degree of diffusion of hydrogen emitted from the nitride layer SIN, and the thickness of the oxide layer SIO is preferably thicker than that of the nitride layer SIN. In addition, the oxide layer SIO must function as a gate insulating layer in the second thin film transistor T2. In view of this situation, it is preferable that the oxide film SIO is stacked to a thickness of about 1,000 Å to 3,000 Å.

A second semiconductor layer A2 overlapping the second gate electrode G2 is disposed on the upper surface of the oxide film SIO. The second semiconductor layer A2 includes a channel region of the second thin film transistor T2. When the second thin film transistor T2 is a thin film transistor for a display element, it is preferable to have properties suitable for performing display function processing. For example, indium-gallium-zinc oxide (Indium Gallium Zinc Oxide: IGZO), indium-gallium oxide (Indium Gallium Oxide: IGO), and indium-zinc oxide (Indium Zinc Oxide: IZO), including oxide semiconductor materials such as It is desirable. Oxide semiconductor materials have low Off-Current characteristics and thus can be driven at a low frequency. Due to this characteristic, it is possible to sufficiently drive even with a size of a low auxiliary capacity, thereby reducing the area occupied by the auxiliary capacity. Therefore, it is advantageous to implement an ultra-high resolution display device having a small unit pixel area. When the oxide semiconductor material is included, it is preferable to have a bottom-gate structure that can more effectively secure the stability of the device.

The second source electrode S2 and the second drain electrode D2 are disposed on the second semiconductor layer A2 and the oxide layer SIO. The second source electrode S2 and the second drain electrode D2 contact upper surfaces of one side and the other side of the second semiconductor layer A2, respectively, and are disposed at a predetermined distance apart from each other. The second source electrode S2 is disposed to contact the upper surface of the oxide layer SIO and the upper surface of one side of the second semiconductor layer A2. The second drain electrode D2 is disposed to contact the upper surface of the oxide film SIO and the upper surface of the other side of the second semiconductor layer A2.

A passivation layer PAS is covering the first thin film transistor T1 and the second thin film transistor T2. Thereafter, a contact hole for exposing the first drain electrode D1 and/or the second drain electrode D2 by patterning the passivation layer PAS may be further formed. Further, a pixel electrode may be further included on the passivation layer PAS to contact the first drain electrode D1 and/or the second drain electrode D2 through a contact hole. Here, for convenience, only portions representing structures of thin film transistors representing the main features of the present invention have been illustrated and described.

As described above, in the thin film transistor substrate for a flat panel display according to the first embodiment of the present invention, the first thin film transistor T1 including the polycrystalline semiconductor material and the second thin film transistor T2 including the oxide semiconductor material are the same. It has a structure formed on the substrate SUB. In particular, the first semiconductor layer A1 including the polycrystalline semiconductor material of the first thin film transistor T1 is disposed under the first gate electrode G1, and includes the oxide semiconductor material of the second thin film transistor T2. The second semiconductor layer A2 is disposed on the second gate electrode G2. Further, the second gate electrode G2 is disposed on the intermediate insulating layer ILD covering the first gate electrode G1. Therefore, by first forming the first semiconductor layer A1 formed at a relatively high temperature, and then forming the second semiconductor layer A2 formed at a relatively low temperature, the oxide semiconductor material is exposed to a high temperature state during the manufacturing process. It has a structure that can avoid the situation that becomes. Accordingly, the first thin film transistor has a top-gate structure because the first semiconductor layer A1 must be formed before the first gate electrode G1. The second thin film transistor has a bottom-gate structure because the second semiconductor layer A2 must be formed later than the second gate electrode G2.

In addition, in the process of heat-treating the second semiconductor layer A2 including the oxide semiconductor material, a hydrogen treatment process may be simultaneously performed on the first semiconductor layer A1 including the polycrystalline semiconductor material. To this end, the intermediate insulating layer ILD is made of a nitride layer SIN, and an oxide layer SIO is stacked on the intermediate insulating layer ILD. As a characteristic of the manufacturing process, a hydrogenation process is required in which hydrogen contained in the nitride film SIN is diffused into the first semiconductor layer A1 by a heat treatment process. In addition, a heat treatment process for stabilizing the second semiconductor layer A2 containing an oxide semiconductor material is also required. The hydrogenation process may be performed after laminating the intermediate insulating film ILD on the first semiconductor layer A1, and the heat treatment process may be performed after the second semiconductor layer A2 is formed. According to the first embodiment of the present invention, hydrogen contained in the nitride film SIN by the oxide film SIO deposited on the nitride film SIN under the second semiconductor layer A2 includes an oxide semiconductor material. It has a structure capable of preventing excessive diffusion into the layer A2. Accordingly, in the structure according to the first embodiment of the present invention, the hydrogenation process may be simultaneously performed in the heat treatment process for stabilizing the oxide semiconductor material.

Meanwhile, the nitride film SIN is stacked on the first gate electrode G1 in order to be disposed close to the first semiconductor layer A1 requiring hydrogen treatment. In addition, the second thin film transistor T2 including the oxide semiconductor material is disposed to be disposed considerably farther away from the nitride film SIN, and the oxide film SIO covering the nitride film SIN and the second gate electrode G2 formed thereon. It is stacked on top of ). As a result, it is possible to prevent excessive diffusion of hydrogen contained in the nitride film SIN into the second semiconductor layer A2 in the subsequent heat treatment process.

The above description with reference to FIG. 1A has been described only for the basic structures of the first thin film transistor and the second thin film transistor. Actually, when the second thin film transistor is used as a display element disposed in the pixel region, gate wiring and data wiring are disposed around the pixel region. In addition, these gate wirings and data wirings are preferably formed on the same layer as the gate wirings and data wirings of the first thin film transistor. Hereinafter, with reference to FIG. 1B, how each of the gate electrode and the source electrode constituting the second thin film transistor can be connected to the gate wiring and the data wiring will be further described.

Referring to FIG. 1B, the basic structure of thin film transistors is the same as described above. Therefore, redundant descriptions are omitted. When forming the first gate electrode G1 constituting the first thin film transistor T1, the gate wiring GL is disposed on the same layer of the same material and around the second thin film transistor T2. That is, the gate wiring GL has a structure covered by the intermediate insulating film ILD like the first gate electrode G1.

A source contact hole SH for opening the source region SA of the first semiconductor layer A1 and a drain contact hole DH for exposing the drain region DA are formed in the intermediate insulating layer ILD. At the same time, a gate wiring contact hole GLH exposing a part of the gate wiring GL is further formed in the intermediate insulating layer ILD.

A first source electrode S1, a first drain electrode D1, a second gate electrode G2, and a data line DL are disposed on the intermediate insulating layer ILD. The first source electrode S1 contacts the source region SA through the source contact hole SH. The first drain electrode D1 contacts the drain region DA through the drain contact hole DH. Also, the second gate electrode G2 is connected to the gate line GL through the gate line contact hole GLH. The data line DL is disposed around the second thin film transistor T2 to cross the gate line GL with the intermediate insulating layer ILD interposed therebetween.

The first source electrode S1, the first drain electrode D1, and the second gate electrode G2 are covered by the oxide film SIO. A second semiconductor layer A2 overlapping the second gate electrode G2 is disposed on the oxide layer SIO. In addition, a data line contact hole DLH exposing a part of the data line DL is further formed in the oxide layer SIO.

A second source electrode S2 and a second drain electrode D2 are disposed on the second semiconductor layer A2 and the oxide layer SIO. The second source electrode S2 contacts the upper surface of one side of the second semiconductor layer A2 and is connected to the data line DL through the data line contact hole DLH. The second drain electrode D2 contacts the upper surface of the other side of the second semiconductor layer A2.

Hereinafter, a method of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention will be described with reference to FIG. 2 further. 2 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to the first embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. Although not described in the drawings, before depositing the buffer layer BUF, a light blocking layer may be formed in a necessary portion. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer A1 is formed by patterning a polycrystalline silicon material by a first mask process. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating layer GI. It is preferable that the gate insulating film GI is formed of silicon oxide. It is preferable that the thickness of the gate insulating layer GI is 1,000 Å to 1,500 Å. (S120)

A gate metal material is deposited on the gate insulating layer GI and patterned by a second mask process to form a first gate electrode G1. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1. (S200)

A doped region including the source region SA and the drain region DA is defined by implanting impurities into the lower first semiconductor layer A1 using the first gate electrode G1 as a mask. The process of defining the doped region may be slightly different depending on the P-MOS, N-MOS, or C-MOS. For example, in the case of an N-MOS type thin film transistor, a high concentration doped region may be formed first, and then a low concentration doped region may be formed later. A highly doped region may be defined by using a photoresist pattern of the first gate electrode G1 having a size larger than that of the first gate electrode G1. By removing the photoresist and using the first gate electrode G1 as a mask, a low density doping area (LDD) may be defined between the high concentration doped region and the first gate electrode G1. The impurity doped region is not shown in the drawing for convenience. (S210)

An intermediate insulating film ILD made of a nitride film SIN is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed using an inorganic nitride material such as silicon nitride (SiNx). The nitride film SIN may contain a large amount of hydrogen therein during a manufacturing process. Considering the manufacturing process and hydrogen diffusion, the intermediate insulating layer ILD is deposited to a thickness of 1,000 Å to 3,000 Å. (S220)

The intermediate insulating layer ILD is patterned in a third mask process to form a source contact hole SH exposing one side of the first semiconductor layer A1 and a drain contact hole DH exposing the other side. This is to connect the source-drain electrode to be formed later with the first semiconductor layer A1. (S300)

A metal material is deposited on the intermediate insulating layer ILD. A metal material is patterned by a fourth mask process to form a first source electrode S1, a first drain electrode D1, and a second gate electrode G2. The first source electrode S1 contacts one side of the first semiconductor layer A1 through the source contact hole SH. The first drain electrode D1 contacts the other side of the first semiconductor layer A1 through the drain contact hole DH. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

The oxide film SIO using an inorganic oxide material such as silicon oxide (SiOx) on the entire surface of the substrate SUB on which the first source electrode S1, the first drain electrode D1, and the second gate electrode G2 are formed. Evaporate. From a structural aspect of the second thin film transistor T2, the oxide film SIO functions as a gate insulating film covering the second gate electrode G2. In addition, the oxide layer SIO is preferably deposited to a thickness of 1,000 Å to 3,000 Å to prevent diffusion of hydrogen particles emitted from the nitride layer SIN into a semiconductor material to be disposed thereon. In consideration of the degree of hydrogen diffusion and device characteristics, the thickness of the oxide film SIO and the nitride film SIN, which is the intermediate insulating film ILD, can be appropriately selected. For example, in order to prevent excessive diffusion of hydrogen, the nitride film SIN is preferably thinner than the oxide film SIO. (S410)

An oxide semiconductor material is deposited on the oxide layer SIO. The oxide semiconductor material includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGZO), and Indium Zinc Oxide (IZO). A second semiconductor layer A2 is formed by patterning an oxide semiconductor material in a fifth mask process. The second semiconductor layer A2 is disposed to overlap the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to subsequent heat treatment to perform hydrogenation of the first semiconductor layer A1 containing polycrystalline silicon and the heat treatment of the second semiconductor layer A2 containing oxide semiconductor material. Perform at the same time. The subsequent heat treatment process is 350? It is carried out at a temperature of 380? In this case, while a large amount of hydrogen contained in the nitride layer SIN diffuses into the first semiconductor layer A1, the amount diffused into the second semiconductor layer A2 by the oxide layer SIO is limited. In some cases, the hydrogenation process of the first semiconductor layer A1 and the heat treatment process of the second semiconductor layer A2 may be separately performed. In this case, the hydrogenation process is performed first after the process S220 of depositing the intermediate insulating layer ILD, and heat treatment of the second semiconductor layer A2 is performed through this subsequent heat treatment process. (S510)

A source-drain metal material is deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A second source electrode S2 and a second drain electrode D2 are formed by patterning a source-drain metal material in a sixth mask process. The second source electrode S2 is disposed to be in contact with the upper surface of one side of the second semiconductor layer A2 and the upper surface of the second intermediate insulating layer ILD2. Likewise, the second drain electrode D2 is disposed to contact the upper surface of the other side of the second semiconductor layer A2 and the upper surface of the oxide film SIO. (S600)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. Although not shown in the drawing, a contact hole for exposing portions of the first and/or second drain electrodes D1 and D2 may be further formed by patterning the passivation layer PAS afterwards. (S700)

<Second embodiment>

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 3. 3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a second exemplary embodiment of the present invention.

The second embodiment of the present invention has the same basic configuration as the first embodiment. If there is a difference, the intermediate insulating film ILD is composed of a double layer. The lower oxide layer SIO2 and the nitride layer SIN may be stacked. For example, a nitride layer SIN may be stacked on the lower oxide layer SIO2. Alternatively, a lower oxide layer SIO2 may be stacked on the nitride layer SIN. Here, the lower oxide film SIO2 is a name because it is located below the oxide film SIO, and is not a term that limits what is disposed under the nitride film.

Through a subsequent heat treatment process, hydrogen must be diffused into the first semiconductor layer A1 from the nitride film SIN containing a large amount of hydrogen in the manufacturing process. In consideration of diffusion efficiency, the thickness of the nitride layer SIN of the intermediate insulating layer ILD is preferably 1,000 Å to 3,000 Å. The lower oxide film SIO2 compensates for the surface of the gate insulating film GI damaged in the process of forming the first gate electrode G1 (which is disposed under the nitride film SIN), or is disposed on the nitride film SIN. ) For stabilizing the nitride film (SIN), it is preferable to have a thickness of about 500Å to 1,000Å.

An oxide layer SIO is stacked on the intermediate insulating layer ILD in which the lower oxide layer SIO2 and the nitride layer SIN are stacked. The oxide layer SIO functions as a gate insulating layer in the second thin film transistor T2. Therefore, if the oxide layer SIO is too thick, the gate voltage may not be normally transmitted to the second semiconductor layer A2. Therefore, it is preferable that the oxide layer SIO has a thickness of 1,000 Å to 3,000 Å. In addition, it is preferable that the gate insulating layer GI has a thickness of about 1,000 Å to 1,500 Å.

In FIG. 3, the intermediate insulating layer ILD is illustrated as a structure in which a nitride layer SIN is stacked on a lower oxide layer SIO2, and this has been described mainly. However, if necessary, the intermediate insulating layer ILD may have a structure in which a nitride layer SIN is stacked on a lower side and a lower oxide layer SIO2 is stacked on the upper side. In this case, the nitride layer SIN may have a structure that is disposed closer to the lower first semiconductor layer A1, while further spaced apart from the upper second semiconductor layer A2 by the thickness of the lower oxide layer SIO2. . Therefore, diffusion of hydrogen into the first semiconductor layer A1 is better, and diffusion of hydrogen into the second semiconductor layer A2 can be better prevented.

Considering the manufacturing process, it is preferable that the thickness of the intermediate insulating layer (ILD) is 2,000 Å to 6,000 Å, so that the thickness of each of the nitride layer (SIN) and the lower oxide layer (SIO2) is formed to a thickness of 1,000 Å to 3,000 Å. It is desirable. In addition, the oxide layer SIO is preferably formed to a thickness of 1,000 Å to 3,000 Å, considering that it is a gate insulating layer in the second thin film transistor T2.

Since other components are the same as those of the first embodiment, detailed descriptions are omitted. Hereinafter, a process of manufacturing the thin film transistor substrate for a flat panel display according to the second embodiment will be described. Again, since it is almost the same as that of the first embodiment, the same description that has no important meaning will be omitted. 4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a second embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer A1 is formed by patterning a polycrystalline silicon material by a first mask process. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating layer GI. The gate insulating layer GI is preferably formed of silicon oxide having a thickness of about 1,000 Å to 1,500 Å. (S120)

A gate metal material is deposited on the gate insulating layer GI and patterned by a second mask process to form a first gate electrode G1. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1. (S200)

A doped region including the source region SA and the drain region DA is defined by implanting impurities into the lower first semiconductor layer A1 using the first gate electrode G1 as a mask. (S210)

An intermediate insulating layer ILD is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, it is deposited in a double layer structure in which the lower oxide layer SIO2 and the nitride layer SIN are stacked. In the intermediate insulating layer ILD, the lower oxide layer SIO2 may be stacked on the lower side, the nitride layer SIN may be stacked on the upper side, or vice versa. When the lower oxide layer SIO2 is stacked below, it is preferable to continuously stack the lower oxide layer SIO2 to have a thickness of 500 Å to 1,000 Å, and the nitride layer SIN to have a thickness of 1,000 Å to 3,000 Å. When the nitride layer SIN is stacked underneath, the lower oxide layer SIO2 is also stacked to about 1,000 Å to 3,000 Å, thereby preventing excessive diffusion of hydrogen into the second semiconductor layer A2. (S220)

The intermediate insulating layer ILD is patterned in a third mask process to form a source contact hole SH and a drain contact hole DH exposing one side and the other side of the first semiconductor layer A1, respectively. (S300)

A metal material is deposited on the intermediate insulating layer ILD. A metal material is patterned by a fourth mask process to form a first source electrode S1, a first drain electrode D1, and a second gate electrode G2. The first source electrode S1 contacts one side of the first semiconductor layer A1 through the source contact hole SH. The first drain electrode D1 contacts the other side of the first semiconductor layer A1 through the drain contact hole DH. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

The oxide film SIO using an inorganic oxide material such as silicon oxide (SiOx) on the entire surface of the substrate SUB on which the first source electrode S1, the first drain electrode D1, and the second gate electrode G2 are formed. Evaporate. The oxide film SIO functions as a gate insulating film in the second thin film transistor T2 and prevents hydrogen diffusion. Therefore, it is preferable to laminate to a thickness of 1,000 Å to 3,000 Å. (S410)

An oxide semiconductor material is deposited on the oxide layer SIO and patterned by a fifth mask process to form a second semiconductor layer A2. The second semiconductor layer A2 is disposed to overlap the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to subsequent heat treatment to perform hydrogenation of the first semiconductor layer A1 containing polycrystalline silicon and the heat treatment of the second semiconductor layer A2 containing oxide semiconductor material. Perform at the same time. The subsequent heat treatment process is performed at a temperature of 350°C to 380°C. In this case, while a large amount of hydrogen contained in the nitride layer SIN diffuses into the first semiconductor layer A1, the amount diffused into the second semiconductor layer A2 by the oxide layer SIO is limited. In some cases, the hydrogenation process of the first semiconductor layer A1 and the heat treatment process of the second semiconductor layer A2 may be separately performed. (S510)

A source-drain metal material is deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A second source electrode S2 and a second drain electrode D2 are formed by patterning a source-drain metal material in a sixth mask process. (S600)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. (S700)

<Third embodiment>

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 5. 5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a third embodiment of the present invention.

The third embodiment of the present invention has the same basic configuration as the first and second embodiments. If there is a difference, the oxide layer SIO functions as an intermediate insulating layer for the first thin film transistor T1 and a gate insulating layer for the second thin film transistor T2. Specifically, the intermediate insulating film ILD includes a first intermediate insulating film ILD1 and a second intermediate insulating film ILD2. The first intermediate insulating layer ILD1 has a structure in which a lower oxide layer SIO2 and a nitride layer SIN are stacked. In particular, the nitride layer SIN is not disposed in the second region where the second thin film transistor T2 is disposed, but has a structure that selectively covers the first region where the first thin film transistor T1 is disposed. The second intermediate insulating layer ILD2 is formed of an oxide layer SIO and functions as a gate insulating layer of the second thin film transistor T2.

By disposing the nitride layer SIN in the region where the first thin film transistor T1 is disposed, hydrogen contained in the nitride layer SIN may be diffused into the first semiconductor layer A1 through a subsequent heat treatment process. In consideration of hydrogen diffusion efficiency, it is preferable that the nitride film SIN has a thickness of 1,000 Å to 3,000 Å. Meanwhile, it is preferable that the lower oxide layer SIO2 has a thin thickness of about 500 Å to 1,000 Å.

Even if the nitride film SIN has a thickness of about 3,000 Å, since it is separated by a considerable distance from the second thin film transistor T2, the possibility that hydrogen in the nitride film SIN will diffuse to the second semiconductor layer A2 is significantly lower. . Further, since the oxide layer SIO, which is the second intermediate insulating layer ILD2, is further stacked on the nitride layer SIN, diffusion of hydrogen into the second semiconductor layer A2 can be reliably prevented.

Meanwhile, in the third embodiment, unlike the first and second embodiments, the first source-drain electrodes S1 and D1 and the second source-drain electrodes S2 and D2 are formed of the same material on the same layer. There is this.

Other components are the same as those of the first and/or second embodiments, and thus redundant descriptions will be omitted. Hereinafter, a process of manufacturing a thin film transistor substrate for a flat panel display according to the third embodiment will be described. Here, too, since it is almost the same as that of the first and/or second embodiments, redundant descriptions are omitted. 5 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a third embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer A1 is formed by patterning a polycrystalline silicon material by a first mask process. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating layer GI. The gate insulating layer GI is preferably formed of silicon oxide having a thickness of about 1,000 Å to 1,500 Å. (S120)

A gate metal material is deposited on the gate insulating layer GI and patterned by a second mask process to form a first gate electrode G1. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1. (S200)

A doped region including the source region SA and the drain region DA is defined by implanting impurities into the lower first semiconductor layer A1 using the first gate electrode G1 as a mask. (S210)

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, it is formed in a double layer structure in which the lower oxide layer SIO2 and the nitride layer SIN are stacked. The first intermediate insulating layer ILD1 may have a lower oxide layer SIO2 underneath it and a nitride layer SIN overlaid thereon, or vice versa. When the lower oxide layer SIO2 is stacked below, it is preferable to continuously stack the lower oxide layer SIO2 to have a thickness of 500 Å to 1,000 Å, and the nitride layer SIN to have a thickness of 1,000 Å to 3,000 Å. When the nitride layer SIN is stacked underneath, the lower oxide layer SIO2 is also stacked to about 1,000 Å to 3,000 Å, thereby preventing excessive diffusion of hydrogen into the second semiconductor layer A2. (S220)

As a third mask process, only the nitride layer SIN of the first intermediate insulating layer ILD1 is patterned to cover the first semiconductor layer A1. When the nitride layer SIN is disposed below, the nitride layer SIN is patterned after the nitride layer SIN is deposited, and the lower oxide layer SIO2 is stacked. When the nitride film SIN is disposed on the upper portion, the lower oxide film SIO2 and the nitride film SIN are continuously deposited, and then only the nitride film SIN is patterned. (S300)

A gate metal material is deposited on the first intermediate insulating layer ILD1 including the nitride layer SIN selectively formed only on the first semiconductor layer A1. A second gate electrode G2 is formed by patterning a gate metal material through a fourth mask process. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

A second intermediate insulating layer ILD2 made of an oxide layer SIO is deposited on the entire surface of the substrate SUB on which the second gate electrodes G2 are formed using an inorganic oxide material such as silicon oxide (SiOx). (S410)

An oxide semiconductor material is deposited on the second intermediate insulating layer ILD2 and patterned by a fifth mask process to form a second semiconductor layer A2. The second semiconductor layer A2 is disposed to overlap the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to subsequent heat treatment to perform hydrogenation of the first semiconductor layer A1 containing polycrystalline silicon and the heat treatment of the second semiconductor layer A2 containing oxide semiconductor material. Perform simultaneously. The subsequent heat treatment process is performed at a temperature of 350°C to 380°C. In some cases, the hydrogenation process of the first semiconductor layer A1 and the heat treatment process of the second semiconductor layer A2 may be separately performed. In this case, a large amount of hydrogen contained in the nitride layer SIN is diffused into the first semiconductor layer A1. On the other hand, since the nitride layer SIN covers only the first region in which the first channel layer A1 is located, the amount of diffusion to the second channel layer A2 is limited. (S510)

After performing a subsequent heat treatment on the semiconductor layer, in a sixth mask process, the second intermediate insulating layer ILD2 and the first intermediate insulating layer ILD1 are patterned to form a source contact hole SH and a drain contact hole DH. Form them. (S600)

A source-drain metal material is deposited on the entire surface of the substrate SUB on which the contact holes SH and DH and the second semiconductor layer A2 are formed. A first source electrode, a first drain electrode, a second source electrode, and a second drain electrode S1, D1, S2, and D2 are formed by patterning a source-drain metal material in a seventh mask process. (S700)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. (S800)

<1st application example>

The thin film transistor substrate including different thin film transistors described so far can be applied to various flat panel display devices. As suggested in the present invention, when thin film transistors having different characteristics are formed on one substrate, there are various advantages. Hereinafter, with reference to FIG. 7, it will be described in detail what features and advantages can be expected in a display device using a thin film transistor substrate according to a first application example of the present invention. 7 is a block diagram schematically showing a configuration of a display device according to a first application example of the present invention.

At least one of the first and second thin film transistors T1 and T2 may be a thin film transistor formed in each of the pixels of the display panel 100 to switch a data voltage written to the pixels or to drive the pixels. In the case of an organic light emitting diode display, the second thin film transistor T2 may be applied as a switch element of a pixel, and the first thin film transistor T1 may be applied as a driving element, but is not limited thereto. The first and second thin film transistors T1 and T2 may be combined and applied as a single switch device or a single driving device.

In order to reduce power consumption in a mobile device or a wearable device, a low-speed driving method for lowering a frame rate has been attempted. In this case, the frame frequency may be lowered in a still image or an image in which the update period of data is delayed. However, if the frame rate is lowered, a phenomenon in which the luminance flashes whenever the data voltage is changed or the voltage discharge time of the pixel is prolonged, so that the luminance flashes in a data update period may be observed. When the first and second thin film transistors T1 and T2 of the present invention are applied to a pixel, a flicker problem during low-speed driving can be solved.

When the data update period is prolonged during low speed driving, the amount of leakage current of the switch thin film transistor increases. The leakage current of the switch thin film transistor causes a decrease in the voltage of the storage capacitor STG and the gate-source voltage of the driving thin film transistor. In the present invention, the second thin film transistor, which is an oxide transistor, can be applied as a switch thin film transistor of a pixel. Since the oxide transistor has a low off-current, voltage drop across the storage capacitor and the gate electrode of the driving thin film transistor can be prevented. Accordingly, the present invention can prevent flicker during low speed driving.

When the first thin film transistor, which is a polysilicon transistor, is applied as a driving thin film transistor of a pixel, since the mobility of electrons is high, the amount of current supplied to the organic light emitting diode can be increased. Accordingly, according to the present invention, the second thin film transistor T2 is applied to the switch element of the pixel and the first thin film transistor T1 is applied to the driving element of the pixel, thereby significantly lowering power consumption and preventing deterioration of image quality.

The present invention is effective in applying to a mobile device or a wearable device because it is possible to prevent deterioration in image quality when a low-speed driving method is applied to reduce power consumption. For example, the portable electronic watch may update data on the display screen every second in order to reduce power consumption. The frame frequency at this time is 1 Hz. The present invention can implement excellent image quality without flicker even when using a driving frequency close to 1Hz or a still image. The present invention can significantly reduce the frame rate of a still image in the standby screen of a mobile device or a wearable device, thereby significantly reducing power consumption without deteriorating image quality. As a result, the present invention can improve the image quality of a mobile device or a wearable device and increase the battery life, thereby enhancing portability. According to the present invention, power consumption can be greatly reduced without deteriorating image quality even in an e-book (E-Book) having a very long data update period.

At least one of the first and second thin film transistors T1 and T2 is embedded in at least one of the driving circuit, for example, the data driver 200, the multiplexer 210, and the gate driver 300 in FIG. 7 A drive circuit can be configured. This driving circuit writes data to the pixels. In addition, one of the first and second thin film transistors T1 and T2 may be formed in the pixel and the other may be formed in the driving circuit. The data driver 200 converts the data of the input image into a data voltage and outputs it. The multiplexer 210 reduces the number of output channels of the data driver 200 by time-dividing the data voltage from the data driver 200 to a plurality of data lines DL. The gate driver 300 outputs a scan signal (or gate signal) synchronized with the data voltage to the gate line GL to sequentially select pixels to which data of an input image is written in line units. In order to reduce the number of output channels of the gate driver 300, a multiplexer (not shown) may be added between the gate driver 300 and the gate lines GL. The multiplexer 210 and the gate driver 300 may be directly formed on the thin film transistor substrate together with the pixel array as shown in FIG. 7. The multiplexer 210 and the gate driver 300 are disposed in the non-display area NA as shown in FIG. 7, and the pixel array is disposed in the display area AA.

The display device of the present invention can be applied to any display device requiring a thin film transistor, such as an active display device using a thin film transistor, for example, a liquid crystal display device, an organic light emitting diode display device, and an electrophoretic display device. Hereinafter, application examples of a display device to which a thin film transistor substrate according to the present invention is applied will be described with more reference to the drawings.

<2nd application example>

8 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device of a horizontal electric field type according to a second application example of the present invention. 9 is a cross-sectional view of the thin film transistor substrate shown in FIG. 8 taken along line I-I'.

The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 8 and 9 has a gate wiring GL and a data wiring DL intersecting on a lower substrate SUB with a gate insulating layer GI interposed therebetween, and the intersection thereof. A thin film transistor T is provided for each unit. In addition, the pixel region is defined by the cross structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode (G) branched from the gate line (GL), a source electrode (S) branched from the data line (DL), a drain electrode (D) facing the source electrode (S), and a gate. It includes a semiconductor layer (A) overlapping the gate electrode (G) on the insulating film (GI) and having a channel region between the source electrode (S) and the drain electrode (D).

A gate pad GP for receiving a gate signal from the outside is disposed at one end of the gate line GL. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 penetrating the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2. Meanwhile, a data pad DP for receiving pixel signals from the outside is disposed at one end of the data line DL. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2.

In the pixel area, a pixel electrode PXL and a common electrode COM are disposed with the second passivation layer PA2 therebetween to form a fringe field. The common electrode COM may be connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL. As another method, the common electrode COM may have a shape disposed on the entire surface of the substrate SUB except for a portion where the drain contact hole DH is disposed. That is, the common electrode COM may function to shield the data line DL by covering the upper layer of the data line DL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may have various shapes according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes at any time according to the video data to be implemented is applied to the pixel electrode PXL. Accordingly, parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such parasitic capacitance may cause a problem in image quality, it is preferable to first place the common electrode COM and then place the pixel electrode PXL on the uppermost layer.

That is, after forming the planarization layer PAC by thickly stacking an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. In addition, after forming the second passivation layer PA2 covering the common electrode COM, a pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2. In this structure, since the pixel electrode PXL is separated by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL are separated. In between, the parasitic capacity can be reduced. However, the present invention is not limited thereto, and in some cases, the pixel electrode PXL may be disposed first, and the common electrode COM may be disposed on the uppermost layer.

The common electrode COM has a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL has a plurality of line segment shapes. In particular, the pixel electrode PXL has a structure vertically overlapping the common electrode COM with the second passivation layer PA2 interposed therebetween. Accordingly, a fringe field is formed between the pixel electrode PXL and the common electrode COM. By the fringe field type electric field, liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

8 and 9 explaining the second application example of the present invention, for convenience, the structure of the thin film transistor T in the liquid crystal display device is only schematically illustrated. The structure of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, when low speed driving is required, the second thin film transistor T2 including an oxide semiconductor layer may be applied. When low power consumption is required, the first thin film transistor T1 including a polycrystalline semiconductor layer may be applied. Alternatively, the first and second thin film transistors T1 and T2 may be provided, and may be configured to connect to each other, thereby complementing each other.

<Third Application Example>

10 is a plan view showing a structure of one pixel in a matrix organic light emitting diode display according to a third application example of the active invention. FIG. 11 is a cross-sectional view illustrating the structure of an active matrix organic light emitting diode display taken along line II-II' in FIG. 10.

10 and 11, the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode OLE connected to the driving thin film transistor DT. Includes.

The switching thin film transistor ST is disposed on the substrate SUB at a portion where the gate line GL and the data line DL cross each other. The switching thin film transistor ST supplies a data voltage from the data line DL to the gate electrode DG and the auxiliary capacitor STG of the driving thin film transistor DT in response to a scan signal, thereby selecting a pixel. Do it. The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. Further, the driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by controlling the current flowing through the organic light emitting diode OLE of the pixel according to the gate voltage.

The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. The organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base wiring VSS.

Referring to FIG. 11 for a closer look, the switching thin film transistor ST and the gate electrodes SG and DG of the driving thin film transistor DT are disposed on a substrate SUB of an active matrix organic light emitting diode display. have. In addition, the gate insulating film GI is covering the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed on a part of the gate insulating film GI overlapping the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are disposed to face each other at a predetermined interval. The drain electrode SD of the switching thin film transistor ST makes contact with the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH penetrating the gate insulating layer GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure are stacked on the entire surface.

The color filter CF is disposed in a portion corresponding to the area of the anode electrode ANO. It is preferable that the color filter CF has as large an area as possible. For example, it is preferable to have a shape overlapping with many areas of the data line DL, the driving current line VDD, and the front gate line GL. As described above, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filter CF are disposed is not flat and has a large step difference. When the organic light-emitting layer OL is stacked on a flat surface, light emission can be uniformly and uniformly emitted. Accordingly, a planarization film (PAC) or an overcoat layer (OC) is deposited on the entire surface of the substrate for the purpose of flattening the surface of the substrate.

In addition, the anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

On the substrate on which the anode electrode ANO is disposed, the bank BA on the area where the switching thin film transistor ST, the driving thin film transistor DT, and various wirings DL, GL, and VDD are disposed to define a pixel area (Or, a bank pattern) is arranged. The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA. In addition, the cathode electrode CAT is sequentially stacked on the organic light-emitting layer OL. When the organic light-emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel is indicated by a color filter CF located below. The organic light emitting diode display having the structure as shown in FIG. 11 becomes a bottom emission display device that emits light in a downward direction.

An auxiliary capacitor (or'Storage Capacitance') STG is disposed between the gate electrode DG and the anode ANO electrode of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT to stably maintain a voltage applied to the gate electrode DG of the driving thin film transistor DT by the switching thin film transistor ST.

By applying the thin film transistor substrate as described above, it is possible to implement a high-quality active display device. In particular, in order to have more excellent driving characteristics, it is preferable to form the semiconductor layer of the thin film transistor with a metal oxide semiconductor material.

The metal oxide semiconductor material has a characteristic of rapidly deteriorating when voltage is driven while being exposed to light. Therefore, it is desirable to have a structure capable of blocking light from outside in the upper and lower portions of the semiconductor layer. In the case of the thin film transistor substrate described above, it is preferable that the thin film transistor has a bottom gate structure. That is, light flowing from the bottom may be partially blocked by the gate electrode G, which is a metal material.

In this way, a plurality of pixel regions arranged in a matrix manner are disposed on a thin film transistor substrate for a flat panel display until now. In addition, at least one thin film transistor is disposed in each of the unit pixel regions. That is, a plurality of thin film transistors are distributed over the entire substrate. Since the structures of each of the plurality of pixels should all be used for the same purpose and have the same quality and properties, they are formed in the same structure.

However, in some cases, it may be necessary to have different characteristics of the thin film transistors. For example, in the case of an organic light emitting diode display, the switching thin film transistor ST and the driving thin film transistor DT are included in one pixel area. Since the switching thin film transistor ST and the driving thin film transistor DT have different purposes, their required characteristics are also different. To this end, it has the same structure and the same semiconductor channel layer, but can be designed to fit each function by different sizes. Alternatively, if necessary, a compensation thin film transistor may be further provided to supplement functions or performance.

10 and 11 explaining a third application example of the present invention, for convenience, the structures of the thin film transistors ST and DT of the organic light emitting diode display are only schematically illustrated. The structure of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, a second thin film transistor T2 including an oxide semiconductor layer may be applied to the switching thin film transistor ST. A first thin film transistor T1 provided with a polycrystalline semiconductor layer can be applied to the driving thin film transistor DT. In this way, while both the first and second thin film transistors T1 and T2 are provided, the disadvantages of the counterpart thin film transistors can be mutually compensated by mutual advantages.

<4th application example>

In another case, a thin film transistor substrate in which a driving element is incorporated in a non-display area of a display device is also used. Hereinafter, a case in which the driving element is directly formed on the display panel will be described in detail with reference to FIGS. 12 and 13.

12 is an enlarged plan view showing a schematic structure of an organic light emitting diode display according to a fourth application example of the present invention. 13 is a cross-sectional view illustrating a structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along line III-III' in FIG. 12. Here, as a description of a thin film transistor substrate for a flat panel display including a driving element, a detailed description of the thin film transistor and the organic light emitting diode disposed in the display area will be omitted.

First, with reference to FIG. 12, the structure on a plane is demonstrated. According to the fourth application example of the present invention, the organic light emitting diode display with a built-in gate driver (GIP) includes a display area AA for displaying image information and a number of elements for driving the display area AA. It includes a substrate SUB divided by the display area NA. In the display area AA, a plurality of pixel areas PA arranged in a matrix manner are defined. In FIG. 5, pixel areas PA are indicated by dotted lines.

For example, the pixel areas PA may be defined in an NxM type rectangle. However, it is not necessarily limited to this method, and may be arranged in various ways. Each of the pixel regions may have the same size or different sizes. In addition, three sub-pixels representing RGB (red, green, blue) colors may be used as one unit and may be regularly arranged. In terms of the simplest structure, the pixel regions PA have a cross structure of a plurality of gate lines GL running in the horizontal direction and a plurality of data lines DL and driving current lines VDD running in the vertical direction. Can be defined as

A data driving unit (or Data Driving Integrated Circuit) (DIC) for supplying a signal corresponding to image information to the data lines DL to the non-display area NA defined on the outer periphery of the pixel area PA, A gate driver (or Gate Driving Integrated Circuit) (GIP) for supplying scan signals to the gate wirings GL may be disposed. In the case of higher resolution than the VGA class, in which the number of data lines DL and driving current lines VDD increases, the data driver DIC is mounted outside the substrate SUB, and the data driver DIC ), data connection pads may be disposed instead.

In order to simplify the structure of the display device, the gate driver GIP is preferably formed directly on one side of the substrate SUB. In addition, a base wiring Vss for supplying a base voltage is disposed at the outermost part of the substrate SUB. The base wiring Vss is preferably arranged to receive a ground voltage supplied from the outside of the substrate SUB and supply the ground voltage to both the data driver DIC and the gate driver GIP. For example, the electrical wiring Vss is connected to the data driver DIC to be separately mounted on the upper side of the substrate SUB, and the gate driver GIP disposed on the left and/or right side of the substrate SUB. It can be arranged as if surrounding the substrate from the outside of.

In each pixel area PA, an organic light emitting diode, which is a core component of an organic light emitting diode display, and thin film transistors for driving the organic light emitting diode are disposed. The thin film transistors may be disposed in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The area that actually emits light is determined by the area of the organic light emitting layer overlapping the anode electrode ANO.

The anode electrode ANO has a shape that occupies a portion of the pixel area PA, and is connected to the thin film transistor disposed in the thin film transistor area TA. An organic light emitting layer OL is stacked on the anode electrode ANO, and an area where the anode electrode ANO and the organic light emitting layer OL overlap is determined as an actual light emitting area. The cathode electrode CAT is formed as one body so as to cover at least an area of the display area AA in which the pixel areas PA are disposed on the organic emission layer OL.

The cathode electrode CAT crosses the gate driver GIP and contacts the base wiring Vss disposed outside the substrate SUB. That is, a base voltage is applied to the cathode electrode CAT through the base wiring Vss. The cathode electrode CAT receives a base voltage, and the anode ANO receives an image voltage, and the organic light-emitting layer OL emits light due to a voltage difference therebetween to display image information.

With further reference to FIG. 13, a cross-sectional structure of an organic light emitting diode display according to a fourth application example of the present invention will be described in more detail. The non-display area NA in which the gate driver GIP and the base wiring Vss are disposed on the substrate SUB, and the switching thin film transistor ST, the driving thin film transistor DT, and the organic light emitting diode OLE are disposed. The display area AA is defined.

The gate driver GIP may include a thin film transistor formed together in a process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST disposed in the pixel area PA includes a gate electrode SG, a gate insulating layer GI, a channel layer SA, a source electrode SS, and a drain electrode SD. Further, the driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating film GI, a channel layer DA, a source electrode DS, and a drain electrode ( DD).

A protective layer PAS and a planarization layer PL are successively stacked on the thin film transistors ST and DT. An isolated rectangular anode electrode ANO occupying only a certain portion of the pixel area PA is disposed on the planarization layer PL. The anode electrode ANO contacts the drain electrode DD of the driving thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer PL.

A bank BA defining a light-emitting area is disposed on the substrate on which the anode electrode ANO is formed. The bank BA has a shape exposing most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA pattern. A cathode electrode CAT made of a transparent conductive material is stacked on the bank BA and the organic light emitting layer OL. Accordingly, the organic light emitting diode OLE including the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT is disposed.

The organic light-emitting layer OL may express white light, and a color may be expressed with a separately formed color filter CF. In this case, it is preferable that the organic light emitting layer OL is stacked to cover at least all of the display area AA.

The cathode electrode CAT is preferably covered over the display area AA and the non-display area NA so as to contact the base wiring Vss disposed on the outer side of the substrate SUB beyond the gate driver GIP. Accordingly, a base voltage may be applied to the cathode electrode CAT through the base wiring Vss.

Meanwhile, the base wiring Vss may be formed on the same layer of the same material as the gate electrode G. In this case, the cathode electrode CAT may be contacted through the protective layer PAS covering the base wiring Vss and the contact hole penetrating the gate insulating layer GI. Alternatively, the base wiring Vss may be formed on the same layer of the same material as the source-drain (SS-SD, DS-DD) electrodes. In this case, the base wiring Vss may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS.

12 and 13 explaining the fourth application example of the present invention, for convenience, the thin film transistors ST and DT of the organic light emitting diode display and the thin film transistor structures of the gate driving element GIP are only schematically illustrated. The structure of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, a second thin film transistor T2 including an oxide semiconductor layer may be applied to the switching thin film transistor ST. A first thin film transistor T1 provided with a polycrystalline semiconductor layer can be applied to the driving thin film transistor DT. In addition, a first thin film transistor T1 including a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may be provided with a C-MOS type thin film transistor including both a P-MOS type and an N-MOS type.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

GL: Gate wiring PAS: Protective film
DL: Data wiring VDD: Driving current wiring
PA: pixel region T: thin film transistor
AA: display area NA: non-display area
G: gate electrode A: semiconductor layer
S: source electrode D: drain electrode
GI: gate insulating film ILD: intermediate insulating film
SIN: nitride film SIO: oxide film
SIO1: upper oxide film SIO2: lower oxide film

Claims (22)

delete delete delete delete delete delete delete delete delete delete delete Board;
A first semiconductor layer disposed on the substrate and including a polycrystalline semiconductor material;
A gate insulating layer covering the first semiconductor layer;
A first gate electrode overlapping the first semiconductor layer on the gate insulating layer;
An intermediate insulating layer covering the first gate electrode and including a nitride layer;
A second gate electrode, a first source electrode, and a first drain electrode disposed on the intermediate insulating layer;
An oxide layer covering the second gate electrode, the first source electrode, and the first drain electrode;
A second semiconductor layer disposed on the oxide layer to overlap the second gate electrode and including an oxide semiconductor material; And
A second source electrode and a second drain electrode disposed on the second semiconductor layer,
The first source electrode is connected to one side of the first semiconductor layer through a source contact hole penetrating the intermediate insulating layer and the gate insulating layer,
The first drain electrode is connected to the other side of the first semiconductor layer through a drain contact hole penetrating the intermediate insulating layer and the gate insulating layer,
The second source electrode is in contact with one side of the second semiconductor layer,
The second drain electrode is in contact with the other side of the second semiconductor layer,
The first source electrode, the first drain electrode, and the second gate electrode disposed under the oxide layer are formed of the same material on the same layer,
The second gate electrode is thermally connected to a gate wiring including the same material as the first gate electrode through a gate contact hole penetrating the intermediate insulating layer,
The gate wiring is disposed on the same layer as the first gate electrode,
The second source electrode is connected to a data line including the same material as the second gate electrode through a data contact hole penetrating the oxide layer,
The data line is disposed on the same layer as the second gate electrode,
Display device.
The method of claim 12,
The first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in a first thin film transistor,
The second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in a second thin film transistor.
delete The method of claim 13,
The second thin film transistor is a switch element for selecting a pixel,
The first thin film transistor is a driving element that drives the organic light emitting diode of the pixel selected by the second thin film transistor.
delete delete delete delete delete The method of claim 12,
The intermediate insulating layer further includes a lower oxide layer.
The method of claim 21,
The nitride layer is disposed on the lower oxide layer.

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