TW583571B - Noise protection method and system of serial peripheral interface - Google Patents

Abstract

The invention relates to a noise protection method and system of serial peripheral interface (SPI). The method of the invention comprises the following procedures: repeatedly sample and proceed error correction, in which the repeated sampling employs a sampling clock with m folds of serial clock (SCK) signal frequency to proceed sampling and acquire a new SCK, where m is an integer greater than 3; proceed error correction procedure that encodes new SCK again based on an output code mapping table to issue a corrected SCK. The encoding of the output code mapping table uses an odd number that is greater than or equal to 3 as the encoding basis, and takes the one with more comparison bit number of data as the corrected SCK output. Based on the method of the invention, the invention further provides an SPI noise protection system by employing a sampling unit and a signal correction unit, so as to output an SCK signal capable of generating only an edge trigger SCK signal during one SCK cycle in accordance with the output code mapping table.

Description

583571 _ Case No. 91113552 / month (Japanese chromium, the next ____ V. Description of the invention (1) [Application field of the invention] The present invention relates to an anti-noise method, especially an anti-noise method for a serial peripheral interface Method and its system. [Background of the Invention] Serial Peripheral Interface (hereinafter referred to as SP I) uses three kinds of connection synchronization protocols: Serial Clock (Serial Clock, referred to as SCK), serial data output ( Se ° r 丄 a 丄 Data Out (hereinafter referred to as SD0), and serial data input (Serial Data I η, referred to as SDI hereinafter). The operation of SPI uses the edge trigger of CK to read data on SDI and For the transmission of data on SD0, please refer to "" Figure 1. "> Because SPI transmits and reads data through the edge trigger of each SCK ', therefore, when noise enters through SC KK or s C KK Unknown signal will cause errors in reading or sending data. In other words, because of the edge trigger of "SCK", SPI reads and sends SDI and SD0 data _ times. Due to the serial nature of SPI, SCK's Noise will cause Reading a single piece of material multiple times results in a data insertion error, which results in a serious problem of the entire series! Material errors. In practice, this kind of data error caused by SCK is not easy to correct. Refer to "Annex 1" for a clear understanding of the possible occurrence of such errors, which are the ^ 1 卞 diagrams of the signal edges on sc κ in the rising or falling stages. From the figure, it can be found that many of the maximum values of the signal (1) ^ = After there are several surges (noise), these surges may be edge-triggered by the system being signal 1, and then cause data, shape. Therefore, the data access of SDI and SD0 may be because of SCK = Miscellaneous ^

Page 5 583571 _Case No. 91113552 | \ January I ’S Amendment_ V. Description of the invention (2) The situation where the data is read incorrectly and sent incorrectly. Such errors need to be improved. [Objective and Summary of the Invention] In view of the above problems, the present invention provides an anti-noise method and a system for serial peripheral interfaces, which can eliminate the noise generated by SCK when SP I reads and transmits data. In order to achieve the above object, the anti-noise method of SP provided by the present invention includes the following steps: first, resampling; second, error correction. Among them, the resampling is to sample the SCK with a sampling clock signal of a frequency which is m times the frequency of S C K to obtain a new SCK. The error correction step is to re-encode the new SCK according to an output code comparison table to send a correction SCK. Among them, within one SCK cycle, this correction SCK has only one edge trigger signal. Here, m is a number of 3 or more. The output code comparison table is based on a comparison bit number, that is, an odd number η greater than or equal to 3. The output of the corrected SC κ is compared with the new SC κ and output code comparison table, and according to the data The larger the number of bits in the middle ratio is used as the output of the correction SCK. In addition, the present invention further provides an anti-noise system of SPI, including: a sampling unit and a signal error correction unit. Among them, the sampling unit is used to receive S C K and sample the SCK with a sampling clock signal (c 10 c k) that is a frequency that is m times the frequency of S C K to obtain a new SCK. The signal correction unit is connected to the sampling unit to correct the new SCK according to an output code comparison table to send a corrected SCK. The signal correction unit includes: an error correction register for storing serial data of the new serial clock signal; and a memory for storing the serial data of the new serial clock signal.

583571 Corrected the difference 1 ^ 1113552 M fJ: V. Description of the invention (3) " I --- output code comparison table · β μ & mouth output code comparison table 2 S y is more than the error correction register With this value, the correction serial clock signal is output. Obviously easy; Dong ,; ": G: 5 he ::, characteristics, and advantages can be changed, detailed description 2: the embodiment of the father, with the accompanying drawings [detailed description of the invention] i ^, refer to" "Figure 2", which is a flowchart of the s PI anti-noise H method of the present invention, to correct the noise and correct errors (step 2 2 0). New sampling (step 21 〇), in the 2 HG when shooting, "the invention first samples the SCK with a sampling date m times the sck frequency ^ pulse sfl # u (ClOck)" so that you can get SCK. Among them, the oblique joint and the edge joint τ team rain joint to the SCK sampling method can be edge upsampling or edge downsampling. Because the data of sp 丨 is read and sent, it is performed in the manner of SCK edge trigger during a SCK clock. Therefore, during the S C K clock period that is broken, only the original g c γ edge trigger 'can be performed to read and send the SP I data of the positive disc. Even if the s c κ edge trigger is delayed or advanced, it will not affect the SDI or 讣 〇 data take-out disk delivery. Λ The sampling clock signal (Clock) for SCK sampling requires that it is not practical to synchronize with SCK. Therefore, when sampling, the edge trigger time of sampling clock (Clock) is bound to be different from the edge trigger time of SCK. Therefore, m can theoretically be any number greater than or equal to 3, instead of 2. Therefore, 'as long as m is equal to or greater than 3', the S C K noise canceling work of the present invention can be performed. Next, in step 220, the present invention is based on an output comparison table.

Page 7 583571 _ plug ^ 91113552 car f month day Article ___ V. Description of the invention (4) '^ (Error Code Correction Table) Re-encode the new SCK to send the corrected S C K. This output code comparison table can be written based on simple error correction rules. For example, the output code comparison table can be every 3 or 5 bits ... the odd number is the coding unit '. In other words, the odd number (n) greater than or equal to 3 will be the sampled new SCK for the comparison of the corrected SCK. Benchmark. That is, the output code comparison table is based on a comparison of the number of bits. The output of the corrected SCK is compared with the new SCK and the output code comparison table, and the correction is based on the larger number of bits in the data. The output of sc K. If there is an error signal caused by noise, the output of s c K will still only occur once during the S C K clock. The corrected SCK is a continuous output, and there will be no separate “surge”, that is, noise that may have caused errors has been eliminated. Therefore, the reading and sending of SPI data will not cause errors due to noise parasitic on SCK. Therefore, the above-mentioned output code comparison table mainly records possible error codes and the correction codes to be sent, that is, the corrected s k K output. There are many possible noise generation situations as shown in “Annex 1” for signal edges. However, after sampling, the possible noise will disappear. For the specific method of the above method, please refer to the following. Please refer to "Figure 4", which is a block diagram of the SPI anti-noise system of the present invention, which contains two main parts: the sampling unit (Sampling

Unit) l0 and Signal Correction Unit (Error Correction Unit) 20. The sampling unit ίο is connected to the output terminal of sck, and is used to receive SCk and pair the sampling clock signal (clOck) with the above ra times SCK-IN frequency.

Page 8 583571 Correction __91 η 3552 t month (fa V. Description of the invention (5) SCK_ IN signal is sampled to obtain a sampling serial clock signal SCK s. The signal correction unit 20 and the sampling unit Connected at 10, which contains at least an error correction register, a memory, and a comparator. The error correction register is used to store the serial data of SCK-S. The memory is used to store an output code Comparison table (Output code Comparison Table), input

The number of comparison bits in the code comparison table is 3, 5, 7, etc. Its I: the number of bits of Ϊ 2 ί 3 according to the comparison bit of the output code comparison table = to correct the new serial clock signal SCK-S, and to output from w 仏 shanli-correct the serial clock Signal SCK. The comparison is based on the comparison of the output code comparison table, Golden Slaves, and the L% is based on the image. Please refer to "The data in the first error correction register to output the SCK. SCK for sampling-SXun Rui: ' 'f is the clock of the SCK-1N signal of the present invention. When sampling, the clock signal with an eight-times sampling rate eight times that of SCK-IN is often associated with the clock and clock of SCK-IN. For the triggering edge, the wave opening / edge of the SCK-S through sampling has a time interval of Δτ. Therefore, there is a time interval. ^ As shown in "Figure 4", it will be delayed by Δτ and then the invention is rotated out. Actual operation: The comparison table is a 3-bit error correction register to explain. Then, please refer to "The actual table of the flute code comparison table, save brother A, 5B", which also refers to the SCK input of the present invention. Figure 3 $ Example of operation, which takes the sampling result of m = 6 as an example. When the number is changed to unit 20, "★ \ when 8 (: 1 (-8, the serial data sent into the signal table is used to correct the signal. , Also = No. error correction unit 2 0 is based on this output code comparison value, such as "the 5A, 5b is' output SCK shape according to the value of the error correction register, and" Figure 5B X. "first map" situation normal sampling "There was the noise of sampling situations. In accordance with this input

583571

The principle of changing and modifying germanium according to the table is as follows. For those who have more bits, the information is provided. For example, when "101" in 2 2 is used, the output of SCK is i; if the error is corrected in the register of error σ, the output data SCK is 0, and so on =. The poor material of the sub-element is "the operation of the entire signal correction unit 2 0 is shown in the above picture", and the default error correction register value is "I bit string is" 1 0 0 0 1 1 1 ". When the timing unit is ^ q and the input Λ output code occupies the data as "010 J in the" 5A data, the input data is, the output SCK will be triggered behind. Enter a bit data as "1" ' Therefore, "1 1 1" on the error correction temporary cry ", and the signal correction unit 20 outputs SCK" i "and accesses another bit as" 0 ". At this time, the signal is corrected ^ yuan 2 〇 auxiliary "1". By analogy, 'the SCK input of the entire numbered error correction unit 2 〇 is "1100011"' and the output of sck-s is "100Q111" clocks of sampling frequency. It is important that there is only one SCK ^ In the case of the green "Figure 5A", the effect of the present invention cannot be seen. Please refer to "Figure 5B". The input data bit string is also "1 0 0 0 1 1 1". When the timing unit is 1, input a bit data as 1, change the data on the error register to "1 1 1", and the signal correction unit 2 outputs SCK "1". Then, input another bit as "0". At this time, the signal correction unit 20 outputs SCK "1". Next, a noisy read signal occurs so that the input is "〇". At this time, the data in the error register is changed to "101". At this time, the SCK output of the signal error correction unit 20 is "1". Although the following input is correct "0", the data of the error correction register will be "010". At this time, the SCK output will be "0". Finally, the SCK output of the entire signal correction unit 20 will become "1110011", and

Page 10 583571 _Case No. 91113552_year / month / 'Revision_ V. Description of the invention (7) 8 (: 1 (_8's output is "1000111". Although the phenomenon of edge trigger delay may occur (it may also be early) However, it is important that only one SCK edge trigger is generated during the correct SCK clock cycle. Therefore, no matter what kind of noise is generated, the output of SCK will eventually be in one SCK cycle, and only one edge is triggered. The situation occurs without the insertion of the data of the conventional technology. In addition, all other situations can be analyzed in the way of "Figure 5B", including changing the error register to 5, 7 ... The situation is the same, so I wo n’t go into details here. Please refer to "Figure 6", which is the SCK_IN signal of the present invention, which is resampled and corrected to correct the SCK. It can be found that under normal circumstances, the corrected SCK , Will delay T time, where T is the sum of ΔΤ and a sampling frequency time. If there is an error due to noise, the waveform will be different, but it will only be in one SCK clock period. One [Edge effect] [Effect of the invention] Using the anti-noise method and system of the SPI of the present invention, the anti-noise capability is significantly increased, and the influence of the impedance matching of the external circuit is reduced. Although the preferred embodiment of the present invention is disclosed as described above However, it is not intended to limit the present invention. Any person skilled in the relevant arts can make some changes and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by The ones defined in the scope of patent application shall prevail.

583571 '_Case No. 91113552, Month, Correction Day_ Brief description of the diagram The first diagram is a schematic diagram of reading and transmitting SPI data; the second diagram is a flowchart of the SPI anti-noise method of the present invention; the third diagram is Block diagram of the SPI anti-noise system of the present invention; Figure 4 is the SCK_S signal of the SCK_IN signal of the present invention after resampling; Figure 5 A is an actual operation example of the SCK output code comparison table of the present invention; Figure 5 B is An actual operation example of the SCK output code comparison table of the present invention; FIG. 6 is a corrected SCK of the SCK_IN signal of the present invention after resampling and correction; and Annex 1 is a signal diagram of SCK. [Symbol description] 10 Sampling unit 20 Signal correction unit B7 ~ B0 Bit 7 ~ 0 SCK serial clock signal (Seria 1 Clock) SCK _IN serial clock signal input SCK _S Pulse signal SDI serial data wm In (S eria 1 Data In) SDO serial data Ψ μ Out (S eria 1 Data Out) △ T Clock difference T m Clock difference

Page 12 583571 Λ_Case No. 91113552 _ ^^ year (month < day amends VI. Designated representative map Page 3

Claims (1)

583571 '_ Case No. 91113552 pf (X-day amendments_ VI) Patent application scope 1. An anti-noise method of serial peripheral interface is based on the serial clock signal (SCK) of the serial peripheral interface The action of correcting mistakes includes the following steps: Resampling ... Sampling the serial clock signal with a sampling clock signal (c 1 ck) that is m times the frequency of the serial clock signal to obtain a The new serial clock signal; and make corrections; compare an output code comparison table with the new serial clock signal to output a corrected serial clock signal; of which, in one of the serial clock signals, During the period, the correction serial clock signal has only one edge-triggered signal. 2 · The anti-noise method of the serial peripheral interface as described in item 1 of the patent application scope, where m is a number of 3 or more. 3. The anti-noise method of the serial peripheral interface as described in the first item of the scope of patent application, wherein the output code comparison table is based on a comparison bit number, and the output of the corrected serial clock signal is compared. A comparison table between the new serial clock signal and the output code. And based on the data of the new serial clock signal that occupies a larger number of the comparison bits, it is used as the output of the corrected serial clock signal, wherein the number of comparison bits is an odd number greater than or equal to 3. An anti-noise system for a serial peripheral interface is applied to an output terminal of a serial clock signal (SCK) of the serial peripheral interface for correcting errors, and includes: a sampling unit and the serial clock The output ends of the signals are connected to receive the serial clock signal and sample the clock signal (c 1 oc k) of the serial clock signal at a frequency that is m times the frequency of the serial clock signal. Page 13 583571 _Case No. 91135552 amended on F / F_ 6. Sample the patent application scope to obtain a new serial clock signal; and a signal correction unit connected to the sampling unit for output based on an output The code comparison table corrects the new serial clock signal to re-encode and send a corrected serial clock signal. 5. The anti-noise system of the serial peripheral interface as described in item 4 of the scope of patent application, wherein the signal correction unit includes: an error correction register for storing the serial of the new serial clock signal Data; a memory for storing the output code comparison table; and a comparator for comparing the value of the error correction register with the output code comparison table to output the correction serial clock signal. 6. The anti-noise system of serial peripheral interface as described in item 4 of the scope of patent application, where m is a number of 3 or more. 7. The anti-noise system of the serial peripheral interface according to item 4 of the scope of the patent application, wherein the output code comparison table is based on a comparison bit number, and the output system of the corrected serial clock signal is The comparison table between the new serial clock signal and the output code is compared, and according to the serial data of the new serial clock signal input in the error correction register, the comparison bit number that accounts for a larger number of bits is regarded as The output of the correction serial clock signal. 8. The anti-noise system with a serial peripheral interface as described in item 4 or 5 of the scope of patent application, wherein the number of comparison bits between the output code comparison table and the error correction register is greater than or equal to 3. odd number. Page 14