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WO2000055742A3 - System for interconnecting circuit boards housed within a chassis - Google Patents

System for interconnecting circuit boards housed within a chassis Download PDF

Info

Publication number
WO2000055742A3
WO2000055742A3 PCT/US2000/006586 US0006586W WO0055742A3 WO 2000055742 A3 WO2000055742 A3 WO 2000055742A3 US 0006586 W US0006586 W US 0006586W WO 0055742 A3 WO0055742 A3 WO 0055742A3
Authority
WO
WIPO (PCT)
Prior art keywords
chassis
circuit board
point
backplane
housed
Prior art date
Application number
PCT/US2000/006586
Other languages
French (fr)
Other versions
WO2000055742A2 (en
Inventor
Martin J Horne
Alexander M Kleyman
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Priority to AU40098/00A priority Critical patent/AU4009800A/en
Publication of WO2000055742A2 publication Critical patent/WO2000055742A2/en
Publication of WO2000055742A3 publication Critical patent/WO2000055742A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

A computer system includes a chassis, a backplane housed within the chassis, a first board housed within the chassis and connected to the backplane, and a second circuit board housed within the chassis and connected to the backplane. The backplane includes a plurality of point-to-point data buses. The first circuit board includes a switching fabric having a plurality of data ports where one of the plurality of data ports is connected to one of the plurality of point-to-point data buses. The second circuit board includes a segmentation and reassembly (SAR) controller having a physical layer interface. The physical layer interface is connected to the point-to-point data bus that is connected to the switching fabric. In this manner, the second circuit board is interconnected to the first circuit board.
PCT/US2000/006586 1999-03-15 2000-03-15 System for interconnecting circuit boards housed within a chassis WO2000055742A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU40098/00A AU4009800A (en) 1999-03-15 2000-03-15 System for interconnecting circuit boards housed within a chassis

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26812899A 1999-03-15 1999-03-15
US09/268,128 1999-03-15

Publications (2)

Publication Number Publication Date
WO2000055742A2 WO2000055742A2 (en) 2000-09-21
WO2000055742A3 true WO2000055742A3 (en) 2001-01-04

Family

ID=23021592

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/006586 WO2000055742A2 (en) 1999-03-15 2000-03-15 System for interconnecting circuit boards housed within a chassis

Country Status (2)

Country Link
AU (1) AU4009800A (en)
WO (1) WO2000055742A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7082100B2 (en) 2001-02-28 2006-07-25 Emc Corporation Storage system adapter and method of using same
GB2391745B (en) * 2001-02-28 2004-12-08 Emc Corp Network adapter and method of using same
US7107337B2 (en) 2001-06-07 2006-09-12 Emc Corporation Data storage system with integrated switching
CN1200533C (en) * 2002-07-08 2005-05-04 华为技术有限公司 Communication method between interior modules of system apparatus
WO2008130299A1 (en) * 2007-04-20 2008-10-30 Telefonaktiebolaget L M Ericsson (Publ) A printed board assembly and a method
DE102009057273A1 (en) 2009-12-08 2011-06-09 Diehl Bgt Defence Gmbh & Co. Kg Electronic module
DE102009057272A1 (en) 2009-12-08 2011-06-09 Diehl Bgt Defence Gmbh & Co. Kg Electronic module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742765A (en) * 1996-06-19 1998-04-21 Pmc-Sierra, Inc. Combination local ATM segmentation and reassembly and physical layer device
US5796735A (en) * 1995-08-28 1998-08-18 Integrated Device Technology, Inc. System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol
US5845153A (en) * 1995-07-07 1998-12-01 Integrated Device Technology, Inc. Memory interface for asynchronous transfer mode segmentation and reassembly circuit
WO1999001009A2 (en) * 1997-06-27 1999-01-07 Nokia Networks Oy Processing of signalling messages in atm node

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5845153A (en) * 1995-07-07 1998-12-01 Integrated Device Technology, Inc. Memory interface for asynchronous transfer mode segmentation and reassembly circuit
US5796735A (en) * 1995-08-28 1998-08-18 Integrated Device Technology, Inc. System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol
US5742765A (en) * 1996-06-19 1998-04-21 Pmc-Sierra, Inc. Combination local ATM segmentation and reassembly and physical layer device
WO1999001009A2 (en) * 1997-06-27 1999-01-07 Nokia Networks Oy Processing of signalling messages in atm node

Also Published As

Publication number Publication date
AU4009800A (en) 2000-10-04
WO2000055742A2 (en) 2000-09-21

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