WO2018107467A1

WO2018107467A1 - Apparatus, method, and storage medium for providing preview of restricted video asset

Info

Publication number: WO2018107467A1
Application number: PCT/CN2016/110402
Authority: WO
Inventors: Wei Zhu; Yong Yang
Original assignee: Thomson Licensing
Priority date: 2016-12-16
Filing date: 2016-12-16
Publication date: 2018-06-21

Abstract

Exemplary apparatuses, methods and computer program products are provided for improved processing of video asset. In one exemplary embodiment, a partial view or preview of a restricted video asset is provided by taking advantage of the optional feature provided by the H. 265 High Efficiency Video Coding (HEVC) standard of being able to partition a picture or a frame of the video asset into rectangular regions called tiles. Accordingly, at the encoder, one or more selected ones of the tiles of a picture or a frame of a restricted video asset are scrambled while the other tiles are not scrambled to provide a partial preview of the restricted video asset.

Description

APPARATUS, METHOD, AND STORAGE MEDIUM FOR PROVIDING PREVIEW OF RESTRICTED VIDEO ASSET

BACKGROUND Technical Field

The present principles generally relate to electronic apparatuses, methods and computer program products for improved processing of video asset, and in particular, to providing a partial view or preview of a restricted video asset by taking advantage of the optional feature provided by the H. 265 High Efficiency Video Coding (HEVC) standard of being able to partition a picture or a frame of the video asset into rectangular regions called tiles.

Background Information

This section is intended to introduce to the reader various aspects of background information which may be related to various aspects of the present principles that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present principles. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

H. 265 High-Efficiency Video Coding (HEVC) standard is the recent video coding standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG) . The main goal of the HEVC standardization effort is to enable significantly improved compression performance relative to existing standards such as e.g., H. 264 H. 264/MPEG-4 AVC (Advanced Video Coding) .

Some new features are introduced in the HEVC standard to enhance parallel processing capability and/or to modify the structuring of slice data for packetization purposes. Each of them may have benefits in different particular application contexts, and it is generally up to the implementer of an encoder or decoder to determine whether and how to take advantage of these features.

One of these features is the optional use of tiles for the HEVC video coding/decoding. This feature of H. 265 allows the partition a picture or a frame of a video asset into rectangular regions called tiles. The main purpose of tiles is to take advantage of parallel processing. As is well-known in the art and as used herewith, parallel processing is a technique for duplicating function units to operate different tasks and/or signals concurrently. Parallel processing may refer to either concurrent processing by more than one processors, and/or concurrently processing by a processor having one or more processing cores, and/or concurrent processing by a processor using multiple software modules running in parallel.

In H. 265, tiles are independently-decodable regions of a picture or frame that are encoded with some shared header information. Therefore, besides being able to be processed in parallel, they could additionally be used for the purpose of random access to local regions of video pictures. A typical tile configuration of a picture consists of segmenting the picture or frame into square regions with approximately equal numbers of coding tree units (CTUs) in each tile.

A coding tree unit (CTU) in HEVC is a similar structure of a macroblock in H. 264. CTU in HEVC has a size selected by the encoder and can be larger than a traditional macroblock. The CTU consists of a luma coding tree block (CTB) and the corresponding chroma CTBs and syntax elements. The size L x L of a luma CTB can be chosen as L ＝ 16, 32, or 64 samples, with the larger sizes typically enabling better compression. HEVC then supports a partitioning of the CTBs into smaller blocks using a tree structure and quadtree-like signaling. Tiles in HEVC provide parallelism at a more coarse level (picture/sub-picture) of granularity, and no sophisticated synchronization of threads is necessary for their use.

SUMMARY

The present principles recognize that it is advantageous to be able to provide a partial view or preview of a restricted video asset by taking advantage of the coding/decoding features of the tiles in the H. 265 HEVC video coding/decoding standard. As used herewith, a restricted video asset is a video asset which is blocked or is scrambled at least partially because of e.g., the lack of viewing right by the viewer. An example of a restricted video asset is e.g., a pay-per-view event, movie or TV show, a premium channel such as HBO or Showtime, and etc. Accordingly, the present principles provide for the preview of a restricted video asset by scrambling only a selected number of tiles on a video frame and by not scrambling all of the tiles of the video frames of the video content, as well as by parallel processing of these tiles.

Accordingly, in an exemplary embodiment of the present principles, a video encoder for encoding a video asset is provided, comprising: an input configured to receive a sequence of video frames representing the video asset； and at least one processor configured to divide each frame of the sequence of the video frames into a plurality of regions of same size and shape, such as squares, wherein the plurality of regions of the each frame are encoded for parallel decoding to decode an encoded frame encoded by the video encoder； and the at least one processor is further configured to scramble at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions.

In another exemplary embodiment, a video decoder for providing a partial view of a restricted video asset is provided, comprising: an input configured to receive a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, such as squares, the plurality of regions are encoded for parallel decoding, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and at least one processor configured to decode in parallel the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.

In another exemplary embodiment, a method performed by a video encoder for encoding a video asset is provided, comprising: receiving a sequence of video frames representing the video asset； dividing each frame of the sequence of the video frames into a plurality of regions of same size and shape, such as squares, wherein the plurality of regions of the each frame are encoded for parallel decoding； and scrambling at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions.

In another exemplary embodiment, a method performed by a video decoder for providing a partial view of a restricted video asset, comprising: receiving a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, such as squares, the plurality of regions are encoded for parallel decoding, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and parallel decoding the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.

In another exemplary embodiment, a computer program product stored in a non-transitory computer-readable storage medium for encoding a video asset is provided, comprising computer-executable instructions for: receiving a sequence of video frames representing the video asset； dividing each frame of the sequence of the video frames into a plurality of regions of same size and shape, such as squares, wherein the plurality of regions of the each frame are encoded for parallel decoding； and scrambling at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions.

In another exemplary embodiment, a computer program product stored in a non-transitory computer-readable storage medium for providing a partial view of a restricted video asset is provided, comprising computer-executable instructions for: receiving a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions, of same size and shape, such as squares, the plurality of regions are encoded for parallel decoding, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and parallel decoding the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.

In another exemplary embodiment, a video decoder for providing a full view of a restricted video asset is provided, comprising: an input configured to receive a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions, of same size and shape, such as squares, the plurality of regions are encoded for parallel decoding, and at least a selected one of the plurality of the regions of the each frame is scrambled while others of the plurality of regions is unscrambled； and at least one processor configured to descramble and decode the at least scrambled selected one of the plurality of the regions, and decode the other unscrambled regions of the each frame to provide a fully decoded and unscrambled frames of the restricted video asset for the full view.

DETAILED DESCRIPTION OF THE DRAWINGS

The above-mentioned and other features and advantages of the present principles, and the manner of attaining them, will become more apparent and the present principles will be better understood by reference to the following description of embodiments of the present principles taken in conjunction with the accompanying drawings, wherein:

Fig. 1 shows an exemplary system according to an embodiment；

Fig. 2 shows an exemplary process according to an embodiment；

Fig. 3 shows another exemplary process according to an embodiment；

Fig. 4 illustrates an exemplary encoding according to an embodiment；

Fig. 5 illustrates exemplary packetizations according to an embodiment；

Fig. 6 also illustrates exemplary packetizations according to an embodiment；

Fig. 7 illustrates an exemplary decoding according to an embodiment； and

Fig. 8 also illustrates an exemplary decoding according to an embodiment.

The examples set out herein illustrate exemplary embodiments of the present principles. Such examples are not to be construed as limiting the scope of the present principles in any manner.

DETAILED DESCRIPTION

The present embodiments provide for a partial view or preview of a restricted video asset by taking advantage of the optional feature specified and provided by the H. 265 High Efficiency Video Coding (HEVC) standard of being able to partition a picture or a frame of a video asset into rectangular regions called tiles. Accordingly, at the encoder, one or more selected ones of the tiles of a picture or a frame of a restricted video asset are scrambled while the other tiles are not scrambled to provide a partial preview of the restricted video asset. At the decoder, the partially scrambled pictures or frames of the video asset, based on which selected tiles have been scrambled at the encoder, are decoded accordingly to provide the partially decoded pictures or frames of the video asset as a preview to a viewer.

The present description illustrates the present principles. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the present principles and are included within its spirit and scope.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the present principles and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

Moreover, all statements herein reciting principles, aspects, and embodiments of the present principles, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Thus, for example, it will be appreciated by those skilled in the art that the block diagrams presented herein represent conceptual views of illustrative circuitry embodying the present principles. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor ( "DSP" ) hardware, read-only memory ( "ROM" ) for storing software, random access memory ( "RAM" ) , and non-volatile storage.

Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

Reference in the specification to "one embodiment" , "an embodiment" , “an exemplary embodiment” of the present principles, or as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase "in one embodiment" , "in an embodiment" , “in an exemplary embodiment” , or as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following "/" , "and/or" , and "at least one of" , for example, in the cases of "A/B" , "A and/or B" and "at least one of A and B" , is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B) . As a further example, in the cases of "A, B, and/or C" and "at least one of A, B, and C" , such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C) . This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

Fig. 1 shows a simplified block diagram of an exemplary system 100 according to the present principles. The exemplary system 100 comprises an exemplary video encoder/transmitter device 110 coupled to an exemplary video decoder/receiver device 150, via

communication links

181 and 182, through a network 180. Also as shown in Fig. 1, the exemplary video encoder/transmitter 110 may comprise one or more processors 117 for processing the various data and for controlling various functions and components of the device 110. The one or more processors 117 may communicate with and control the various functions and components of the transmitter 110 via a representative control and data bus 118 as shown in Fig. 1. Likewise, the exemplary receiver 150 in Fig. 1 may also comprise one or more processors 157 for processing the various data and for controlling the various functions and components of the receiver 150. The one or more processors 157 may communicate with and control the various functions and components of the receiver 150 via a control and data bus 158, as shown in Fig. 1.

In addition, a

respective memory

116 and 156 may be provided for each of the transmitter 110 and receiver 150 as shown in Fig. 1. Each of the memory 116 and memory 156 may represent both a transitory memory such as RAM, and a non-transitory memory such as a ROM, a hard drive, a CD drive, a Blu-ray drive, and/or a flash memory. The

memories

116 and 156 are for processing and storing different data, files and information as necessary, including computer program products and software (e.g., as represented by the flow chart diagrams of Fig. 2 and Fig. 3, as to be discussed below) .

Additionally, the video encoder/transmitter device 110 includes a H. 265 HEVC compliant encoder 111. The H. 265 encoder 111 receives from a video source 120 a sequence of video frames corresponding to one or more video assets. The H. 265 encoder 111 then divides and encodes a video frame of the received video sequence into a plurality of regions. In one exemplary embodiment according the present principles, the plurality of the regions may be square regions and may correspond to tiles as provided and specified according to, and in compliant with, the H.265 HEVC video coding/decoding standard.

Fig. 4 illustrates exemplary operations of the H. 265 HEVC encoder 111 shown in Fig. 1. As mentioned previously, the support of parallel processing by using square partitions such as tiles is a significant feature of H. 265 HEVC coding/decoding standard. The tiles option may be used for parallel encoding and decoding, and works by dividing a picture/frame of a video asset into rectangular areas (or tiles) as shown, e.g., in an exemplary diagram 400 of Fig. 4.

As illustrated in Fig. 4, an exemplary video frame 401 of a video sequence of a video asset may be divided into e.g., 4 tiles, A, B, C, and D as shown in 402 of Fig. 4. Each tile A, B, C or D in 402 consists of an integer number of H. 265 coding tree units (CTUs) . Coding tree units are the basic processing units/blocks of the HEVC standard. They are conceptually similar to macroblock units that have been used in the several previous video standards such as e.g., H. 264 and MPEG 2. The CTUs are processed in a raster scan order within each tile, and the tiles themselves are processed in the same way. Prediction based on neighboring tiles is disabled, and therefore the processing of each tile is independent. In-loop filters, however, may operate over tile boundaries. In addition, de-blocking and sample adaptive offset (SAO) filtering may be processed in parallel. Therefore, filtering may be performed independently inside each tile, and tile boundaries may be processed by in-loop filters in a final pass.

In accordance with the present principles as shown in Fig. 4, the video frame 401 may be divided into four square regions or tiles A, B, C and D as shown in 402, and then the divided tiles may be further processed and encoded in parallel into the sequence of tiles data as shown in 404, using e.g., multi-core parallel encoding processes and/or multi-processor encoders A-D, as shown in 403 of Fig. 4.

Returning to Fig. 1, the exemplary video encoder/transmitter 110 further comprises a tile selector 112 in order to select e.g., one or more tiles of A, B, C, and D of the video frame 401 as shown in Fig. 4 for the scrambling/encrypting to be performed by a tile scrambler/conditional access system 113 of the exemplary video encoder/transmitter 110. In one exemplary embodiment, tiles B, C and D of the video frame 401 are selected by the tile selector 112 to be scrambled by the tile scrambler 113, and only tile A of the video frame 401 is not selected by the tile selector 112 for the scrambling. As used herewith, the added prime symbol (′) to a tile labeling letter denotes that the tile is scrambled, such as e.g., Tile B’, Tile C’ and Tile D’ shown in 801 of Fig. 8. Accordingly, the resulting exemplary partially scrambled video frame 401 is illustrated e.g. in 803 of Fig. 8. That is, the video frame shown in 803 of Fig. 8 has only one region, tile A, as being un-scrambled and is thus viewable by the viewer in order to provide a partial view or preview of a restricted video asset.

Video scrambling/conditional access technologies for digital video which may be used herewith are well known in the art and will not be described in detail. For example, conditional access system (CAS) for Digital Video Broadcasting (DVB) standards are defined in the specification documents for DVB-CA (conditional access) , DVB-CSA (the common scrambling algorithm) and DVB-CI (the Common Interface) . These standards define a method by which one can scramble a digital-television stream, with access provided only to those with valid decryption smart-cards and/or an access control key. The DVB specifications for conditional access are available from the standards page on the DVB website. This is achieved by a combination of scrambling and encryption. The data stream is scrambled with a 48-bit secret key, called the control word. Knowing the value of the control word at a given moment is of relatively little value, as under normal conditions, content providers will change the control word several times per minute. The control word is generated automatically in such a way that successive values are not usually predictable； the DVB specification recommends using a physical process for that.

In order for a receiver to unscramble the data stream, it must be permanently informed about the current value of the control word. In practice, it must be informed slightly in advance, so that no viewing interruption occurs. Encryption is used to protect the control word during transmission to the receiver: the control word is encrypted as an entitlement control message (ECM) . The CA subsystem in the receiver will decrypt the control word only when authorized to do so； that authority is sent to the receiver in the form of an entitlement management message (EMM) . The EMMs are specific to each subscriber, as identified by the smart card in his receiver, or to groups of subscribers, and are issued much less frequently than ECMs, usually at monthly intervals.

Returning again to Fig. 1, the video encoder/transmitter device 110 further comprises a transport stream packetizer 114 for packetization of the encoded tiles data into appropriate transport packets according to the present principles. Exemplary operations of the transport stream packetizer 114 according to the present principles are further illustrated in Fig. 5. In one exemplary embodiment, tiles data 404 shown in Fig. 4 are first packetized into the MEPG 2 packet elemental stream (PES) format as shown e.g., in 510 of Fig. 5, by the transport stream packetizer 114 shown in Fig. 1.

The transport stream packetizer 114 then further divides the PES data into smaller MPEG 2 Systems transport stream (TS) packets which are 188-bit in length as shown in e.g., 520 of Fig. 5. According to one exemplary aspect of the present principles, the transport stream packetizer 114 shown in Fig. 1 performs the transport stream packetization to make sure that each transport packet only includes data from one tile. At the same time of this packetization process, the relationship of which tile data belong to which MPEG 2 transport stream packet may be recorded and this information may be provided to a downstream video decoder/receiver to aid the decoding. In one exemplary embodiment, this scrambling information is provided as metadata or header information and may be used by the video decoder/receiver to decide which transport packet contains a scrambled tile.

Accordingly, 520 of Fig. 5 illustrates that a plurality of transport packets packetized by the transport stream packetizer 114 of Fig. 1, each of the transport packets having only PES data from one and only one tile. Similarly, 530 of Fig. 5 also illustrates a plurality of transport packets packetized by the transport stream packetizer 114 of Fig. 1, and each of the transport packets having PES data from one and only one tile. Additionally, 530 illustrates that one or more of the tiles may have been scrambled by the tile scrambler/conditional access system 113 of Fig. 1, as shown by e.g., TileD’₁ and TileD’_n in 530 of Fig. 5.

Returning again to Fig. 1, video encoder/transmitter 110 further comprises an output communication port 115 coupled to the transport stream packetizer 114. The output communication port 115 represents functions such as, e.g., modulating of signals and/or formatting of the signals into the applicable communication protocol for connection to a network 180 via a communication link 181. The connection 181 and the network 180 may represent communications through one or more of a cable network, a FIOS network, a Wi-Fi network, a cellphone network (e.g., 3G, 4G, LTE, 5G) , and/or the internet, and etc.

Fig. 1 also shows an exemplary video decoder/receiver 150 according to an embodiment. According to the embodiment, the exemplary device 110 shown in Fig. 1 may represent and is not limited to e.g., a set top box, a digital television, a computer, a tablet, a cellphone, a media server, and etc. The exemplary video decoder/receiver 150 comprises an input communication port 155 for receiving the encoded and modulated signal representing a sequence of the encoded video frames encoded by and transmitted from the exemplary video encoder/transmitter 110 of Fig. 1. The input communication port 155 performs, e.g., the demodulating and communication protocol interfacing functions so that the received information may be further processed by the exemplary video decoder/receiver 150.

In one exemplary embodiment according to the present principles, the signal received by the input communication port 155 comprises the plurality of MPEG 2 Systems transport stream packets as described previously. Again, an example of the transport stream packets having selected scrambled tiles in their associated packets of a restricted video asset is shown e.g., in 530 of Fig. 5, and an example of the transport stream packets having all un-scrambled tiles in all of the packets is shown in, e.g., 520 of Fig. 5. These received transport stream packets are further processed by a transport stream de-packetizer 154 shown in Fig. 1 to obtain the baseband tiles data such as e.g., shown in 404 of Fig. 4, 701 of Fig. 7 or 801 of Fig. 8.

According to the present principles, these tiles data are further processed by a tile descrambler 153 and a H. 265 HEVC decoder 151 of the exemplary video decoder/receiver 150 as shown in Fig. 1. In one exemplary embodiment, the tile descrambling function of 153 and tile decoding functions of 151 may be performed via parallel processing 159 by using e.g., one or more processors 157 or one or more cores of the at least one processor of the one or more processors 157, as illustrated in Fig. 1.

In one exemplary embodiment according to the present principles, at least one processor of the processors 157 of video decoder/receiver 150 as shown in Fig. 1 is configured to decode in parallel the at least one scrambled square region and the other unscrambled square region of the each frame of a restricted video asset to provide a partially unscrambled frame of the restricted video asset for the partial view. This is illustrated e.g., in Fig. 6. As shown in Fig. 6, a plurality of MPEG 2 transport streams packets 610 are received by the input communication port 155 of the video decoder/receiver 150 as shown in Fig. 1. As illustrated in 610 of Fig. 6, one or more of the transport packets may contain a tile that had been selected for scrambling at the video encoder/transmitter 110 of Fig. 1, such as e.g., TileD’1 and TileD’n shown in 610 of Fig. 6.

When a video decoder/receiver is authorized to descramble the scrambled tiles of a restricted video because e.g., the viewer has paid for the access to the restricted video and an access/descrambling key has been provided, all of the previously scrambled tiles are selected and descrambled by the exemplary tile descrambler 153 shown in Fig. 1. This is also illustrated in Fig. 7 in that all of the tiles A-D in 701 of Fig. 7 corresponding to a video frame 703 have been unscrambled as shown in Fig. 7, and the unscrambled tiles data are then provided to the exemplary H. 265 HEVC decoder 151 shown in Fig. 1 for decoding, so that a full, unscrambled view of the whole video frame is viewable by the authorized viewer, as shown in 703 of Fig. 7. In one exemplary embodiment, the video frame is provided to a display 170 of Fig. 1 so the viewer may view the video asset in full and unrestricted view as shown in 703 of Fig. 7.

On the other hand, however, if a video decoder/receiver is not authorized to descramble the scrambled tiles of a restricted video because e.g., the viewer does not have the proper access privilege for the restricted video, and the access/descrambling key is not available as shown in 630 of Fig. 6, then the previously scrambled tiles will not be descrambled by the tile descrambler 153 shown in Fig. 1. This is illustrated in Fig. 8 in that tiles B’-D’ remain scrambled as shown in 801 of Fig. 8, and that the scrambled tiles data B’-D’, as well as the unscrambled tile A data are then provided to the H. 265 HEVC decoder 151 shown in Fig. 1, so that a partial view of the video frame, with only the unscrambled tile A being viewable, is provided to the unauthorized viewer as shown in 803 of Fig. 8. In one exemplary embodiment, the video frame is provided to a display 170 of Fig. 1 so that the viewer may view the video asset in the preview mode with a partially obstructed view as shown in 803 of Fig. 8.

Fig. 2 represents a flow chart diagram of an exemplary encoding process 200 according to the present principles. The exemplary encoding process 200 may be implemented as a computer program product comprising computer executable instructions which may be executed by one or more processors (e.g., processor (s) 117 of the video encoder/transmitter 110 shown in Fig. 1) . The computer program product having the computer-executable instructions may be stored in a non-transitory computer-readable storage medium as represented by e.g., memory 116 of the exemplary device 110 in Fig. 1, as described above. One skilled in the art may readily recognize that the exemplary process 200 may also be implemented by using a combination of hardware and software (e.g., a firmware implementation) , and/or executed using programmable logic arrays (PLA) , and/or application-specific integrated circuit (ASIC) , etc., as already mentioned above.

The exemplary encoding process 200 in Fig. 2 starts at 205. Again, the exemplary process 200 may be performed by, e.g., the exemplary video encoder/transmitter 110 shown in Fig. 1. At 210, the exemplary process 200 receives a sequence of video frames representing the video asset, from e.g., a media source 120 shown in Fig. 1. At 215, the exemplary process 200 divides each frame of the sequence of the video frames into a plurality of regions of same size and shape, such as squares, wherein the plurality of regions of the each frame are encoded for parallel decoding. A decoder (e.g., video decoder/receiver 150 shown in Fig. 1) decodes an encoded frame encoded by the video encoder 110. At 220, the exemplary process 200 scrambles at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions. In one exemplary embodiment as already described above, the plurality of regions may correspond to tiles as specified and provided by the H. 265 HEVC standard. Also, according to the present principles, the selected ones of the plurality of regions of the each frame may be selected by e.g., tile selector 112 and are scrambled by e.g., tile scrambler 113 of the exemplary device 110 as shown in Fig. 1.

At 225 of Fig. 2, the exemplary process 200 may transport each of the scrambled selected at least one of the plurality of regions using its own transport packet. In one exemplary embodiment, the transport packet may be, e.g., an MEPG-2 Systems transport packet with 188 bits.

Fig. 3 represents a flow chart diagram of an exemplary decoding process 300 according to the present principles. The exemplary decoding process 300 may be implemented as a computer program product comprising computer executable instructions which may be executed by one or more processors (e.g., processor (s) 157 of the video decoder/receiver 150 shown in Fig. 1) . The computer program product having the computer-executable instructions may be stored in a non-transitory computer-readable storage medium as represented by e.g., memory 156 of the exemplary device 150 in Fig. 1, as described above. One skilled in the art may readily recognize that the exemplary process 300 may also be implemented by using a combination of hardware and software (e.g., a firmware implementation) , and/or executed using programmable logic arrays (PLA) , and/or application-specific integrated circuit (ASIC) , etc., as already mentioned above.

The exemplary decoding process 300 in Fig. 3 starts at 305. At 310, the exemplary process 300 receives a sequence of encoded video frames representing a restricted or partially scrambled video asset, and each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, such as squares. The plurality of regions are encoded for parallel decoding and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled. A video decoder (e.g., video decoder/receiver 150 as shown in Fig. 1) is used to decode the encoded the video asset. In one exemplary embodiment as already described above, the plurality of regions may correspond to tiles as specified and provided by the H. 265 HEVC standard. In another exemplary embodiment, the scrambled plurality of regions are each transported using its own transport packet. In yet another exemplary embodiment, the transport packet may be an MEPG-2 systems transport packet with 188 bits.

According the present principles, at step 315 of Fig. 3, the exemplary process 300 determines whether the video decoder/receiver is authorized or has the viewing right to view the restricted video in the unscrambled format. If the determination is no, then at 320, the exemplary decoding process 300 decodes in parallel the at least one scrambled region and the other unscrambled regions of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view. On the other hand, if the determination is yes, then at 325, the exemplary decoding process 300 descrambles and decodes the at least scrambled selected one of the plurality of the regions, and decodes the other unscrambled regions of the each frame to provide a fully decoded and unscrambled frames of the restricted video asset for full, unrestricted view.

While several embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the functions and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the present embodiments. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings herein is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereof, the embodiments disclosed may be practiced otherwise than as specifically described and claimed. The present embodiments are directed to each individual feature, system, article, material and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials and/or methods, if such features, systems, articles, materials and/or methods are not mutually inconsistent, is included within the scope of the present embodiment.

Claims

A video encoder for encoding a video asset, comprising:

an input configured to receive a sequence of video frames representing the video asset； and

at least one processor configured to divide each frame of the sequence of the video frames into a plurality of regions of same size and shape, wherein the plurality of regions of the each frame are encoded for parallel decoding； and the at least one processor is further configured to scramble at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of square regions.
The video encoder of claim 1 wherein the plurality of the regions are H. 265 HEVC tiles.
The video encoder of claim 2 wherein each of the scrambled selected at least one of the plurality of regions is transported using its own transport packet.
The video encoder of claim 3 wherein the transport packet is a MEPG-2 systems transport packet with 188 bits.
A video decoder for providing a partial view of a restricted video asset, comprising:

an input configured to receive a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, the plurality of regions are encoded for parallel decoding by the video decoder, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and

at least one processor configured to decode in parallel the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.
The video decoder of claim 5 wherein the plurality of the regions are H. 265 HEVC tiles.
The video decoder of claim 6 wherein each of the scrambled selected one of the plurality of regions is transported using its own transport packet.
The video decoder of claim 7 wherein the transport packet is a MEPG-2 systems transport packet with 188 bits.
A method performed by a video encoder for encoding a video asset, comprising:

receiving a sequence of video frames representing the video asset；

dividing each frame of the sequence of the video frames into a plurality of regions of same size and shape, wherein the plurality of regions of the each frame are encoded for parallel decoding by a decoder； and

scrambling at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions.
The method of claim 9 wherein the plurality of the regions are H. 265 HEVC tiles.
The method of claim 10 further comprising transporting each of the scrambled selected at least one of the plurality of regions using its own transport packet.
The method of claim 11 wherein the transport packet is a MEPG-2 systems transport packet with 188 bits.
A method performed by a video decoder for providing a partial view of a restricted video asset, comprising:

receiving a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, the plurality of regions are encoded for parallel decoding, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and

parallel decoding the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.
The method of claim 13 wherein the plurality of the regions are H. 265 HEVC tiles.
The method of claim 14 wherein each of the scrambled selected one of the plurality of regions is transported using its own transport packet.
The method of claim 15 wherein the transport packet is a MEPG-2 systems transport packet with 188 bits.
A computer program product stored in a non-transitory computer-readable storage medium for encoding a video asset, comprising computer-executable instructions for:

receiving a sequence of video frames representing the video asset；

dividing each frame of the sequence of the video frames into a plurality of regions of same size and shape, wherein the plurality of regions of the each frame are encoded for parallel decoding to decode an encoded frame encoded by the video encoder； and

scrambling at least a selected one of the plurality of regions of the each frame while not scrambling other of the plurality of regions.
A computer program product stored in a non-transitory computer-readable storage medium for providing a partial view of a restricted video asset, comprising computer-executable instructions for:

receiving a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, the plurality of regions are encoded for parallel decoding by the video decoder, and at least a selected one of the plurality of the regions of the each frame is scrambled while other of the plurality of regions is unscrambled； and

parallel decoding the at least one scrambled region and the other unscrambled region of the each frame to provide a partially unscrambled frame of the restricted video asset for the partial view.
A video decoder for providing a full view of a restricted video asset, comprising:

an input configured to receive a sequence of encoded video frames representing the restricted video asset, wherein each frame of the sequence of the encoded video frames is divided into a plurality of regions of same size and shape, the plurality of regions are encoded for parallel decoding by the video decoder, and at least a selected one of the plurality of the regions of the each frame is scrambled while others of the plurality of regions is unscrambled； and

at least one processor configured to descramble and decode the at least scrambled selected one of the plurality of the regions, and decode the other unscrambled regions of the each frame to provide a fully decoded and unscrambled frames of the restricted video asset for the full view.