1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19#ifndef __RTL8188E_SPEC_H__ 20#define __RTL8188E_SPEC_H__ 21 22#ifndef BIT 23#define BIT(x) (1 << (x)) 24#endif 25 26#define BIT0 0x00000001 27#define BIT1 0x00000002 28#define BIT2 0x00000004 29#define BIT3 0x00000008 30#define BIT4 0x00000010 31#define BIT5 0x00000020 32#define BIT6 0x00000040 33#define BIT7 0x00000080 34#define BIT8 0x00000100 35#define BIT9 0x00000200 36#define BIT10 0x00000400 37#define BIT11 0x00000800 38#define BIT12 0x00001000 39#define BIT13 0x00002000 40#define BIT14 0x00004000 41#define BIT15 0x00008000 42#define BIT16 0x00010000 43#define BIT17 0x00020000 44#define BIT18 0x00040000 45#define BIT19 0x00080000 46#define BIT20 0x00100000 47#define BIT21 0x00200000 48#define BIT22 0x00400000 49#define BIT23 0x00800000 50#define BIT24 0x01000000 51#define BIT25 0x02000000 52#define BIT26 0x04000000 53#define BIT27 0x08000000 54#define BIT28 0x10000000 55#define BIT29 0x20000000 56#define BIT30 0x40000000 57#define BIT31 0x80000000 58 59/* 8192C Regsiter offset definition */ 60 61#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ 62#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ 63 64#define MAC_ADDR_LEN 6 65/* 8188E PKT_BUFF_ACCESS_CTRL value */ 66#define TXPKT_BUF_SELECT 0x69 67#define RXPKT_BUF_SELECT 0xA5 68#define DISABLE_TRXPKT_BUF_ACCESS 0x0 69 70 71/* 0x0000h ~ 0x00FFh System Configuration */ 72#define REG_SYS_ISO_CTRL 0x0000 73#define REG_SYS_FUNC_EN 0x0002 74#define REG_APS_FSMCO 0x0004 75#define REG_SYS_CLKR 0x0008 76#define REG_9346CR 0x000A 77#define REG_EE_VPD 0x000C 78#define REG_AFE_MISC 0x0010 79#define REG_SPS0_CTRL 0x0011 80#define REG_SPS_OCP_CFG 0x0018 81#define REG_RSV_CTRL 0x001C 82#define REG_RF_CTRL 0x001F 83#define REG_LDOA15_CTRL 0x0020 84#define REG_LDOV12D_CTRL 0x0021 85#define REG_LDOHCI12_CTRL 0x0022 86#define REG_LPLDO_CTRL 0x0023 87#define REG_AFE_XTAL_CTRL 0x0024 88#define REG_AFE_PLL_CTRL 0x0028 89#define REG_APE_PLL_CTRL_EXT 0x002c 90#define REG_EFUSE_CTRL 0x0030 91#define REG_EFUSE_TEST 0x0034 92#define REG_GPIO_MUXCFG 0x0040 93#define REG_GPIO_IO_SEL 0x0042 94#define REG_MAC_PINMUX_CFG 0x0043 95#define REG_GPIO_PIN_CTRL 0x0044 96#define REG_GPIO_INTM 0x0048 97#define REG_LEDCFG0 0x004C 98#define REG_LEDCFG1 0x004D 99#define REG_LEDCFG2 0x004E 100#define REG_LEDCFG3 0x004F 101#define REG_FSIMR 0x0050 102#define REG_FSISR 0x0054 103#define REG_HSIMR 0x0058 104#define REG_HSISR 0x005c 105#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS 106 * Multi-Function GPIO Pin Control. */ 107#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS 108 * Multi-Function GPIO Select. */ 109#define REG_BB_PAD_CTRL 0x0064 110#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS 111 * Multi-Function control source. */ 112#define REG_GPIO_OUTPUT 0x006c 113#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ 114#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ 115#define REG_MCUFWDL 0x0080 116#define REG_WOL_EVENT 0x0081 /* RTL8188E */ 117#define REG_MCUTSTCFG 0x0084 118#define REG_HMEBOX_E0 0x0088 119#define REG_HMEBOX_E1 0x008A 120#define REG_HMEBOX_E2 0x008C 121#define REG_HMEBOX_E3 0x008E 122#define REG_HMEBOX_EXT_0 0x01F0 123#define REG_HMEBOX_EXT_1 0x01F4 124#define REG_HMEBOX_EXT_2 0x01F8 125#define REG_HMEBOX_EXT_3 0x01FC 126#define REG_HIMR_88E 0x00B0 127#define REG_HISR_88E 0x00B4 128#define REG_HIMRE_88E 0x00B8 129#define REG_HISRE_88E 0x00BC 130#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection 131 * for RTL8723 */ 132#define REG_BIST_SCAN 0x00D0 133#define REG_BIST_RPT 0x00D4 134#define REG_BIST_ROM_RPT 0x00D8 135#define REG_USB_SIE_INTF 0x00E0 136#define REG_PCIE_MIO_INTF 0x00E4 137#define REG_PCIE_MIO_INTD 0x00E8 138#define REG_HPON_FSM 0x00EC 139#define REG_SYS_CFG 0x00F0 140#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ 141#define REG_TYPE_ID 0x00FC 142 143#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 144 145/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 146#define REG_CR 0x0100 147#define REG_PBP 0x0104 148#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 149#define REG_TRXDMA_CTRL 0x010C 150#define REG_TRXFF_BNDY 0x0114 151#define REG_TRXFF_STATUS 0x0118 152#define REG_RXFF_PTR 0x011C 153/* define REG_HIMR 0x0120 */ 154/* define REG_HISR 0x0124 */ 155#define REG_HIMRE 0x0128 156#define REG_HISRE 0x012C 157#define REG_CPWM 0x012F 158#define REG_FWIMR 0x0130 159#define REG_FTIMR 0x0138 160#define REG_FWISR 0x0134 161#define REG_PKTBUF_DBG_CTRL 0x0140 162#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 163#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 164#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 165#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 166#define REG_PKTBUF_DBG_DATA_L 0x0144 167#define REG_PKTBUF_DBG_DATA_H 0x0148 168 169#define REG_TC0_CTRL 0x0150 170#define REG_TC1_CTRL 0x0154 171#define REG_TC2_CTRL 0x0158 172#define REG_TC3_CTRL 0x015C 173#define REG_TC4_CTRL 0x0160 174#define REG_TCUNIT_BASE 0x0164 175#define REG_MBIST_START 0x0174 176#define REG_MBIST_DONE 0x0178 177#define REG_MBIST_FAIL 0x017C 178#define REG_32K_CTRL 0x0194 /* RTL8188E */ 179#define REG_C2HEVT_MSG_NORMAL 0x01A0 180#define REG_C2HEVT_CLEAR 0x01AF 181#define REG_MCUTST_1 0x01c0 182#define REG_FMETHR 0x01C8 183#define REG_HMETFR 0x01CC 184#define REG_HMEBOX_0 0x01D0 185#define REG_HMEBOX_1 0x01D4 186#define REG_HMEBOX_2 0x01D8 187#define REG_HMEBOX_3 0x01DC 188 189#define REG_LLT_INIT 0x01E0 190 191/* 0x0200h ~ 0x027Fh TXDMA Configuration */ 192#define REG_RQPN 0x0200 193#define REG_FIFOPAGE 0x0204 194#define REG_TDECTRL 0x0208 195#define REG_TXDMA_OFFSET_CHK 0x020C 196#define REG_TXDMA_STATUS 0x0210 197#define REG_RQPN_NPQ 0x0214 198 199/* 0x0280h ~ 0x02FFh RXDMA Configuration */ 200#define REG_RXDMA_AGG_PG_TH 0x0280 201#define REG_RXPKT_NUM 0x0284 202#define REG_RXDMA_STATUS 0x0288 203 204/* 0x0300h ~ 0x03FFh PCIe */ 205#define REG_PCIE_CTRL_REG 0x0300 206#define REG_INT_MIG 0x0304 /* Interrupt Migration */ 207#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ 208#define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ 209#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ 210#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ 211#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ 212#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ 213#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ 214#define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ 215#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ 216#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ 217#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ 218#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ 219#define REG_WATCH_DOG 0x0368 220 221/* RTL8723 series ------------------------------ */ 222#define REG_PCIE_HISR 0x03A0 223 224/* spec version 11 */ 225/* 0x0400h ~ 0x047Fh Protocol Configuration */ 226#define REG_VOQ_INFORMATION 0x0400 227#define REG_VIQ_INFORMATION 0x0404 228#define REG_BEQ_INFORMATION 0x0408 229#define REG_BKQ_INFORMATION 0x040C 230#define REG_MGQ_INFORMATION 0x0410 231#define REG_HGQ_INFORMATION 0x0414 232#define REG_BCNQ_INFORMATION 0x0418 233#define REG_TXPKT_EMPTY 0x041A 234 235#define REG_CPU_MGQ_INFORMATION 0x041C 236#define REG_FWHW_TXQ_CTRL 0x0420 237#define REG_HWSEQ_CTRL 0x0423 238#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 239#define REG_TXPKTBUF_MGQ_BDNY 0x0425 240#define REG_LIFETIME_EN 0x0426 241#define REG_MULTI_BCNQ_OFFSET 0x0427 242#define REG_SPEC_SIFS 0x0428 243#define REG_RL 0x042A 244#define REG_DARFRC 0x0430 245#define REG_RARFRC 0x0438 246#define REG_RRSR 0x0440 247#define REG_ARFR0 0x0444 248#define REG_ARFR1 0x0448 249#define REG_ARFR2 0x044C 250#define REG_ARFR3 0x0450 251#define REG_AGGLEN_LMT 0x0458 252#define REG_AMPDU_MIN_SPACE 0x045C 253#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 254#define REG_FAST_EDCA_CTRL 0x0460 255#define REG_RD_RESP_PKT_TH 0x0463 256#define REG_INIRTS_RATE_SEL 0x0480 257/* define REG_INIDATA_RATE_SEL 0x0484 */ 258#define REG_POWER_STATUS 0x04A4 259#define REG_POWER_STAGE1 0x04B4 260#define REG_POWER_STAGE2 0x04B8 261#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 262#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 263#define REG_STBC_SETTING 0x04C4 264#define REG_PROT_MODE_CTRL 0x04C8 265#define REG_MAX_AGGR_NUM 0x04CA 266#define REG_RTS_MAX_AGGR_NUM 0x04CB 267#define REG_BAR_MODE_CTRL 0x04CC 268#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 269#define REG_EARLY_MODE_CONTROL 0x4D0 270#define REG_NQOS_SEQ 0x04DC 271#define REG_QOS_SEQ 0x04DE 272#define REG_NEED_CPU_HANDLE 0x04E0 273#define REG_PKT_LOSE_RPT 0x04E1 274#define REG_PTCL_ERR_STATUS 0x04E2 275#define REG_TX_RPT_CTRL 0x04EC 276#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ 277#define REG_DUMMY 0x04FC 278 279/* 0x0500h ~ 0x05FFh EDCA Configuration */ 280#define REG_EDCA_VO_PARAM 0x0500 281#define REG_EDCA_VI_PARAM 0x0504 282#define REG_EDCA_BE_PARAM 0x0508 283#define REG_EDCA_BK_PARAM 0x050C 284#define REG_BCNTCFG 0x0510 285#define REG_PIFS 0x0512 286#define REG_RDG_PIFS 0x0513 287#define REG_SIFS_CTX 0x0514 288#define REG_SIFS_TRX 0x0516 289#define REG_TSFTR_SYN_OFFSET 0x0518 290#define REG_AGGR_BREAK_TIME 0x051A 291#define REG_SLOT 0x051B 292#define REG_TX_PTCL_CTRL 0x0520 293#define REG_TXPAUSE 0x0522 294#define REG_DIS_TXREQ_CLR 0x0523 295#define REG_RD_CTRL 0x0524 296/* Format for offset 540h-542h: */ 297/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting 298 * beacon content before TBTT. */ 299/* [7:4]: Reserved. */ 300/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding 301 * to send the beacon packet. */ 302/* [23:20]: Reserved */ 303/* Description: */ 304/* | */ 305/* |<--Setup--|--Hold------------>| */ 306/* --------------|---------------------- */ 307/* | */ 308/* TBTT */ 309/* Note: We cannot update beacon content to HW or send any AC packets during 310 * the time between Setup and Hold. */ 311#define REG_TBTT_PROHIBIT 0x0540 312#define REG_RD_NAV_NXT 0x0544 313#define REG_NAV_PROT_LEN 0x0546 314#define REG_BCN_CTRL 0x0550 315#define REG_BCN_CTRL_1 0x0551 316#define REG_MBID_NUM 0x0552 317#define REG_DUAL_TSF_RST 0x0553 318#define REG_BCN_INTERVAL 0x0554 319#define REG_DRVERLYINT 0x0558 320#define REG_BCNDMATIM 0x0559 321#define REG_ATIMWND 0x055A 322#define REG_BCN_MAX_ERR 0x055D 323#define REG_RXTSF_OFFSET_CCK 0x055E 324#define REG_RXTSF_OFFSET_OFDM 0x055F 325#define REG_TSFTR 0x0560 326#define REG_TSFTR1 0x0568 327#define REG_ATIMWND_1 0x0570 328#define REG_PSTIMER 0x0580 329#define REG_TIMER0 0x0584 330#define REG_TIMER1 0x0588 331#define REG_ACMHWCTRL 0x05C0 332 333/* define REG_FW_TSF_SYNC_CNT 0x04A0 */ 334#define REG_FW_RESET_TSF_CNT_1 0x05FC 335#define REG_FW_RESET_TSF_CNT_0 0x05FD 336#define REG_FW_BCN_DIS_CNT 0x05FE 337 338/* 0x0600h ~ 0x07FFh WMAC Configuration */ 339#define REG_APSD_CTRL 0x0600 340#define REG_BWOPMODE 0x0603 341#define REG_TCR 0x0604 342#define REG_RCR 0x0608 343#define REG_RX_PKT_LIMIT 0x060C 344#define REG_RX_DLK_TIME 0x060D 345#define REG_RX_DRVINFO_SZ 0x060F 346 347#define REG_MACID 0x0610 348#define REG_BSSID 0x0618 349#define REG_MAR 0x0620 350#define REG_MBIDCAMCFG 0x0628 351 352#define REG_USTIME_EDCA 0x0638 353#define REG_MAC_SPEC_SIFS 0x063A 354 355/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 356/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 357#define REG_R2T_SIFS 0x063C 358/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 359#define REG_T2T_SIFS 0x063E 360#define REG_ACKTO 0x0640 361#define REG_CTS2TO 0x0641 362#define REG_EIFS 0x0642 363 364/* RXERR_RPT */ 365#define RXERR_TYPE_OFDM_PPDU 0 366#define RXERR_TYPE_OFDM_false_ALARM 1 367#define RXERR_TYPE_OFDM_MPDU_OK 2 368#define RXERR_TYPE_OFDM_MPDU_FAIL 3 369#define RXERR_TYPE_CCK_PPDU 4 370#define RXERR_TYPE_CCK_false_ALARM 5 371#define RXERR_TYPE_CCK_MPDU_OK 6 372#define RXERR_TYPE_CCK_MPDU_FAIL 7 373#define RXERR_TYPE_HT_PPDU 8 374#define RXERR_TYPE_HT_false_ALARM 9 375#define RXERR_TYPE_HT_MPDU_TOTAL 10 376#define RXERR_TYPE_HT_MPDU_OK 11 377#define RXERR_TYPE_HT_MPDU_FAIL 12 378#define RXERR_TYPE_RX_FULL_DROP 15 379 380#define RXERR_COUNTER_MASK 0xFFFFF 381#define RXERR_RPT_RST BIT(27) 382#define _RXERR_RPT_SEL(type) ((type) << 28) 383 384/* Note: */ 385/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. 386 * The default value is always too small, but the WiFi TestPlan test 387 * by 25,000 microseconds of NAV through sending CTS in the air. 388 * We must update this value greater than 25,000 microseconds to pass 389 * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and 390 * the offset should be 0x0652. */ 391#define REG_NAV_UPPER 0x0652 /* unit of 128 */ 392 393/* WMA, BA, CCX */ 394/* define REG_NAV_CTRL 0x0650 */ 395#define REG_BACAMCMD 0x0654 396#define REG_BACAMCONTENT 0x0658 397#define REG_LBDLY 0x0660 398#define REG_FWDLY 0x0661 399#define REG_RXERR_RPT 0x0664 400#define REG_WMAC_TRXPTCL_CTL 0x0668 401 402/* Security */ 403#define REG_CAMCMD 0x0670 404#define REG_CAMWRITE 0x0674 405#define REG_CAMREAD 0x0678 406#define REG_CAMDBG 0x067C 407#define REG_SECCFG 0x0680 408 409/* Power */ 410#define REG_WOW_CTRL 0x0690 411#define REG_PS_RX_INFO 0x0692 412#define REG_UAPSD_TID 0x0693 413#define REG_WKFMCAM_CMD 0x0698 414#define REG_WKFMCAM_NUM_88E 0x698 415#define REG_RXFLTMAP0 0x06A0 416#define REG_RXFLTMAP1 0x06A2 417#define REG_RXFLTMAP2 0x06A4 418#define REG_BCN_PSR_RPT 0x06A8 419#define REG_BT_COEX_TABLE 0x06C0 420 421/* Hardware Port 2 */ 422#define REG_MACID1 0x0700 423#define REG_BSSID1 0x0708 424 425/* 0xFE00h ~ 0xFE55h USB Configuration */ 426#define REG_USB_INFO 0xFE17 427#define REG_USB_SPECIAL_OPTION 0xFE55 428#define REG_USB_DMA_AGG_TO 0xFE5B 429#define REG_USB_AGG_TO 0xFE5C 430#define REG_USB_AGG_TH 0xFE5D 431 432/* For normal chip */ 433#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 434#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 435#define REG_NORMAL_SIE_OPTIONAL 0xFE64 436#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ 437#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ 438#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C 439#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ 440#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 441#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ 442 443/* TODO: use these definition when using REG_xxx naming rule. */ 444/* NOTE: DO NOT Remove these definition. Use later. */ 445 446#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ 447#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ 448#define MSR (REG_CR + 2) /* Media Status reg */ 449#define ISR REG_HISR_88E 450/* Timing Sync Function Timer Register. */ 451#define TSFR REG_TSFTR 452 453#define PBP REG_PBP 454 455/* Redifine MACID register, to compatible prior ICs. */ 456/* MAC ID Register, Offset 0x0050-0x0053 */ 457#define IDR0 REG_MACID 458/* MAC ID Register, Offset 0x0054-0x0055 */ 459#define IDR4 (REG_MACID + 4) 460 461/* 9. Security Control Registers (Offset: ) */ 462/* IN 8190 Data Sheet is called CAMcmd */ 463#define RWCAM REG_CAMCMD 464/* Software write CAM input content */ 465#define WCAMI REG_CAMWRITE 466/* Software read/write CAM config */ 467#define RCAMO REG_CAMREAD 468#define CAMDBG REG_CAMDBG 469/* Security Configuration Register */ 470#define SECR REG_SECCFG 471 472/* Unused register */ 473#define UnusedRegister 0x1BF 474#define DCAM UnusedRegister 475#define PSR UnusedRegister 476#define BBAddr UnusedRegister 477#define PhyDataR UnusedRegister 478 479/* Min Spacing related settings. */ 480#define MAX_MSS_DENSITY_2T 0x13 481#define MAX_MSS_DENSITY_1T 0x0A 482 483/* EEPROM enable when set 1 */ 484#define CmdEEPROM_En BIT5 485/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ 486#define CmdEERPOMSEL BIT4 487#define Cmd9346CR_9356SEL BIT4 488 489/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ 490#define GPIOSEL_GPIO 0 491#define GPIOSEL_ENBT BIT5 492 493/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ 494/* GPIO pins input value */ 495#define GPIO_IN REG_GPIO_PIN_CTRL 496/* GPIO pins output value */ 497#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 498/* GPIO pins output enable when a bit is set to "1"; otherwise, 499 * input is configured. */ 500#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 501#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 502 503/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 504#define HSIMR_GPIO12_0_INT_EN BIT0 505#define HSIMR_SPS_OCP_INT_EN BIT5 506#define HSIMR_RON_INT_EN BIT6 507#define HSIMR_PDN_INT_EN BIT7 508#define HSIMR_GPIO9_INT_EN BIT25 509 510/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 511#define HSISR_GPIO12_0_INT BIT0 512#define HSISR_SPS_OCP_INT BIT5 513#define HSISR_RON_INT_EN BIT6 514#define HSISR_PDNINT BIT7 515#define HSISR_GPIO9_INT BIT25 516 517/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ 518/* 519Network Type 52000: No link 52101: Link in ad hoc network 52210: Link in infrastructure network 52311: AP mode 524Default: 00b. 525*/ 526#define MSR_NOLINK 0x00 527#define MSR_ADHOC 0x01 528#define MSR_INFRA 0x02 529#define MSR_AP 0x03 530 531/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ 532#define USB_INTR_CONTENT_C2H_OFFSET 0 533#define USB_INTR_CONTENT_CPWM1_OFFSET 16 534#define USB_INTR_CONTENT_CPWM2_OFFSET 20 535#define USB_INTR_CONTENT_HISR_OFFSET 48 536#define USB_INTR_CONTENT_HISRE_OFFSET 52 537 538/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ 539/* IOL config for REG_FDHM0(Reg0x88) */ 540#define CMD_INIT_LLT BIT0 541#define CMD_READ_EFUSE_MAP BIT1 542#define CMD_EFUSE_PATCH BIT2 543#define CMD_IOCONFIG BIT3 544#define CMD_INIT_LLT_ERR BIT4 545#define CMD_READ_EFUSE_MAP_ERR BIT5 546#define CMD_EFUSE_PATCH_ERR BIT6 547#define CMD_IOCONFIG_ERR BIT7 548 549/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ 550/* 8192C Response Rate Set Register (offset 0x181, 24bits) */ 551#define RRSR_1M BIT0 552#define RRSR_2M BIT1 553#define RRSR_5_5M BIT2 554#define RRSR_11M BIT3 555#define RRSR_6M BIT4 556#define RRSR_9M BIT5 557#define RRSR_12M BIT6 558#define RRSR_18M BIT7 559#define RRSR_24M BIT8 560#define RRSR_36M BIT9 561#define RRSR_48M BIT10 562#define RRSR_54M BIT11 563#define RRSR_MCS0 BIT12 564#define RRSR_MCS1 BIT13 565#define RRSR_MCS2 BIT14 566#define RRSR_MCS3 BIT15 567#define RRSR_MCS4 BIT16 568#define RRSR_MCS5 BIT17 569#define RRSR_MCS6 BIT18 570#define RRSR_MCS7 BIT19 571 572/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ 573/* WOL bit information */ 574#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 575#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 576 577/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ 578#define BW_OPMODE_20MHZ BIT2 579#define BW_OPMODE_5G BIT1 580 581/* 8192C CAM Config Setting (offset 0x250, 1 byte) */ 582#define CAM_VALID BIT15 583#define CAM_NOTVALID 0x0000 584#define CAM_USEDK BIT5 585 586#define CAM_CONTENT_COUNT 8 587 588#define CAM_NONE 0x0 589#define CAM_WEP40 0x01 590#define CAM_TKIP 0x02 591#define CAM_AES 0x04 592#define CAM_WEP104 0x05 593#define CAM_SMS4 0x6 594 595#define TOTAL_CAM_ENTRY 32 596#define HALF_CAM_ENTRY 16 597 598#define CAM_CONFIG_USEDK true 599#define CAM_CONFIG_NO_USEDK false 600 601#define CAM_WRITE BIT16 602#define CAM_READ 0x00000000 603#define CAM_POLLINIG BIT31 604 605#define SCR_UseDK 0x01 606#define SCR_TxSecEnable 0x02 607#define SCR_RxSecEnable 0x04 608 609/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ 610#define WOW_PMEN BIT0 /* Power management Enable. */ 611#define WOW_WOMEN BIT1 /* WoW function on or off. */ 612#define WOW_MAGIC BIT2 /* Magic packet */ 613#define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 614 615/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ 616/* 8188 IMR/ISR bits */ 617#define IMR_DISABLED_88E 0x0 618/* IMR DW0(0x0060-0063) Bit 0-31 */ 619#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ 620#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ 621#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 622#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 623#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ 624#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ 625#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 626#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ 627#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ 628#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 629#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 630#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ 631#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ 632#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 633#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 634#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 635#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ 636#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ 637#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ 638#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ 639#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ 640#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ 641#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ 642#define IMR_ROK_88E BIT0 /* Receive DMA OK */ 643 644/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 645#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ 646#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ 647#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ 648#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ 649#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ 650#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ 651#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ 652#define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */ 653#define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */ 654#define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */ 655#define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */ 656#define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */ 657#define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */ 658#define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */ 659#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */ 660#define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */ 661#define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */ 662#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ 663#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ 664 665#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ 666 667/* 8192C EFUSE */ 668#define HWSET_MAX_SIZE 256 669#define HWSET_MAX_SIZE_88E 512 670 671/*=================================================================== 672===================================================================== 673Here the register defines are for 92C. When the define is as same with 92C, 674we will use the 92C's define for the consistency 675So the following defines for 92C is not entire!!!!!! 676===================================================================== 677=====================================================================*/ 678/* 679Based on Datasheet V33---090401 680Register Summary 681Current IOREG MAP 6820x0000h ~ 0x00FFh System Configuration (256 Bytes) 6830x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 6840x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 6850x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 6860x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 6870x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 6880x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 6890x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 6900x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 691*/ 692/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ 693/* Note: */ 694/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet 695 * RTL8192S/RTL8192C are wrong, */ 696/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, 697 * and BK - Bit3. */ 698/* 8723 and 88E may be not correct either in the earlier version. */ 699#define StopBecon BIT6 700#define StopHigh BIT5 701#define StopMgt BIT4 702#define StopBK BIT3 703#define StopBE BIT2 704#define StopVI BIT1 705#define StopVO BIT0 706 707/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ 708#define RCR_APPFCS BIT31 /* WMAC append FCS after payload */ 709#define RCR_APP_MIC BIT30 710#define RCR_APP_PHYSTS BIT28 711#define RCR_APP_ICV BIT29 712#define RCR_APP_PHYST_RXFF BIT28 713#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ 714#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ 715#define RCR_LSIGEN BIT23 716#define RCR_MFBEN BIT22 717#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ 718#define RCR_AMF BIT13 /* Accept management type frame */ 719#define RCR_ACF BIT12 /* Accept control type frame */ 720#define RCR_ADF BIT11 /* Accept data type frame */ 721#define RCR_AICV BIT9 /* Accept ICV error packet */ 722#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ 723#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet 724 * (Rx beacon, probe rsp) */ 725#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/ 726#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ 727#define RCR_APWRMGT BIT5 /* Accept power management pkt*/ 728#define RCR_ADD3 BIT4 /* Accept address 3 match pkt */ 729#define RCR_AB BIT3 /* Accept broadcast packet */ 730#define RCR_AM BIT2 /* Accept multicast packet */ 731#define RCR_APM BIT1 /* Accept physical match pkt */ 732#define RCR_AAP BIT0 /* Accept all unicast packet */ 733#define RCR_MXDMA_OFFSET 8 734#define RCR_FIFO_OFFSET 13 735 736/* 0xFE00h ~ 0xFE55h USB Configuration */ 737#define REG_USB_INFO 0xFE17 738#define REG_USB_SPECIAL_OPTION 0xFE55 739#define REG_USB_DMA_AGG_TO 0xFE5B 740#define REG_USB_AGG_TO 0xFE5C 741#define REG_USB_AGG_TH 0xFE5D 742 743#define REG_USB_HRPWM 0xFE58 744#define REG_USB_HCPWM 0xFE57 745/* 8192C Regsiter Bit and Content definition */ 746/* 0x0000h ~ 0x00FFh System Configuration */ 747 748/* 2 SYS_ISO_CTRL */ 749#define ISO_MD2PP BIT(0) 750#define ISO_UA2USB BIT(1) 751#define ISO_UD2CORE BIT(2) 752#define ISO_PA2PCIE BIT(3) 753#define ISO_PD2CORE BIT(4) 754#define ISO_IP2MAC BIT(5) 755#define ISO_DIOP BIT(6) 756#define ISO_DIOE BIT(7) 757#define ISO_EB2CORE BIT(8) 758#define ISO_DIOR BIT(9) 759#define PWC_EV12V BIT(15) 760 761/* 2 SYS_FUNC_EN */ 762#define FEN_BBRSTB BIT(0) 763#define FEN_BB_GLB_RSTn BIT(1) 764#define FEN_USBA BIT(2) 765#define FEN_UPLL BIT(3) 766#define FEN_USBD BIT(4) 767#define FEN_DIO_PCIE BIT(5) 768#define FEN_PCIEA BIT(6) 769#define FEN_PPLL BIT(7) 770#define FEN_PCIED BIT(8) 771#define FEN_DIOE BIT(9) 772#define FEN_CPUEN BIT(10) 773#define FEN_DCORE BIT(11) 774#define FEN_ELDR BIT(12) 775#define FEN_DIO_RF BIT(13) 776#define FEN_HWPDN BIT(14) 777#define FEN_MREGEN BIT(15) 778 779/* 2 APS_FSMCO */ 780#define PFM_LDALL BIT(0) 781#define PFM_ALDN BIT(1) 782#define PFM_LDKP BIT(2) 783#define PFM_WOWL BIT(3) 784#define EnPDN BIT(4) 785#define PDN_PL BIT(5) 786#define APFM_ONMAC BIT(8) 787#define APFM_OFF BIT(9) 788#define APFM_RSM BIT(10) 789#define AFSM_HSUS BIT(11) 790#define AFSM_PCIE BIT(12) 791#define APDM_MAC BIT(13) 792#define APDM_HOST BIT(14) 793#define APDM_HPDN BIT(15) 794#define RDY_MACON BIT(16) 795#define SUS_HOST BIT(17) 796#define ROP_ALD BIT(20) 797#define ROP_PWR BIT(21) 798#define ROP_SPS BIT(22) 799#define SOP_MRST BIT(25) 800#define SOP_FUSE BIT(26) 801#define SOP_ABG BIT(27) 802#define SOP_AMB BIT(28) 803#define SOP_RCK BIT(29) 804#define SOP_A8M BIT(30) 805#define XOP_BTCK BIT(31) 806 807/* 2 SYS_CLKR */ 808#define ANAD16V_EN BIT(0) 809#define ANA8M BIT(1) 810#define MACSLP BIT(4) 811#define LOADER_CLK_EN BIT(5) 812 813/* 2 9346CR */ 814 815#define BOOT_FROM_EEPROM BIT(4) 816#define EEPROM_EN BIT(5) 817 818/* 2 SPS0_CTRL */ 819 820/* 2 SPS_OCP_CFG */ 821 822/* 2 RF_CTRL */ 823#define RF_EN BIT(0) 824#define RF_RSTB BIT(1) 825#define RF_SDMRSTB BIT(2) 826 827/* 2 LDOV12D_CTRL */ 828#define LDV12_EN BIT(0) 829#define LDV12_SDBY BIT(1) 830#define LPLDO_HSM BIT(2) 831#define LPLDO_LSM_DIS BIT(3) 832#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 833 834/* 2EFUSE_CTRL */ 835#define ALD_EN BIT(18) 836#define EF_PD BIT(19) 837#define EF_FLAG BIT(31) 838 839/* 2 EFUSE_TEST (For RTL8723 partially) */ 840#define EF_TRPT BIT(7) 841/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 842#define EF_CELL_SEL (BIT(8)|BIT(9)) 843#define LDOE25_EN BIT(31) 844#define EFUSE_SEL(x) (((x) & 0x3) << 8) 845#define EFUSE_SEL_MASK 0x300 846#define EFUSE_WIFI_SEL_0 0x0 847#define EFUSE_BT_SEL_0 0x1 848#define EFUSE_BT_SEL_1 0x2 849#define EFUSE_BT_SEL_2 0x3 850 851#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ 852#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ 853 854/* 2 8051FWDL */ 855/* 2 MCUFWDL */ 856#define MCUFWDL_EN BIT(0) 857#define MCUFWDL_RDY BIT(1) 858#define FWDL_ChkSum_rpt BIT(2) 859#define MACINI_RDY BIT(3) 860#define BBINI_RDY BIT(4) 861#define RFINI_RDY BIT(5) 862#define WINTINI_RDY BIT(6) 863#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ 864#define ROM_DLEN BIT(19) 865#define CPRST BIT(23) 866 867/* 2 REG_SYS_CFG */ 868#define XCLK_VLD BIT(0) 869#define ACLK_VLD BIT(1) 870#define UCLK_VLD BIT(2) 871#define PCLK_VLD BIT(3) 872#define PCIRSTB BIT(4) 873#define V15_VLD BIT(5) 874#define SW_OFFLOAD_EN BIT(7) 875#define SIC_IDLE BIT(8) 876#define BD_MAC2 BIT(9) 877#define BD_MAC1 BIT(10) 878#define IC_MACPHY_MODE BIT(11) 879#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 880#define BT_FUNC BIT(16) 881#define VENDOR_ID BIT(19) 882#define PAD_HWPD_IDN BIT(22) 883#define TRP_VAUX_EN BIT(23) /* RTL ID */ 884#define TRP_BT_EN BIT(24) 885#define BD_PKG_SEL BIT(25) 886#define BD_HCI_SEL BIT(26) 887#define TYPE_ID BIT(27) 888 889#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 890#define CHIP_VER_RTL_SHIFT 12 891 892/* 2REG_GPIO_OUTSTS (For RTL8723 only) */ 893#define EFS_HCI_SEL (BIT(0)|BIT(1)) 894#define PAD_HCI_SEL (BIT(2)|BIT(3)) 895#define HCI_SEL (BIT(4)|BIT(5)) 896#define PKG_SEL_HCI BIT(6) 897#define FEN_GPS BIT(7) 898#define FEN_BT BIT(8) 899#define FEN_WL BIT(9) 900#define FEN_PCI BIT(10) 901#define FEN_USB BIT(11) 902#define BTRF_HWPDN_N BIT(12) 903#define WLRF_HWPDN_N BIT(13) 904#define PDN_BT_N BIT(14) 905#define PDN_GPS_N BIT(15) 906#define BT_CTL_HWPDN BIT(16) 907#define GPS_CTL_HWPDN BIT(17) 908#define PPHY_SUSB BIT(20) 909#define UPHY_SUSB BIT(21) 910#define PCI_SUSEN BIT(22) 911#define USB_SUSEN BIT(23) 912#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 913 914/* 2SYS_CFG */ 915#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ 916 917/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 918 919/* 2 Function Enable Registers */ 920/* 2 CR */ 921 922#define HCI_TXDMA_EN BIT(0) 923#define HCI_RXDMA_EN BIT(1) 924#define TXDMA_EN BIT(2) 925#define RXDMA_EN BIT(3) 926#define PROTOCOL_EN BIT(4) 927#define SCHEDULE_EN BIT(5) 928#define MACTXEN BIT(6) 929#define MACRXEN BIT(7) 930#define ENSWBCN BIT(8) 931#define ENSEC BIT(9) 932#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 933 934/* Network type */ 935#define _NETTYPE(x) (((x) & 0x3) << 16) 936#define MASK_NETTYPE 0x30000 937#define NT_NO_LINK 0x0 938#define NT_LINK_AD_HOC 0x1 939#define NT_LINK_AP 0x2 940#define NT_AS_AP 0x3 941 942/* 2 PBP - Page Size Register */ 943#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 944#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 945#define _PSRX_MASK 0xF 946#define _PSTX_MASK 0xF0 947#define _PSRX(x) (x) 948#define _PSTX(x) ((x) << 4) 949 950#define PBP_64 0x0 951#define PBP_128 0x1 952#define PBP_256 0x2 953#define PBP_512 0x3 954#define PBP_1024 0x4 955 956/* 2 TX/RXDMA */ 957#define RXDMA_ARBBW_EN BIT(0) 958#define RXSHFT_EN BIT(1) 959#define RXDMA_AGG_EN BIT(2) 960#define QS_VO_QUEUE BIT(8) 961#define QS_VI_QUEUE BIT(9) 962#define QS_BE_QUEUE BIT(10) 963#define QS_BK_QUEUE BIT(11) 964#define QS_MANAGER_QUEUE BIT(12) 965#define QS_HIGH_QUEUE BIT(13) 966 967#define HQSEL_VOQ BIT(0) 968#define HQSEL_VIQ BIT(1) 969#define HQSEL_BEQ BIT(2) 970#define HQSEL_BKQ BIT(3) 971#define HQSEL_MGTQ BIT(4) 972#define HQSEL_HIQ BIT(5) 973 974/* For normal driver, 0x10C */ 975#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 976#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 977#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 978#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 979#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 980#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 981 982#define QUEUE_LOW 1 983#define QUEUE_NORMAL 2 984#define QUEUE_HIGH 3 985 986/* 2 TRXFF_BNDY */ 987 988/* 2 LLT_INIT */ 989#define _LLT_NO_ACTIVE 0x0 990#define _LLT_WRITE_ACCESS 0x1 991#define _LLT_READ_ACCESS 0x2 992 993#define _LLT_INIT_DATA(x) ((x) & 0xFF) 994#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 995#define _LLT_OP(x) (((x) & 0x3) << 30) 996#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 997 998/* 0x0200h ~ 0x027Fh TXDMA Configuration */ 999/* 2RQPN */ 1000#define _HPQ(x) ((x) & 0xFF) 1001#define _LPQ(x) (((x) & 0xFF) << 8) 1002#define _PUBQ(x) (((x) & 0xFF) << 16) 1003/* NOTE: in RQPN_NPQ register */ 1004#define _NPQ(x) ((x) & 0xFF) 1005 1006#define HPQ_PUBLIC_DIS BIT(24) 1007#define LPQ_PUBLIC_DIS BIT(25) 1008#define LD_RQPN BIT(31) 1009 1010/* 2TDECTRL */ 1011#define BCN_VALID BIT(16) 1012#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1013#define BCN_HEAD_MASK 0xFF00 1014 1015/* 2 TDECTL */ 1016#define BLK_DESC_NUM_SHIFT 4 1017#define BLK_DESC_NUM_MASK 0xF 1018 1019/* 2 TXDMA_OFFSET_CHK */ 1020#define DROP_DATA_EN BIT(9) 1021 1022/* 0x0280h ~ 0x028Bh RX DMA Configuration */ 1023 1024/* REG_RXDMA_CONTROL, 0x0286h */ 1025 1026/* 2 REG_RXPKT_NUM, 0x0284 */ 1027#define RXPKT_RELEASE_POLL BIT(16) 1028#define RXDMA_IDLE BIT(17) 1029#define RW_RELEASE_EN BIT(18) 1030 1031/* 0x0400h ~ 0x047Fh Protocol Configuration */ 1032/* 2 FWHW_TXQ_CTRL */ 1033#define EN_AMPDU_RTY_NEW BIT(7) 1034 1035/* 2 SPEC SIFS */ 1036#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1037#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1038 1039/* 2 RL */ 1040#define RETRY_LIMIT_SHORT_SHIFT 8 1041#define RETRY_LIMIT_LONG_SHIFT 0 1042 1043/* 0x0500h ~ 0x05FFh EDCA Configuration */ 1044 1045/* 2 EDCA setting */ 1046#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1047#define AC_PARAM_ECW_MAX_OFFSET 12 1048#define AC_PARAM_ECW_MIN_OFFSET 8 1049#define AC_PARAM_AIFS_OFFSET 0 1050 1051#define _LRL(x) ((x) & 0x3F) 1052#define _SRL(x) (((x) & 0x3F) << 8) 1053 1054/* 2 BCN_CTRL */ 1055#define EN_MBSSID BIT(1) 1056#define EN_TXBCN_RPT BIT(2) 1057#define EN_BCN_FUNCTION BIT(3) 1058#define DIS_TSF_UPDATE BIT(3) 1059 1060/* The same function but different bit field. */ 1061#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1062#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1063#define STOP_BCNQ BIT(6) 1064 1065/* 2 ACMHWCTRL */ 1066#define AcmHw_HwEn BIT(0) 1067#define AcmHw_BeqEn BIT(1) 1068#define AcmHw_ViqEn BIT(2) 1069#define AcmHw_VoqEn BIT(3) 1070#define AcmHw_BeqStatus BIT(4) 1071#define AcmHw_ViqStatus BIT(5) 1072#define AcmHw_VoqStatus BIT(6) 1073 1074/* 0x0600h ~ 0x07FFh WMAC Configuration */ 1075/* 2APSD_CTRL */ 1076#define APSDOFF BIT(6) 1077#define APSDOFF_STATUS BIT(7) 1078 1079#define RATE_BITMAP_ALL 0xFFFFF 1080 1081/* Only use CCK 1M rate for ACK */ 1082#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1083 1084/* 2 TCR */ 1085#define TSFRST BIT(0) 1086#define DIS_GCLK BIT(1) 1087#define PAD_SEL BIT(2) 1088#define PWR_ST BIT(6) 1089#define PWRBIT_OW_EN BIT(7) 1090#define ACRC BIT(8) 1091#define CFENDFORM BIT(9) 1092#define ICV BIT(10) 1093 1094/* 2 RCR */ 1095#define AAP BIT(0) 1096#define APM BIT(1) 1097#define AM BIT(2) 1098#define AB BIT(3) 1099#define ADD3 BIT(4) 1100#define APWRMGT BIT(5) 1101#define CBSSID BIT(6) 1102#define CBSSID_DATA BIT(6) 1103#define CBSSID_BCN BIT(7) 1104#define ACRC32 BIT(8) 1105#define AICV BIT(9) 1106#define ADF BIT(11) 1107#define ACF BIT(12) 1108#define AMF BIT(13) 1109#define HTC_LOC_CTRL BIT(14) 1110#define UC_DATA_EN BIT(16) 1111#define BM_DATA_EN BIT(17) 1112#define MFBEN BIT(22) 1113#define LSIGEN BIT(23) 1114#define EnMBID BIT(24) 1115#define APP_BASSN BIT(27) 1116#define APP_PHYSTS BIT(28) 1117#define APP_ICV BIT(29) 1118#define APP_MIC BIT(30) 1119#define APP_FCS BIT(31) 1120 1121/* 2 SECCFG */ 1122#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ 1123#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ 1124#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ 1125#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ 1126#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ 1127#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ 1128#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ 1129#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ 1130 1131/* RTL8188E SDIO Configuration */ 1132 1133/* I/O bus domain address mapping */ 1134#define SDIO_LOCAL_BASE 0x10250000 1135#define WLAN_IOREG_BASE 0x10260000 1136#define FIRMWARE_FIFO_BASE 0x10270000 1137#define TX_HIQ_BASE 0x10310000 1138#define TX_MIQ_BASE 0x10320000 1139#define TX_LOQ_BASE 0x10330000 1140#define RX_RX0FF_BASE 0x10340000 1141 1142/* SDIO host local register space mapping. */ 1143#define SDIO_LOCAL_MSK 0x0FFF 1144#define WLAN_IOREG_MSK 0x7FFF 1145#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ 1146#define WLAN_RX0FF_MSK 0x0003 1147 1148/* Without ref to the SDIO Device ID */ 1149#define SDIO_WITHOUT_REF_DEVICE_ID 0 1150#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ 1151#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ 1152#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ 1153#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ 1154#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ 1155#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ 1156 1157/* SDIO Tx Free Page Index */ 1158#define HI_QUEUE_IDX 0 1159#define MID_QUEUE_IDX 1 1160#define LOW_QUEUE_IDX 2 1161#define PUBLIC_QUEUE_IDX 3 1162 1163#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ 1164#define SDIO_MAX_RX_QUEUE 1 1165 1166/* SDIO Tx Control */ 1167#define SDIO_REG_TX_CTRL 0x0000 1168/* SDIO Host Interrupt Mask */ 1169#define SDIO_REG_HIMR 0x0014 1170/* SDIO Host Interrupt Service Routine */ 1171#define SDIO_REG_HISR 0x0018 1172/* HCI Current Power Mode */ 1173#define SDIO_REG_HCPWM 0x0019 1174/* RXDMA Request Length */ 1175#define SDIO_REG_RX0_REQ_LEN 0x001C 1176/* Free Tx Buffer Page */ 1177#define SDIO_REG_FREE_TXPG 0x0020 1178/* HCI Current Power Mode 1 */ 1179#define SDIO_REG_HCPWM1 0x0024 1180/* HCI Current Power Mode 2 */ 1181#define SDIO_REG_HCPWM2 0x0026 1182/* HTSF Informaion */ 1183#define SDIO_REG_HTSFR_INFO 0x0030 1184/* HCI Request Power Mode 1 */ 1185#define SDIO_REG_HRPWM1 0x0080 1186/* HCI Request Power Mode 2 */ 1187#define SDIO_REG_HRPWM2 0x0082 1188/* HCI Power Save Clock */ 1189#define SDIO_REG_HPS_CLKR 0x0084 1190/* SDIO HCI Suspend Control */ 1191#define SDIO_REG_HSUS_CTRL 0x0086 1192/* SDIO Host Extension Interrupt Mask Always */ 1193#define SDIO_REG_HIMR_ON 0x0090 1194/* SDIO Host Extension Interrupt Status Always */ 1195#define SDIO_REG_HISR_ON 0x0091 1196 1197#define SDIO_HIMR_DISABLED 0 1198 1199/* RTL8188E SDIO Host Interrupt Mask Register */ 1200#define SDIO_HIMR_RX_REQUEST_MSK BIT0 1201#define SDIO_HIMR_AVAL_MSK BIT1 1202#define SDIO_HIMR_TXERR_MSK BIT2 1203#define SDIO_HIMR_RXERR_MSK BIT3 1204#define SDIO_HIMR_TXFOVW_MSK BIT4 1205#define SDIO_HIMR_RXFOVW_MSK BIT5 1206#define SDIO_HIMR_TXBCNOK_MSK BIT6 1207#define SDIO_HIMR_TXBCNERR_MSK BIT7 1208#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 1209#define SDIO_HIMR_C2HCMD_MSK BIT17 1210#define SDIO_HIMR_CPWM1_MSK BIT18 1211#define SDIO_HIMR_CPWM2_MSK BIT19 1212#define SDIO_HIMR_HSISR_IND_MSK BIT20 1213#define SDIO_HIMR_GTINT3_IND_MSK BIT21 1214#define SDIO_HIMR_GTINT4_IND_MSK BIT22 1215#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 1216#define SDIO_HIMR_OCPINT_MSK BIT24 1217#define SDIO_HIMR_ATIMEND_MSK BIT25 1218#define SDIO_HIMR_ATIMEND_E_MSK BIT26 1219#define SDIO_HIMR_CTWEND_MSK BIT27 1220 1221/* RTL8188E SDIO Specific */ 1222#define SDIO_HIMR_MCU_ERR_MSK BIT28 1223#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 1224 1225/* SDIO Host Interrupt Service Routine */ 1226#define SDIO_HISR_RX_REQUEST BIT0 1227#define SDIO_HISR_AVAL BIT1 1228#define SDIO_HISR_TXERR BIT2 1229#define SDIO_HISR_RXERR BIT3 1230#define SDIO_HISR_TXFOVW BIT4 1231#define SDIO_HISR_RXFOVW BIT5 1232#define SDIO_HISR_TXBCNOK BIT6 1233#define SDIO_HISR_TXBCNERR BIT7 1234#define SDIO_HISR_BCNERLY_INT BIT16 1235#define SDIO_HISR_C2HCMD BIT17 1236#define SDIO_HISR_CPWM1 BIT18 1237#define SDIO_HISR_CPWM2 BIT19 1238#define SDIO_HISR_HSISR_IND BIT20 1239#define SDIO_HISR_GTINT3_IND BIT21 1240#define SDIO_HISR_GTINT4_IND BIT22 1241#define SDIO_HISR_PSTIME BIT23 1242#define SDIO_HISR_OCPINT BIT24 1243#define SDIO_HISR_ATIMEND BIT25 1244#define SDIO_HISR_ATIMEND_E BIT26 1245#define SDIO_HISR_CTWEND BIT27 1246 1247/* RTL8188E SDIO Specific */ 1248#define SDIO_HISR_MCU_ERR BIT28 1249#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 1250 1251#define MASK_SDIO_HISR_CLEAR \ 1252 (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ 1253 SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\ 1254 SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\ 1255 SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\ 1256 SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) 1257 1258/* SDIO HCI Suspend Control Register */ 1259#define HCI_RESUME_PWR_RDY BIT1 1260#define HCI_SUS_CTRL BIT0 1261 1262/* SDIO Tx FIFO related */ 1263/* The number of Tx FIFO free page */ 1264#define SDIO_TX_FREE_PG_QUEUE 4 1265#define SDIO_TX_FIFO_PAGE_SZ 128 1266 1267/* 0xFE00h ~ 0xFE55h USB Configuration */ 1268 1269/* 2 USB Information (0xFE17) */ 1270#define USB_IS_HIGH_SPEED 0 1271#define USB_IS_FULL_SPEED 1 1272#define USB_SPEED_MASK BIT(5) 1273 1274#define USB_NORMAL_SIE_EP_MASK 0xF 1275#define USB_NORMAL_SIE_EP_SHIFT 4 1276 1277/* 2 Special Option */ 1278#define USB_AGG_EN BIT(3) 1279 1280/* 0; Use interrupt endpoint to upload interrupt pkt */ 1281/* 1; Use bulk endpoint to upload interrupt pkt, */ 1282#define INT_BULK_SEL BIT(4) 1283 1284/* 2REG_C2HEVT_CLEAR */ 1285/* Set by driver and notify FW that the driver has read 1286 * the C2H command message */ 1287#define C2H_EVT_HOST_CLOSE 0x00 1288/* Set by FW indicating that FW had set the C2H command 1289 * message and it's not yet read by driver. */ 1290#define C2H_EVT_FW_CLOSE 0xFF 1291 1292/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 1293/* Enable GPIO[9] as WiFi HW PDn source */ 1294#define WL_HWPDN_EN BIT0 1295/* WiFi HW PDn polarity control */ 1296#define WL_HWPDN_SL BIT1 1297/* WiFi function enable */ 1298#define WL_FUNC_EN BIT2 1299/* Enable GPIO[9] as WiFi RF HW PDn source */ 1300#define WL_HWROF_EN BIT3 1301/* Enable GPIO[11] as BT HW PDn source */ 1302#define BT_HWPDN_EN BIT16 1303/* BT HW PDn polarity control */ 1304#define BT_HWPDN_SL BIT17 1305/* BT function enable */ 1306#define BT_FUNC_EN BIT18 1307/* Enable GPIO[11] as BT/GPS RF HW PDn source */ 1308#define BT_HWROF_EN BIT19 1309/* Enable GPIO[10] as GPS HW PDn source */ 1310#define GPS_HWPDN_EN BIT20 1311/* GPS HW PDn polarity control */ 1312#define GPS_HWPDN_SL BIT21 1313/* GPS function enable */ 1314#define GPS_FUNC_EN BIT22 1315 1316/* 3 REG_LIFECTRL_CTRL */ 1317#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 1318#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 1319#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 1320#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 1321 1322#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ 1323 1324/* General definitions */ 1325#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ 1326 1327#define POLLING_LLT_THRESHOLD 20 1328#define POLLING_READY_TIMEOUT_COUNT 1000 1329/* GPIO BIT */ 1330#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 1331 1332/* 8192C EEPROM/EFUSE share register definition. */ 1333 1334/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ 1335#define EEPROM_TX_PWR_INX_88E 0x10 1336 1337#define EEPROM_ChannelPlan_88E 0xB8 1338#define EEPROM_XTAL_88E 0xB9 1339#define EEPROM_THERMAL_METER_88E 0xBA 1340#define EEPROM_IQK_LCK_88E 0xBB 1341 1342#define EEPROM_RF_BOARD_OPTION_88E 0xC1 1343#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 1344#define EEPROM_RF_BT_SETTING_88E 0xC3 1345#define EEPROM_VERSION_88E 0xC4 1346#define EEPROM_CUSTOMERID_88E 0xC5 1347#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 1348 1349/* RTL88EE */ 1350#define EEPROM_MAC_ADDR_88EE 0xD0 1351#define EEPROM_VID_88EE 0xD6 1352#define EEPROM_DID_88EE 0xD8 1353#define EEPROM_SVID_88EE 0xDA 1354#define EEPROM_SMID_88EE 0xDC 1355 1356/* RTL88EU */ 1357#define EEPROM_MAC_ADDR_88EU 0xD7 1358#define EEPROM_VID_88EU 0xD0 1359#define EEPROM_PID_88EU 0xD2 1360#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 1361 1362/* RTL88ES */ 1363#define EEPROM_MAC_ADDR_88ES 0x11A 1364 1365/* EEPROM/Efuse Value Type */ 1366#define EETYPE_TX_PWR 0x0 1367 1368/* Default Value for EEPROM or EFUSE!!! */ 1369#define EEPROM_Default_TSSI 0x0 1370#define EEPROM_Default_TxPowerDiff 0x0 1371#define EEPROM_Default_CrystalCap 0x5 1372/* Default: 2X2, RTL8192CE(QFPN68) */ 1373#define EEPROM_Default_BoardType 0x02 1374#define EEPROM_Default_TxPower 0x1010 1375#define EEPROM_Default_HT2T_TxPwr 0x10 1376 1377#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 1378#define EEPROM_Default_ThermalMeter 0x12 1379 1380#define EEPROM_Default_AntTxPowerDiff 0x0 1381#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 1382#define EEPROM_Default_TxPowerLevel 0x2A 1383 1384#define EEPROM_Default_HT40_2SDiff 0x0 1385/* HT20<->40 default Tx Power Index Difference */ 1386#define EEPROM_Default_HT20_Diff 2 1387#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 1388#define EEPROM_Default_HT40_PwrMaxOffset 0 1389#define EEPROM_Default_HT20_PwrMaxOffset 0 1390 1391#define EEPROM_Default_CrystalCap_88E 0x20 1392#define EEPROM_Default_ThermalMeter_88E 0x18 1393 1394/* New EFUSE deafult value */ 1395#define EEPROM_DEFAULT_24G_INDEX 0x2D 1396#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 1397#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 1398 1399#define EEPROM_DEFAULT_5G_INDEX 0X2A 1400#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 1401#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 1402 1403#define EEPROM_DEFAULT_DIFF 0XFE 1404#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F 1405#define EEPROM_DEFAULT_BOARD_OPTION 0x00 1406#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 1407#define EEPROM_DEFAULT_BT_OPTION 0x10 1408 1409/* For debug */ 1410#define EEPROM_Default_PID 0x1234 1411#define EEPROM_Default_VID 0x5678 1412#define EEPROM_Default_CustomerID 0xAB 1413#define EEPROM_Default_CustomerID_8188E 0x00 1414#define EEPROM_Default_SubCustomerID 0xCD 1415#define EEPROM_Default_Version 0 1416 1417#define EEPROM_CHANNEL_PLAN_FCC 0x0 1418#define EEPROM_CHANNEL_PLAN_IC 0x1 1419#define EEPROM_CHANNEL_PLAN_ETSI 0x2 1420#define EEPROM_CHANNEL_PLAN_SPA 0x3 1421#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 1422#define EEPROM_CHANNEL_PLAN_MKK 0x5 1423#define EEPROM_CHANNEL_PLAN_MKK1 0x6 1424#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 1425#define EEPROM_CHANNEL_PLAN_TELEC 0x8 1426#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 1427#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 1428#define EEPROM_CHANNEL_PLAN_NCC 0xB 1429#define EEPROM_USB_OPTIONAL1 0xE 1430#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 1431 1432#define EEPROM_CID_DEFAULT 0x0 1433#define EEPROM_CID_TOSHIBA 0x4 1434#define EEPROM_CID_CCX 0x10 /* CCX test. */ 1435#define EEPROM_CID_QMI 0x0D 1436#define EEPROM_CID_WHQL 0xFE 1437#define RTL_EEPROM_ID 0x8129 1438 1439#endif /* __RTL8188E_SPEC_H__ */ 1440