[go: nahoru, domu]

Searched refs:DP (Results 1 - 21 of 21) sorted by last modified time

/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x.h89 #define DP(__mask, fmt, ...) \ macro
H A Dbnx2x_cmn.c210 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
294 DP(NETIF_MSG_TX_DONE,
369 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
400 DP(NETIF_MSG_RX_STATUS,
487 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
793 DP(NETIF_MSG_RX_STATUS,
807 DP(NETIF_MSG_RX_STATUS,
892 DP(NETIF_MSG_RX_STATUS,
928 DP(NETIF_MSG_RX_STATUS,
959 DP(NETIF_MSG_RX_STATU
[all...]
H A Dbnx2x_cmn.h55 DP(NETIF_MSG_HW, \
65 DP(NETIF_MSG_HW, \
525 DP(NETIF_MSG_RX_STATUS,
643 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
708 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
1113 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1231 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1302 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
H A Dbnx2x_dcb.c129 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error);
132 DP(NETIF_MSG_LINK,
135 DP(NETIF_MSG_LINK,
139 DP(NETIF_MSG_LINK,
144 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n",
146 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n",
148 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n",
151 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n",
153 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n",
155 DP(BNX2X_MSG_DC
[all...]
H A Dbnx2x_ethtool.c244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
328 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
349 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
373 DP(BNX2X_MSG_ETHTOOL,
382 DP(BNX2X_MSG_ETHTOOL,
403 DP(BNX2X_MSG_ETHTOOL,
422 DP(BNX2X_MSG_ETHTOOL,
437 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
447 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
456 DP(BNX2X_MSG_ETHTOO
[all...]
H A Dbnx2x_init.h713 DP(NETIF_MSG_HW, "Setting parity mask "
746 DP(NETIF_MSG_HW,
756 DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
H A Dbnx2x_init_ops.h479 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
484 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
489 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
492 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
H A Dbnx2x_link.c261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
394 DP(NETIF_MSG_LIN
[all...]
H A Dbnx2x_main.c393 DP(msglvl, "DMAE: opcode 0x%08x\n"
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
411 DP(msglvl, "DMAE: opcode 0x%08x\n"
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
429 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
858 DP(NETIF_MSG_IFDOWN,
878 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
911 DP(BNX2X_MSG_STAT
[all...]
H A Dbnx2x_sp.c73 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
80 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n");
127 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc);
188 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
249 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n");
290 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state);
296 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt);
399 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n");
403 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n");
422 DP(BNX2X_MSG_S
[all...]
H A Dbnx2x_sriov.c98 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
104 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n");
131 DP(BNX2X_MSG_IOV,
149 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
245 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
254 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n");
287 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
296 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n");
348 DP(BNX2X_MSG_S
[all...]
H A Dbnx2x_stats.c86 DP(BNX2X_MSG_STATS, "dumping stats:\n"
102 DP(BNX2X_MSG_STATS,
139 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n",
857 DP(BNX2X_MSG_STATS,
916 DP(BNX2X_MSG_STATS,
923 DP(BNX2X_MSG_STATS,
930 DP(BNX2X_MSG_STATS,
937 DP(BNX2X_MSG_STATS,
987 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n",
991 DP(BNX2X_MSG_STAT
[all...]
H A Dbnx2x_vfpf.c43 DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n",
60 DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n",
85 DP(BNX2X_MSG_IOV, "TLV list does not contain %d TLV\n", req_tlv);
98 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i,
117 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i,
156 DP(BNX2X_MSG_IOV, "detecting channel down. Aborting message\n");
188 DP(BNX2X_MSG_SP, "Got a response from PF\n");
214 DP(BNX2X_MSG_IOV, "valid ME register value: 0x%08x\n", me_reg);
267 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
287 DP(BNX2X_MSG_S
[all...]
/drivers/net/ethernet/sun/
H A Dsunbmac.c58 #define DP(x) printk x macro
60 #define DP(x) macro
/drivers/net/wan/
H A Dsbni.h10 #define DP( A ) A macro
12 #define DP( A ) macro
/drivers/pinctrl/
H A Dpinctrl-tegra124.c2003 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
/drivers/gpu/drm/i915/
H A Dintel_ddi.c37 * them for both DP and FDI transports, allowing those ports to
155 * values in advance. The buffer values are different for FDI and DP modes,
157 * in either FDI or DP modes only, as HDMI connections will work with both
237 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
399 intel_dp->DP = intel_dig_port->saved_port_bits |
401 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1390 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1391 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1592 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatibl
[all...]
H A Dintel_dp.c89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
758 /* Must try at least 3 times according to DP spec */
1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1190 * There are four kinds of DP register
2383 _intel_dp_set_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) argument
3336 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) argument
3370 intel_dp_set_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) argument
3403 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) argument
3412 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, const uint8_t link_status[DP_LINK_STATUS_SIZE]) argument
3472 uint32_t DP = intel_dp->DP; local
3559 uint32_t DP = intel_dp->DP; local
3650 uint32_t DP = intel_dp->DP; local
[all...]
H A Dintel_drv.h162 * encoder are flushed (for example for DP AUX transactions) and
291 /* DP has a bunch of special case unfortunately, so mark the pipe
344 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
551 uint32_t DP; member in struct:intel_dp
/drivers/block/
H A Dfloppy.c303 #define DP (&drive_params[current_drive]) macro
627 if (DP->flags & DEBUGT)
823 if (DP->select_delay)
942 if (DP->select_delay)
1001 debug_dcl(DP->flags, "calling disk change from watchdog\n");
1302 srt = 16 - DIV_ROUND_UP(DP->srt * scale_dtr / 1000, NOMINAL_DTR);
1309 hlt = DIV_ROUND_UP(DP->hlt * scale_dtr / 2, NOMINAL_DTR);
1315 hut = DIV_ROUND_UP(DP->hut * scale_dtr / 16, NOMINAL_DTR);
1422 if (DP->flags & FTD_MSG)
1425 } else if (*errors >= DP
[all...]
/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c64 uint32_t DP; member in struct:cdv_intel_dp
113 * @intel_dp: DP struct
115 * If a CPU or PCH DP output is attached to an eDP panel, this function
407 /* Must try at least 3 times according to DP spec */
853 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
854 intel_dp->DP |= intel_dp->color_range;
857 intel_dp->DP |= DP_SYNC_HS_HIGH;
859 intel_dp->DP |= DP_SYNC_VS_HIGH;
861 intel_dp->DP |= DP_LINK_TRAIN_OFF;
865 intel_dp->DP |
1313 uint32_t DP = intel_dp->DP; local
1405 uint32_t DP = intel_dp->DP; local
1488 uint32_t DP = intel_dp->DP; local
[all...]

Completed in 1946 milliseconds