Release v1.1.541

This is NOT a long-term support version!!!

For some reason, the package released by Github is wrong. Please see the correct package HERE

Correct commit id: 8ee3fb8

This is the last release before the major organization #747 !!!

🔥 After 541 commits since last release, OpenFPGA has experienced several major updates.

• Now support pin constraint file for I/O constraints, including the customization on pin table file.
• Support I/O at any location of FPGA fabrics, and I/O indexing now follows a natural way (clockwise) throughout the fabric
• Include Configuration Region Statistics in Bitstream Distribution Report
• Alleviate the huge memory consumption in support large FPGA devices using memory bank protocols
• Now .act file is no longer required in openfpga_flow/task when power analysis option is off
• Fixed a critical bug in uniquifying routing blocks. More unique modules can be detected, reducing physical design challenges
• Enhanced GSB writer with more flexibility

What's Changed

• [CI] Update patch updater due to release v1.1.0 by @tangxifan in #547
• Pulling refs/heads/master into master by @github-actions in #548
• Bump yosys-plugins from 0fa6d61 to 770b917 by @dependabot in #546
• Bump yosys-plugins from 770b917 to 57a3b87 by @dependabot in #550
• Pulling refs/heads/master into master by @github-actions in #552
• Now preconfigured Verilog wrapper can handle config_enable signals correctly by @tangxifan in #556
• Fixed a bug in config_enable support for preconfigured testbenches by @tangxifan in #558
• Pulling refs/heads/master into master by @github-actions in #559
• Bump yosys-plugins from 57a3b87 to 61db11f by @dependabot in #557
• Merge fixes for post layout netlist/sdf generation for blackbox modules by @tpagarani in #554
• Bump yosys-plugins from 61db11f to e40caae by @dependabot in #560
• Pulling refs/heads/master into master by @github-actions in #561
• Bump yosys-plugins from e40caae to 69a541c by @dependabot in #563
• Pulling refs/heads/master into master by @github-actions in #566
• Bump yosys-plugins from 69a541c to 6a80e6e by @dependabot in #567
• Bump yosys-plugins from 6a80e6e to b02792d by @dependabot in #570
• Post layout netlist by @tpagarani in #564
• Bump yosys-plugins from b02792d to ecfc0af by @dependabot in #572
• Pulling refs/heads/master into master by @github-actions in #571
• Pulling refs/heads/master into master by @github-actions in #575
• Bump yosys-plugins from ecfc0af to 6d51ff0 by @dependabot in #579
• Pulling refs/heads/master into master by @github-actions in #581
• Post layout by @tpagarani in #580
• Bump yosys-plugins from 6d51ff0 to 8dbda8d by @dependabot in #582
• Pulling refs/heads/master into master by @github-actions in #584
• Bump yosys-plugins from 8dbda8d to af72a89 by @dependabot in #585
• Pulling refs/heads/master into master by @github-actions in #586
• Bump yosys-plugins from af72a89 to c87f7b0 by @dependabot in #587
• Now port/wire names uses "__" to avoid collision FPGA global ports by @tangxifan in #588
• Pulling refs/heads/master into master by @github-actions in #589
• fix openfpga_digest functions to work on WIN32(MinGW-w64-g++) by @coolbreeze413 in #592
• Pulling refs/heads/master into master by @github-actions in #593
• Bump yosys-plugins from c87f7b0 to d849fd4 by @dependabot in #591
• Now fabric generator supports a global port from partial bits of physical tile ports by @tangxifan in #594
• Pulling refs/heads/master into master by @github-actions in #595
• Bump yosys-plugins from d849fd4 to a2a80a1 by @dependabot in #596
• Pulling refs/heads/master into master by @github-actions in #598
• Fix a small typo to trigger the CI flow. by @taoli4rs in #600
• Pulling refs/heads/master into master by @github-actions in #602
• Bump yosys-plugins from a2a80a1 to 46810a5 by @dependabot in #599
• Bump yosys-plugins from 46810a5 to 40a1431 by @dependabot in #604
• Pulling refs/heads/master into master by @github-actions in #605
• Include Configuration Region Statistics in Bitstream Distribution Report File by @tangxifan in #608
• Pulling refs/heads/master into master by @github-actions in #610
• Bump yosys-plugins from 40a1431 to d64a754 by @dependabot in #612
• Pulling refs/heads/master into master by @github-actions in #613
• Bump yosys-plugins from d64a754 to 1256b0a by @dependabot in #617
• [Engine] Now GSB output file contains segments name and pin name in SB module by @tangxifan in #618
• Pulling refs/heads/master into master by @github-actions in #619
• [Test] Add a new test case to validate the fix_pins option by @tangxifan in #620
• Bump yosys-plugins from 1256b0a to 8ae5bf7 by @dependabot in #622
• Bump yosys-plugins from 8ae5bf7 to ff70a90 by @dependabot in #623
• Pulling refs/heads/master into master by @github-actions in #621
• Bump yosys-plugins from ff70a90 to d09ffc1 by @dependabot in #624
• Pulling refs/heads/master into master by @github-actions in #625
• Bump yosys-plugins from d09ffc1 to c19f808 by @dependabot in #630
• Pulling refs/heads/master into master by @github-actions in #633
• Added Binder interface by @ganeshgore in #632
• Added create-task shortcut in openfpga shell scripts by @ganeshgore in #635
• Pulling refs/heads/master into master by @github-actions in #638
• Bump yosys-plugins from c19f808 to f79f203 by @dependabot in #636
• Added option to copy example projects by @ganeshgore in #637
• Skipped large fabric_independent_bitstream.xml writing in CI by @ganeshgore in #642
• Pulling refs/heads/master into master by @github-actions in #644
• Bump yosys-plugins from f79f203 to cfd794b by @dependabot in #641
• Minor enhancements in openfpga.sh script by @ganeshgore in #643
• Pulling refs/heads/master into master by @github-actions in #646
• Support Negative Edge Flip-flop by @tangxifan in #647
• Pulling refs/heads/master into master by @github-actions in #648
• Bump yosys-plugins from cfd794b to 00590be by @dependabot in #649
• Pulling refs/heads/master into master by @github-actions in #650
• Updated documentation on how to execute with docker by @ganeshgore in #651
• Bump yosys-plugins from 00590be to 2fa356d by @dependabot in #652
• Pulling refs/heads/master into master by @github-actions in #653
• Added user to the docker image by @ganeshgore in #654
• Bump yosys-plugins from 2fa356d to aadd173 by @dependabot in #655
• Pulling refs/heads/master into master by @github-actions in https://gith...

Release v1.1.0

This is NOT a long-term support version!!!

🔥 After ~4k commits since last release, OpenFPGA has experienced several major updates.

• Bring VPR8 as a core engine
• Fully rewrite the codebase to follow a modern user interface, especially openfpga has a shell-like interface
• All the OpenFPGA commands now have documentation
• All the OpenFPGA file formats now have documentation
• Deploy regression tests for all the features
• Built a library of FPGA architecture files to showcase OpenFPGA features
• Reworked documentation for each tools, FPGA-Verilog/FPGA-Bitstream/FPGA-SDC

⌚ Sorry for not releasing it regularly. We are trying to it every quarter from now on.

What's Changed

• Update README from Tim by @tangxifan in #30
• Update master with latest development version by @tangxifan in #31
• Misc Updates on regression tests and clean-up flow run by @tangxifan in #32
• Remove legacy codes in FPGA-Verilog by @tangxifan in #33
• Dev by @tangxifan in #34
• Fix tutorial configuration file by @skulis in #36
• Fix docker file (do not run make multi threaded) by @skulis in #35
• architecture fix for tutorial purpose by @AurelienUoU in #38
• Remove redundant net source addition in CBs and SBs by @tangxifan in #39
• Dev by @AurelienUoU in #40
• bug fixed in SDC for CBs and SBs: remove useless module names by @AurelienUoU in #41
• Dev by @AurelienUoU in #43
• Fix GUI support with cmake 3.16 by @srtemp in #44
• Update dev to be even with master's documentation update by @LNIS-Projects in #45
• Ganesh dev by @tangxifan in #51
• Porting Dev branch to master by @tangxifan in #53
• Dev by @tangxifan in #56
• Bug fix in the line parser when dealing with empty inputs for Centos 8 which is strict on this by @tangxifan in #57
• Memory, runtime and netlist size optimization by @tangxifan in #58
• Runtime and memory improvement on bitstream database by @tangxifan in #59
• Bug fix in reserve configuration blocks for bitstream manager to optimize memory usage by @tangxifan in #60
• Remove obsolete codes and restructure compilation options by @tangxifan in #61
• Simplify fabric key where users just need to provide alias; start porting FPGA-SPICE by @tangxifan in #62
• Improve runtime of fabric key loading; Documentation update for different file format of fabric keys by @tangxifan in #63
• using a unified string to replace multi net names to save memory of b… by @tangxifan in #64
• Updated Dockerfile for Ubuntu 18.04 by @samycharas in #66
• hotfix on treating the dangling ports in pb_graph for analysis SDC ge… by @tangxifan in #67
• Remove obsolete documentation and add technology binding by @tangxifan in #68
• Bug fix in yosys-vpr flow using OpenFPGA shell; by @tangxifan in #69
• Misc Updates by @tangxifan in #70
• Fabric Bitstream file writer by @tangxifan in #72
• Misc Updates by @tangxifan in #73
• Update FPGA-Bitstream regression tests to track runtime of large devices and practical benchmarks by @tangxifan in #74
• Misc Updates by @tangxifan in #77
• [Architecture Languange] Patch the default circuit model definition by @tangxifan in #79
• Update documentation and debugging aid by @tangxifan in #81
• Enriched regression test for flexible routing multiplexer designs by @tangxifan in #83
• Add compiler compatibility tests to Travis CI by @tangxifan in #84
• Support on flexible local routing architecture by @tangxifan in #85
• Misc Updates by @tangxifan in #86
• Transplant FPGA-SPICE to OpenFPGA by @tangxifan in #87
• Update issue templates by @tangxifan in #88
• Regression test & architecture updates by @tangxifan in #89
• Architecture and regression test update by @tangxifan in #90
• [Regression Tests] Remove deadlink by @tangxifan in #91
• Smart Configuration Support and Verilog Netlist Refactoring by @tangxifan in #92
• [Architecture] Reorganize the cell netlists and update architecture f… by @tangxifan in #93
• [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name by @tangxifan in #94
• [OpenFPGA Tool] Add self-testing Verilog codes for configuration done… by @tangxifan in #96
• Deprecated Code Removal by @tangxifan in #97
• Support of multiple regions for configuration chain by @tangxifan in #98
• Edits to enable basic run_fpga_flow.py by @lukefahr in #100
• Documentation Update to Include Technical Features by @tangxifan in #101
• Fixed blif formatting bug by @lukefahr in #102
• FLOW: fixed display flag by @lukefahr in #104
• Docs: Updated note to enable VPR's GUI by @lukefahr in #103
• Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates by @tangxifan in #105
• Documentation update by @tangxifan in #106
• Enable Customized Fabric Netlist Location in Verilog Testbench Generation by @tangxifan in #107
• Add test cases for constant inputs of routing multiplexers by @tangxifan in #108
• Frontpage README Update with more links to documentation pages by @tangxifan in #109
• Bug fix in tutorial due to renamed regression tests by @tangxifan in #111
• Multi-region Memory Bank Configuration Protocol Support by @tangxifan in #112
• Multi-region support on Frame-based Configuration Protocol by @tangxifan in #113
• Support I/O interfaces for Embedded FPGAs by @tangxifan in #114
• Refactor the codes for walking through io blocks by @tangxifan in #115
• Extended I/O Support for SoC I/O interface by @tangxifan in #116
• Update README.md by @olofk in #117
• Remove the restrictions on requiring two outputs for configurable memory circuits by @tangxifan in #118
• Support Global Port Definition for Physical Tile Ports by @tangxifan in #122
• Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation by @tangxifan in #123
• Add readthedoc Setting File by @tangxifan in #124
• Multiple Bug Fixes by @tangxifan in #126
• Bug fix for global clock port using physical tile pins by @tangxifan in #127
• Generate Signal Initialization in Verilog Testbenches rather than HDL netlists by @tangxifan in #129
• Fix for rr graph loading by VPR by @mkurc-ant in #130
• Use GitHub Actions as CI by @tangxifan in #133
• Improvements on Signal Initialization in Testbench Generation by @tangxifan in #131
• Support on Native Fracturable LUT Design by @tangxifan in #135
• Update README with latest Github Action badge by @tangxifan in #139
• Add a Test Case to CI which defines global reset port through tile port in VPR architecture by @tangxifan in #141
• Critical Bug ...

This release is for the following papers:

• X. Tang, E. Giacomin, A. Alacchi, B. Chauviere and P.-E. Gaillardon, "OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs," 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 367-374.
• X. Tang, E. Giacomin, A. Alacchi and P.-E. Gaillardon, "A Study on Switch Block Patterns for
  Tileable FPGA Routing Architectures", International Conference on Field-Programmable Technology (FPT), Tianjin, China, 2019, pp. 1-4.

What is new:

• Full support on Verilog generation and bitstream generation for multi-mode CLB architectures
• Experimental support for multi-mode heterogeneous blocks
• Experimental support for tileable routing architecture generation
• Upgraded Verilog testbenches which include auto-check flags to ease the verification
• Validated over MCNC big20, EPFL benchmarks, and picoRV32 (https://github.com/cliffordwolf/picorv32)
• Tested over opensource iVerilog simulator and Mentor ModelSim

This release is for the TVLSI'19 paper:
X. Tang, E. Giacomin, G. D. Micheli and P. Gaillardon, "FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 637-650, March 2019.

What is new:

1. Functional SPICE generator (FPGA-SPICE) for homogeneous single-mode FPGAs. Users are able to perform full-fabric, grid-level and component-level simulations (see details in documentation and paper).
2. Functional Verilog generator (FPGA-Verilog) for homogeneous single-mode FPGAs, which generates tech-mapped Verilog netlists and testbenches. User are able to perform functionality verification and launch back-end flow. Our verification has covered MCNC big20 and EPFL benchmarks.
3. Functional Bitstream generator (FPGA-Bitstream) for homogeneous single-mode FPGAs.

How to cite:
@Article{8576622,
author={X. {Tang} and E. {Giacomin} and G. D. {Micheli} and P. {Gaillardon}},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title={FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs},
year={2019},
volume={27},
number={3},
pages={637-650},
doi={10.1109/TVLSI.2018.2883923},
ISSN={1063-8210},
month={March},}

This release is for the ICCD'15 paper:
X. Tang, P. Gaillardon and G. De Micheli, "FPGA-SPICE: A simulation-based power estimation framework for FPGAs," 2015 33rd IEEE International Conference on Computer Design (ICCD), New York, NY, 2015, pp. 696-703.

How to cite:
@INPROCEEDINGS{7357183,
author={X. {Tang} and P. {Gaillardon} and G. {De Micheli}},
booktitle={2015 33rd IEEE International Conference on Computer Design (ICCD)},
title={FPGA-SPICE: A simulation-based power estimation framework for FPGAs},
year={2015},
volume={},
number={},
pages={696-703},
doi={10.1109/ICCD.2015.7357183},
ISSN={},
month={Oct},}