JPH0437029A - Wiring forming method of semiconductor device - Google Patents

Abstract

PURPOSE:To selectively deposite metal material on an irradiation part and form a fine wiring pattern, by selectively projecting a high energy beam on a desired portion of a substrate having an insulating film. CONSTITUTION:A semiconductor substratum 104, in which a lower layer Al wiring, an insulating layer covering it, and a through hole for connecting an upper layer Al and the lower layer Al are formed and which is to be irradiated with a beam, is arranged in a chamber 102 as an image drawing chamber. An electron beam which is generated in a convergent electron beam source 101a, and subjected to direction control by a polarizing lens is projected on the semiconductor substratum 104 through an aperture part 101b. After a wiring pattern is written with the electron beam, the semiconductor substratum is taken out from the chamber 102. Al is deposited only on the region 123 irradiated with the electron beam, and at the same time, Al is deposited in a through hole 124. After that, the ohmic contact between the upper layer Al and the lower layer Al is improved by heat treatment, and a sufficiently low contact resistance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the wiring of semiconductor devices used to form fine wiring patterns of semiconductor devices such as memory photoelectric conversion devices and signal processing devices installed in various electronic devices. This relates to a forming method.

(Prior Art) Conventionally, as shown in FIGS. 11(A) to 11(C), the wiring pattern of an integrated circuit is formed by depositing a conductive material on the entire surface of an insulating film and then patterning a photoresist. ,
The desired wiring shape was obtained by removing unnecessary portions by etching using a patterned resist as a mask.

In FIG. 11(A), 130 is a semiconductor active layer;
1 is the lower layer Al. 132 is an insulating layer (Si02 or 5i3N
4), 133 is upper layer AA, 134 is antireflection film, 135
136 indicates a resist, and 136 indicates a concave portion of the resist directly above the through hole.

To achieve this structure, after forming the wiring pattern of the lower Al layer 131, depositing an insulating film 132 on the entire surface, and then opening a through hole. Thereafter, An or Au2-3t or the like is deposited to a thickness of about 1 .mu.m over the entire surface at a substrate temperature of 250.degree. C., for example, by magnetron sputtering. Further, for patterning, 2,000 layers of polyimide silane as an antireflection film 134 during exposure and 1 μm of regular resist 135 are applied. During the overexposure period after the resist has been exposed to the bottom, polyimide silane absorbs light energy that would not be absorbed by the resist alone, and also decomposes itself. This prevents excess light from hitting areas that are not originally desired to be exposed and causing the resist in those areas to decompose. This improves the accuracy of buttering. Excimer light source (ArF line, λ-186
The resist and reflective film are removed by exposing the wiring pattern using an exposure machine such as an exposure machine having a lens with an aperture ratio NA of 0.4[deg.] nm). This situation is shown in Figure 11 (B
). Thereafter, the Au exposed using the RIE method is removed by anisotropic etching, and the remaining resist and antireflection film are removed to obtain a desired wiring pattern (FIG. 11(C)).

[Problem that the invention is trying to solve]

However, these conventional wiring forming methods have the following technical problems to be solved.

(1) Since the wiring material generally has a high reflectance, the light reflected and scattered on the surface of the wiring + J material in the exposed area goes around to areas that should not be exposed and exposes the resist in those areas. I had left it behind. Therefore, it has been difficult to pattern the resist faithfully to the mask pattern. For this reason, an antireflection film is required directly above the wiring material, making the resist process complicated.

(2) When the unevenness of the base of the wiring material is larger than the depth of focus of the exposure machine, the resist is not sufficiently exposed, making it difficult to perform faithful resist patterning.

Below, regarding the point (2) above, Figure 12 (A) and 12
This will be explained using Figure (B).

In FIG. 12(A), 140 is the lower layer A1 wiring, 1
41 is an interlayer insulating layer, 142a is an upper layer of Au2 deposited on the entire surface, 143 is a resist, 144 is an antireflection film, 14
Reference numeral 5 indicates a light-transmitting portion of the exposure mask, 146a and 146b both light-opaque portions of the exposure mask, and 147 light condensed by a lens. 142b in FIG. 12(B) is the upper layer Aj2 that has been properly patterned. 142c is the upper layer AI that has not been properly buttered! , is.

FIG. 12(A) shows the state of exposure when there are severe irregularities on the surface of sea urchins due to steps in the base. Assume that the level difference between the bottoms of the resist to be etched is D, and the exposure is focused on the resist directly below the pattern 146a. At this time, if D≧λ/NA2 (λ: exposure wavelength, NA: numerical aperture of the lens), the light to be exposed will not focus well on the resist directly below 146b. In the above equation, the value on the right side is a constant determined by the exposure machine called depth of focus. For example, a typical value of λ/NA2 is 12 μm.
If D≧1.2 μm, the resist and anti-reflection film immediately below 146b are not etched according to the pattern of 146b, and the resist remains unexposed as shown in FIG. 12(A). This residue is caused by the light not being focused, so setting a longer exposure time will not improve the image. After the exposure step shown in FIG. 12(A), A
u2. When the wiring is etched, as shown in FIG. 12(B), a portion 142C of the resist is not exposed according to the pattern.
This causes sagging in Afl such as Lil 142 d. Therefore, a short circuit with the adjacent Afl wiring is likely to occur.

On the other hand, in the latest LSI process, although the size is reduced in the horizontal direction, the size is not reduced in the vertical direction, and a step of 1 μm or more is often created on the surface during the final wiring process. Even worse, if an attempt is made to reduce the exposure wavelength λ and increase the numerical aperture NA in order to cope with miniaturization, the depth of focus will become smaller and smaller.

As can be seen from the above explanation, the method of forming fine wiring patterns on highly uneven steps cannot sufficiently respond to improvements in the resolution of devices.

(Means for Solving the Problems (and Effects)) The wiring forming method for a semiconductor device according to the present invention provides a method for forming wiring for a semiconductor device having an insulating film on an insulating film, in which a portion of the wiring on the insulating crotch is to be formed. The method is characterized in that it includes the steps of selectively irradiating a high-energy beam to perform a deposition process to deposit a conductive metal material, and selectively depositing the conductive metal material on the irradiated portion.

[Function] According to the present invention, by selectively irradiating desired locations on a substrate having an insulating film with a high-energy beam such as alpha rays, beta rays, gamma rays, ion beams, or electron beams, By performing a deposition process on the insulating film that has been irradiated with a high-energy beam, and selectively depositing a metal substance on the irradiated area, there is no need for a resist process, and even on highly uneven substrates, fine particles can be deposited. It becomes possible to form a wiring pattern.

〔Example〕

<Embodiment> The present invention selectively applies a high-energy beam onto an insulating layer and through-holes as shown in FIG. 2 using a high-energy beam irradiation means such as an electron beam exposure device as shown in FIG. After the irradiation, high-energy beam irradiation is performed using a selective vapor deposition method to selectively deposit a conductive metal material only on the lid portion, thereby providing a method for forming wiring without a resist process.

A deposition method suitable for this formation method is a CVD method using alkyl aluminum bitite and hydrogen, which will be described later.

In this method, high-quality Al is produced by reaction with the electron-donating surface.
2 or AI-based metals can be deposited. This method shows very good selectivity for depositing conductive metallic substances on electron-donating surfaces. Therefore, using this method, after selectively filling a metal substance into a contact hole having an electron-donating surface, a desired portion of the insulating film having a non-electron-donating surface is surface-modified by energy beam irradiation. An electron-donating surface can be formed. If an electron-donating surface is formed in the form of a wiring pattern in this way, metal can be deposited with good selectivity again by the above-mentioned CVD method. If this process is repeated again, a multilayer wiring structure with three or more layers can be obtained. The metal film thus formed exhibits excellent properties as a wiring material, as will be described later.

Electron-donating materials are those in which free electrons exist in the substrate, or free electrons are intentionally generated, and chemical reactions are promoted by electron transfer with raw material gas molecules attached to the substrate surface. A material with a surface that is

For example, metals and semiconductors generally correspond to this. In addition, materials in which a thin oxide film is present on the surface of a metal or semiconductor are also included in the electron-donating materials of the present invention, since chemical reactions can occur between the substrate surface and attached raw material molecules by electron transfer.

Similarly, even if the surface is made of an insulating material, high-energy beams such as α-rays, β-rays, γ-rays, ion beams, or electron beams can be irradiated. The electrons of the present invention also include those in which the physical structure or chemical bonding state of the insulating film surface irradiated with the energy beam is changed so that a chemical reaction can occur between the substrate surface and the attached raw material molecules by electron transfer. Included in donating materials.

Specific examples of electron-donating materials include Ga, In, Al1, etc. as group III elements, and P as group V elements.
, As, N, etc., or a semiconductor material such as a binary, ternary or more multi-component group III-V compound semiconductor, or single crystal silicon or amorphous silicon. Or the following metals, alloys, sisosite, etc., such as tungsten, molybdenum, tantalum, copper, titanium, aluminum, titanium aluminum, titanium nitride, aluminum silicon copper, aluminum palladium, tungsten silicide, titanium silicide, aluminum silicide , molybdenum silicide, tantalum silicide, and the like.

Furthermore, examples of insulating materials include silicon oxide and silicon nitride, which have surfaces that are chemically active when irradiated with high-energy beams.

On the other hand, materials forming the surface on which Al1 or Al1-3i is not selectively deposited, that is, non-electron-donating materials, include silicon oxide formed by thermal oxidation, CVD, etc., BSG, PSG, BPSG, etc. glass or oxide film, thermal nitride film, plasma CVD method, low pressure CVD method,
Examples include insulating materials that have a stable surface and do not easily exchange electrons on the surface, such as a silicon nitride film formed by ECR-CVD or the like.

Next, the above-mentioned CVD method will be explained in detail.

Here, an example is shown in which the inside of the contact hole is filled by the CVD method, and then metal is deposited on the entire surface of the insulating film by the well-known sputtering method and then patterned. The present invention improves the method for forming wiring on a film and provides an even more excellent method for forming wiring.

Therefore, the following explanation is only useful for understanding whether the film deposited by this CVD method has excellent properties and how it is an excellent method for forming wiring for semiconductor devices. Will.

(Film Forming Method) A film forming method suitable for forming the electrode according to the present invention will be described below.

This method is a film forming method used to fill a contact hole with a conductive material in order to form an electrode having the above-described structure.

A film forming method suitable for the present invention is one in which a deposited film is formed on an electron-donating substrate by a surface reaction using an alkyl aluminum hydride gas and hydrogen gas (
(hereinafter referred to as the Al-CVD method). In particular, it is possible to deposit high-quality Aj211i by using monomethylaluminum hydride (MMAH) or dimethylaluminum hydride (DMAH) as the raw material gas, using H2 gas as the reaction gas, and heating the substrate surface under a mixture of these gases. I can do it. Here, when selectively depositing An, it is preferable to maintain the surface temperature of the substrate at a temperature higher than the decomposition temperature of the alkyl aluminum hydride and lower than 450° C. by direct heating or indirect heating, more preferably between 260° C. and 440 t: or lower.

Methods for heating the substrate to the above temperature range include direct heating and indirect heating, and in particular, if the substrate is maintained at the above temperature by direct heating, a high quality An film can be formed at a high deposition rate. For example, the substrate surface temperature at the time of forming the ρ film is set to a more preferable temperature range of 260'C to 440'C.
t, a high-quality film can be obtained at a deposition rate higher than that in the case of resistance heating, which is 3000 to 5000 people/min. Examples of such a method of direct heating (energy from a heating means is directly transmitted to the substrate to heat the substrate itself) include lamp heating using a halogen lamp, a xenon lamp, or the like. In addition, there is resistance heating as a method of indirect heating, which is carried out using a heating element etc. provided on a substrate support member disposed in a space for forming a deposited film to support a substrate on which a deposited film is to be formed. I can do it.

By applying the CVD method to a substrate in which electron-donating surface portions and non-electron-donating surface portions coexist, Al
A single crystal of 2 is formed. This material has excellent properties in all respects desired as an electrode/wiring material. That is,
This results in a reduction in the probability of hillock occurrence and a reduction in the probability of alloy spike occurrence.

This is because high-quality Al1 can be selectively formed on a surface made of a semiconductor or conductor as an electron-donating surface, and because Al1 has excellent crystallinity, it can undergo a eutectic reaction with underlying silicon, etc. It is considered that there is almost no formation of alloy spikes or the like, or that there is no wheat at all. When used as an electrode in a semiconductor device, effects that go beyond the conventional concept of an All-Al electrode can be obtained that could not be expected with conventional technology.

As mentioned above, it was explained that AA deposited on an electron-donating surface, for example, in an opening formed in an insulating film and exposing the surface of a semiconductor substrate, has a single crystal structure, but according to this ^1-CVD method, It is also possible to selectively deposit metal films mainly composed of AI2 as shown below, and the film quality also exhibits excellent characteristics.

For example, in addition to alkyl aluminum hydride gas and hydrogen, SiH4, Si2 Ha, Sf3 Ha, 5i(CHs
) a, 5iCI14. SiH2Cl1z, 5iHCj2
Gas containing Si atoms such as TiCl1. , Ti
Br4. Gases containing T1 atoms such as Ti (CH3)a, bisacetylacetonatocopper Cu (C5H702) 2
, bisdipivaloyl methanite copper Cu(Cz)l+90
2)2. bishexafluoroacetylacetonatocopper C
υ (C5HF602) 2, etc. are introduced in appropriate combination to create a mixed gas atmosphere, such as AIL-3i%A11-Ti, AI2-Cu, A
The electrode may be formed by selectively depositing a conductive material such as l1-3i-Ti or An-Si-Cu.

In addition, since the above ^1-CVD method is a film forming method with excellent selectivity and the surface properties of the deposited film are good, a non-selective film forming method is applied to the next deposition process. By forming a metal film containing AI2 or Afl as a main component also on the selectively deposited Aj2@ and SiO2 as an insulating film, a suitable metal film with high versatility as wiring for semiconductor devices can be obtained. can be obtained.

Specifically, such a metal film is as follows. Selectively deposited AI, Al1-5i, A11-Ti, A
LL-Cu, Al1-5i-Ti, AI2-3t-Cu
and A1, A11-3i, Afl-T deposited non-selectively.
i, AI2-Cu, Al1-5t-T i, AJl-3
For example, a combination with 1-Cu.

As a film forming method for non-selective volume, the above-mentioned AI-C is used.
There are CVD methods, sputtering methods, etc. other than the VD method.

(Film Forming Apparatus) Next, a film forming apparatus suitable for forming the electrode according to the present invention will be described.

FIGS. 6 to 9 schematically show a continuous metal film forming apparatus suitable for applying the film forming method described above.

As shown in FIG. 6, this metal film continuous forming apparatus is a load-lock system that is connected to each other through gate valves 310a to 310f so that they can communicate with each other while being shut off from outside air. 31 j
, a CVD reaction chamber 312 as a first film-forming chamber, an Rf etching chamber 313, and a sputtering chamber 31 as a second film-forming chamber.
4, load lock chambers 3 and 5, and each chamber is configured to be evacuated and depressurized by exhaust systems 316a to 316e, respectively. Here, the load lock chamber 31 is a chamber for replacing the substrate atmosphere before the deposition process with H3 atmosphere after exhausting to improve throughput performance. The next CVD reaction chamber 312 is a chamber in which selective deposition is performed on the substrate by the above-mentioned AI-CVD method under normal pressure or reduced pressure, and the substrate surface to be deposited is heated to at least 200°C.
A base holder 318 having a heating resistor 317 that can be heated in the range of ~450°C is provided inside, and a CV
A raw material gas such as alkyl aluminum hydride, which has been bubbled with hydrogen and vaporized by a bubbler 319-1, is introduced into the room through the D raw material gas introduction line 3]9, and hydrogen gas as a reaction gas is also introduced from the gas line 319°. It is configured to The next Rf etching chamber 313 cleans the substrate surface after selective deposition (
This is a chamber for performing etching) under an Ar atmosphere, and inside is provided with a substrate holder 320 that can heat the substrate at least in the range of 100°C to 250°C, an electrode line 321 for Rf etching, and an Ar gas supply. line 3
22 are connected. The next sputtering chamber 314 is a chamber in which a metal film is non-selectively deposited on the substrate surface by sputtering in an Ar atmosphere, and the interior temperature is at least 200°C to 200°C.
A substrate holder 323 heated in a range of 50°C and a target electrode 32 to which a sputter target material 324a is attached.
4 is provided, and an Ar gas supply line 325 is provided.
is connected. The last load lock chamber 315 is an adjustment chamber before the substrate is exposed to the outside air after the metal film deposition is completed.
It is configured to replace the atmosphere with N2.

FIG. 7 shows another configuration example of a continuous metal film forming apparatus suitable for applying the above-described film forming method, and the same parts as those described above are given the same reference numerals. The difference from the device in FIG. 7 is that a halogen lamp 330 is used as a direct heating means.
is provided, and the substrate surface can be directly heated.
To this end, the base holder 312 is provided with a claw 331 that holds the base in a floating state.

With this configuration, by directly heating the substrate surface, it is possible to further improve the deposition rate as described above.

As shown in FIG. 8, the metal film continuous forming apparatus having the above configuration actually includes the load lock chamber 311, the CVD reaction chamber 312, the Rf etching chamber 313, the sputtering chamber 314, and the transfer chamber 326 as a relay chamber. This is substantially equivalent to a structure in which the load lock chambers 315 are interconnected. In this configuration, the load lock chamber 311 is
It also serves as 5. As shown in FIG. 8, the transfer chamber 326 is provided with an arm 327 as a transfer means that can be rotated forward and backward in the AA force direction and extendable and retractable in the BB direction.
This arm 327 allows the substrate to be exposed to the outside air from the load lock chamber 311 to the CVD chamber 312, the Rf etching chamber 313, the sputter chamber 314, and the load rotor chamber 315 in order according to the process, as shown by the arrow in FIG. It is now possible to move it continuously.

(Film Forming Procedure) A film forming procedure for forming electrodes and wiring according to the present invention will be described.

FIG. 10 is a schematic perspective view for explaining the film forming procedure for forming electrodes and wiring according to the present invention.

First, I will explain the outline. A semiconductor substrate with holes formed in an insulating film is prepared, and this substrate is placed in a film forming chamber, and its surface is maintained at a temperature of, for example, 260°C to 450°C, and DMAH gas and hydrogen gas are added to form an alkyl aluminum hydride. 8ρ is selectively deposited on the exposed portion of the semiconductor inside the opening by thermal CVD in a mixed atmosphere. Of course, as described above, a gas containing Si atoms or the like may be introduced to selectively deposit a metal film mainly composed of Au2 such as Aρ-Si. Next, A was selectively deposited by sputtering method.
A metal film containing Au2 or An as a main component is non-selectively formed on u2 and the insulating film. Thereafter, electrodes and wiring can be formed by patterning the non-selectively deposited metal film in a desired wiring shape.

Next, a substrate is prepared, which will be explained in detail with reference to FIGS. 7 and 10. The substrate is prepared, for example, by forming an insulating film with openings of various diameters on a single-crystal Si wafer soil.

FIG. 10(A) is a schematic diagram showing a part of this base. Here, 401 is a single crystal silicon substrate as a conductive substrate, and 402 is a thermally oxidized silicon film as an insulating film (layer). 403 and 404 are openings (exposed parts),
Each has a different caliber.

Referring to FIG. 7, the procedure for forming an Au film as an electrode as a first wiring layer on a substrate is as follows.

First, the base body described above is placed in the load lock chamber 311. Hydrogen is introduced into the load lock chamber 311 as described above to create a hydrogen atmosphere. And exhaust system 316b
The inside of the reaction chamber 312 is evacuated to approximately 1xlO"' Torr.However, the degree of vacuum inside the reaction chamber 312 is 1xlO"'Torr.
A film of A, 12 can be formed even if it is worse than Torr.

Then, the DMA bubbled from the gas line 319
Supply H gas. N2 is used as the carrier gas for the DMAH line.

The second gas line 319゛ is for N3 as a reaction gas, and N7 is flowed from this second gas line 319゛.
The reaction chamber 3 is opened by adjusting the opening degree of a slow leak valve (not shown).
12 to a predetermined value. A typical pressure in this case is approximately 1.5 Torr. DM from DMAH line
AH is introduced into the reaction tube. Total pressure approximately 1.5 Torr
, DMA8 partial pressure is approximately 5.0XIO-'TOrr.

Thereafter, the halogen lamp 330 is energized to directly heat the wafer. In this way, A1 is selectively deposited.

After a predetermined deposition time has elapsed, the supply of DMAH is temporarily stopped. The predetermined deposition time for the A film deposited in this process is the time required until the thickness of All@ on Si (single crystal silicon substrate 1) becomes equal to the film thickness of 5i02 (thermal oxidized silicon@2). It is time and can be determined in advance through experiments.

The temperature of the substrate surface due to direct heating of the gloss is approximately 270°C. According to the steps up to this point, Af1@405 is selectively deposited inside the openings as shown in FIG. 10(B).

The above process is referred to as a first film forming process for forming an electrode in a contact hole.

After the first film forming step, the CVD reaction chamber 312 is
6b until a vacuum level of 5xlO-'Torr or less is reached. At the same time, the Rf etching chamber 313 is
Exhaust to below X10-6 Torr. After confirming that both chambers have reached the above degree of vacuum, the gate valve 310C is opened and the substrate is transferred from the CVD reaction chamber 312 to the R
f Move to the etching chamber 313 and open the gate valve 310C.
Close. The substrate is transferred to the Rf etching chamber 313, and the Rf etching chamber 313 is heated to 1.0-
Evacuate until a vacuum level of 6 Torr or less is reached. After that, argon is supplied through the Rff etching argon supply line 322, and the Rf etching chamber 313 is
Maintain an argon atmosphere of 10-3 orr. The Rff etching substrate holter 320 is maintained at about 200° C., and Rf power of the Rf etching electric power 1321100 W is supplied for 60 seconds with the valve open to generate argon discharge in the Rf etching chamber 313. In this way, the surface of the substrate can be etched with argon ions, and unnecessary surface layers of the CVD 1 film can be removed. In this case, the etching depth is approximately 100 metal degrees equivalent to the oxide. Here, the surface of the CVD deposited film was etched in the Rf etching chamber, but since the CVD surface layer of the substrate transported in vacuum does not contain atmospheric oxygen, Rff etching was not performed. It can't be beat. In that case, the Rf etching chamber 313 includes the CVD reaction chamber 12 and the sputtering chamber 314.
When there is a large temperature difference, the chamber functions as a temperature change chamber to change the temperature in a short period of time.

After the Rff etching is completed in the Rf etching chamber 313, the flow of argon is stopped and the argon in the Rf etching chamber 313 is exhausted.

After the Rf etching chamber 313 is evacuated to 5X10-6 Torr and the sputtering chamber 314 is evacuated to 5xio-'Torr or less, the gate valve 310d is opened. Thereafter, the substrate is moved from the Rf etching chamber 313 to the sputtering chamber 314 using a transport means, and the gate valve 310d is closed.

After transporting the substrate to the sputtering chamber 314, the sputtering chamber 3
! 4 to 0-' to 10- as in the Rf etching chamber 313.
The temperature of the substrate holter 323 on which the substrate is placed is set to about 200 to 250°C. Then, argon discharge is performed with a DC power of 5 to 10 kW, and Al and Al1-5 i (S i :
1000% of metal such as Al2 or Afl-5i is ground on the substrate -F by cutting the tarcerate material such as O, '5%) with argon ions.
Film formation is performed at a deposition rate of about 0 people/minute. This process is a non-selective deposition process. This is called a second film forming step for forming wiring to connect to the electrodes.

After forming about 5000 metal films on the substrate, the flow of argon and the application of DC power are stopped. After exhausting the load lock chamber 311 to below 5X10-'Torr,
Gate valve 3] Open Oe and move the substrate. After closing the gate valve 310e, N2 gas is caused to flow into the lock chamber 311 until it reaches atmospheric pressure, and the gate valve 310
Open f and take the substrate out of the device.

According to the second film forming step described above, the Aj2 film 406 can be formed on the 5i02 film 402 as shown in FIG. 10(C).

Then, by patterning this Al film 406 as shown in FIG. 10(D), wiring in a desired shape can be obtained.

(Experimental Example) The superiority of the Al-CVD method described above and the high quality of the film deposited in the openings using the Al-CVD method will be explained below based on experimental results.

First, the surface of an N-type single crystal silicon wafer as a substrate was thermally oxidized to form 8000 5i02 and 0.25μmX
A plurality of openings with various diameters ranging from 0.25 μm square to 100 μm×100 μm square were patterned to expose the underlying Si single crystal. (Sample 1-1) These were processed into Al1 by Al-CVD method under the following conditions.
A film was formed. DMAH1 reaction gas as deposition gas, hydrogen as gas, total pressure 1,5 Torr s
D M Under the common condition that the partial pressure of AH is 5.0XIO-3 Torr, the amount of electricity supplied to the halogen lamp is adjusted and the substrate surface temperature is directly heated to 200°C to 490°C.
Film formation was performed with the setting within the range of .

The results are shown in Table 1.

As can be seen from Table 1, the substrate surface temperature due to direct heating is 2.
At temperatures above 60°C, Al2 has a concentration of 3000 to 5000 in the open pores.
selectively deposited at high deposition rates of 1 person/min.

When examining the characteristics of A42@ in the open pores when the substrate surface temperature is in the range of 260°C to 440°C, it is found that there is no carbon content, resistivity is 2.8 to 3.4 μΩcm, reflectance is 90 to 95%, 1
It was found that the hillock density of μm or more was 0 to 10 cm-'', and it had good characteristics with almost no spike occurrence (probability of failure of a 0.15 μm junction).

On the other hand, when the substrate surface temperature is 200°C to 250°C,
Although the film quality is slightly worse than in the case of 260°C to 440°C, it looks quite good based on the conventional technology, but the deposition rate is not high enough at 1000 to 1500 people/min, and the throughput is also low. The rate is relatively low at 7-10 sheets/h.

In addition, when the substrate surface temperature is 450°C or higher, the reflectance is 60% or less, and the hillock density of 1 μm or more is 10 to 10'.
cm-2, the occurrence of alloy spikes was 0 to 30%, and the properties of the Aρ film within the pores were degraded.

Next, it will be explained how the above-described method can be suitably used for opening holes such as contact holes and through holes.

That is, it is preferably applied to contact hole/through hole structures made of the materials described below.

An was applied to the substrate (sample) having the structure described below under the same conditions as when Afl was formed on the sample 1-1 described above.
A film was formed.

A silicon oxide film as a second substrate surface material is formed by CVD on the single crystal silicon soil as the first substrate surface material, and buttering is performed by a photolithography process to partially cover the single crystal silicon surface. I made a comparison.

At this time, the thickness of the thermally oxidized SiO2 film was 8,000 mm, and the size of the exposed part of the single crystal silicon, that is, the opening, was Q, g5 μm
It was 9.25 μm to 100 μm x 100 μm. Sample ]-2 was thus prepared. (Hereinafter, such a sample will be referred to as “CVDSi, 02 (hereinafter S f O
(abbreviated as 2)/monocrystalline silicon”)
.

Sample 1-3 is a poron-doped oxide film (hereinafter abbreviated as BSG)/single crystal silicon formed by atmospheric pressure CVD, and Sample 1-4 is a phosphorus-doped oxide film (hereinafter abbreviated as PSG)/ Sample 1-5 is a phosphorus- and poron-doped oxide film (hereinafter referred to as BSPG)/single-crystal silicon deposited by atmospheric pressure CVD; Sample 1-6 is a nitride film deposited by plasma CVD (hereinafter referred to as P- Samples 1-7 are thermal nitride films (abbreviated as T-SiN)/
Single-crystal silicon, Sample 1-8 is a nitride film (
(hereinafter abbreviated as LP-3iN)/single-crystal silicon sample]-9 is a nitride film (hereinafter abbreviated as LP-3iN) formed by an ECR device.
(hereinafter abbreviated as ECR-5iN)/single crystal silicon.

Furthermore, samples 1-11 to 1-x79 (?Main: Sample number 1-
10.20, 30.40.50.60, 70.80.9
0.100.1101120.130.140.150
．． 160.170 are missing numbers). Single crystal silicon (single crystal Si), polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous S1) as the first substrate surface material
, tungsten (W), molybdenum (MO), tantalum (T a ), tungsten silicide (wsi>,
Titanium silicide (TiSi).

Aluminum (Al2), aluminum silicon (Al
1-3i), titanium aluminum (8ρ-Ti), titanium nitride (Ti-N), copper (Cu), aluminum silicon copper (All-3i-Cu), aluminum palladium (Al1-Pd), titanium (Ti ), molybdenum silicide (Mo-Si), and tantalum silicide (Ta-Si) were used. The second substrate surface material is T-3i02, Si02, BSG, PSG.
, BPSG, P-SiN, T-SiN, LP-SiN,
It is ECR-3iN. For all of the samples described above, it was possible to form good Al2 films comparable to those of sample 1-1 described above.

Next, on the substrate on which Al1 was selectively deposited as described above, Al2 was non-selectively deposited by the sputtering method described above and patterned.

As a result, the Al film produced by sputtering and the selectively deposited Al1 inside the openings have good electrical and mechanical durability due to the good surface properties of the A and Q films inside the openings. There was a high level of contact.

(Example 1) <Circuit Description> As this example, a method for forming wiring in an Af12 layer wiring process, particularly in an upper layer/MZ layer, in a semiconductor integrated circuit will be described. FIG. 3 shows the connections of the AI1 pattern shown in this embodiment. Figure 'tS3 shows a small part of the grid-like H1 wiring pattern. In Figure 3, 10
8 is the connection of the upper layer A1, and 109a and 109b are the connections of the lower layer Al.

110 is the intersection of 109b and 108, and the black dot indicates that both are connected via a through hole. On the other hand, there is no through hole pattern at the intersection 111 between 109a and 108, and the two are not connected. In this way, a custom LSI such as a gate array can be constructed by adopting a method of determining the presence or absence of a connection based on the presence or absence of a through hole. In other words, the process up to the opening of the through-holes is performed in advance, and the presence or absence of through-holes is determined according to the circuit ordered by the customer, and the circuit is formed.

<Description of Apparatus for Forming Wiring> FIG. 1 is a style diagram showing the concept of a system for electron beam exposure that can be suitably applied to this embodiment. The pattern data of the upper Al layer is converted by an arithmetic circuit to provide data for controlling the electron beam.

101a is a focused electron beam source having an electron beam source, a focusing lens, and a polarizing lens.

An electron beam generated within 101a and whose direction is controlled by a polarizing lens passes through an aperture 101b to the semiconductor substrate 104.
is irradiated.

FIG. 2 shows how a pattern is drawn by irradiation with an electron beam. In FIG. 2, 105 indicates a beam source and a polarizing lens, 06 indicates an electron beam bundle, and 104
107 indicates a semiconductor substrate, and 107 indicates an irradiated electron beam pattern.

<Wiring formation method> Next, using FIGS. 1 to 5, Aj2 in this example is
A method for forming wiring will be explained. As described above, data for one wiring pattern for the upper layer is prepared as pattern data. A semiconductor substrate 104 to be irradiated with a beam, which has a through hole for connecting the lower layer All wiring, the insulating film covering it, and the upper layer Afl to the lower layer Aj2, is placed in a chamber 102 serving as a drawing chamber.

After drawing the wiring pattern with an electron beam as shown in Figure 2,
The semiconductor substrate is taken out from the chamber 102. The situation at this time is shown in FIG. In FIG. 4, 120 is the active region of the silicon substrate, 121 is the lower layer Al wiring, 122 is the insulating film, 123 is the irradiated region of the electron beam, and 124 is the through hole opening.

Next, place the wafer in a chamber for AJZ vapor phase growth,
DMAH as alkyl aluminum hydride (
Dimethyl Aluminum Hydri
de) Using AflH(CH3)2 gas and hydrogen as a reaction gas, at a substrate surface temperature of around 290°C, Al1 is deposited only on the region 123 irradiated with the electron beam. is deposited. At this time, the Al2@thickness is assumed to be approximately 8,000 people. FIG. 5 shows the situation immediately after this. After this, the upper layer Al is heat-treated at 400°C for about 30 minutes in a nitrogen atmosphere.
It is possible to improve the ohmic contact between Aj1 and the lower layer Aj2 and obtain a sufficiently low contact resistance.

<Comparison Results> Experimental Example> A plurality of samples having shapes as shown in FIG. 5 were prepared according to the above-described procedure.

These samples have a width (line width) of the upper layer All of 02
5 to 2 μm, and the distance (space width) between the upper layers A42 to 0.
25 to 2 μm, and the maximum step difference was 0.5 to 2.0 μm by changing the layer thickness of the lower Al layer.

Comparative Example> Similar to the experimental example described above using the conventional method (λ = 186 nm, NA = 40), the width (line width) of the upper layer Al was 0.2
5-2 μm, distance between upper layers A and Q is 1! + (space width) was set to 0.25 to 2 μm, and the layer thickness of the lower layer A1 was changed to create one with a maximum step difference of 0.5 to 2.0 μm.

Table 2 shows the quality of the shape of the upper layer Al wiring of samples prepared by the experimental example according to the present invention and by the conventional method.
Table 2 shows the L/S as a parameter. O marks are those with almost good patterning, Δ marks are those with some sag in the pattern, x
The marks indicate defects such as short circuits between wires.

According to the experimental examples according to the present invention, wiring could be formed without causing defects between wirings such as short circuits under any of the conditions listed in Table 2. On the other hand, with the conventional method, it has not been possible to form a step difference of 1.0 μm or more or an L/S pattern of 0.25 μm without causing defects between interconnections.

<Effects of the present invention> ■An anti-reflection layer and resist forming process are no longer required,
Since the process becomes easier, the yield, which was conventionally limited by poor patterning, can be significantly improved.

(2) Desired wiring patterns can be formed even on large steps.

■It is effective for miniaturizing chips because it can draw patterns as fine as the beam diameter of the beam source.

(2) By using selective vapor phase epitaxy, it is possible to create highly reliable wiring with good step coverage even when miniaturized.

[Brief explanation of drawings]

FIG. 1 is a schematic explanatory diagram of a system for implementing the present invention. FIG. 2 is a schematic illustration of selective irradiation with an energy beam, and FIG. 3 is a schematic explanatory diagram of a wiring pattern. FIGS. 4 and 5 are schematic explanatory diagrams of steps in the wiring forming method of the present invention. FIGS. 6 to 9 are schematic explanatory diagrams showing examples of continuous film forming apparatus suitable for applying the present invention. FIG. 10 is a schematic perspective view for explaining the film forming procedure of the wiring forming method of the present invention. FIG. 11(A) to FIG. 11(C) are schematic explanatory diagrams of the prior art. FIG. 12(A) and FIG. 12(B) are ridge-style explanatory diagrams of conventional defects. 121... Lower layer Al wiring 122... Insulating film 123... Area irradiated with energy 311...
Load lock chamber 312...CVD reaction chamber 313...Etching chamber 314...Sputtering chamber 326...Transfer chamber 402...Insulating film 403, 404...Opening 405...Selectively formed Conductive metal film 406
...Non-selectively formed conductive metal film chamber 2 - Figure ℃L - -105, jet p (2 notes gt + 1rEQcA) (E3) T120 (C) Iρ /14/

Claims (5)

[Claims] (1) In a method for forming wiring in a semiconductor device having an insulating film on an insulating film, selectively irradiating a portion of the insulating film where a wiring is to be formed with a high-energy beam to deposit a conductive metal substance. A method for forming wiring in a semiconductor device, the method comprising the step of performing a deposition process and selectively depositing a conductive metal substance on the irradiated portion. (2) A method for forming wiring in a semiconductor device, in which the conductive metal substance is deposited by a CVD method using an alkyl aluminum halide gas and hydrogen. (3) The method for forming interconnects in a semiconductor device according to claim 1, wherein the high-energy beam is a focused electron beam. (4) The method for forming interconnects in a semiconductor device according to claim 1, wherein the conductive metal material is Al. (5) The method for forming interconnects in a semiconductor device according to claim 1, wherein the conductive metal substance is a metal substance containing Al as a main component.