Merge tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Olof Johansson:
"Like always, the DT branch is sizable. There are numerous additions
and fixes to existing platforms, but also a handful of new ones
introduced. Less than some other releases, but there's been
significant work on cleanups, refactorings and device enabling on
existing platforms.
A non-exhaustive list of new material:
- Refactoring of BCM2711 dtsi structure to add support for the
Raspberry Pi 400
- Rockchip: RK3568 SoC and EVB, video codecs for
rk3036/3066/3188/322x
- Qualcomm: SA8155p Automotive platform (SM8150 derivative),
SM8150/8250 enhancements and support for Sony Xperia 1/1II and
5/5II
- TI K3: PCI/USB3 support on AM64-sk boards, R5 remoteproc
definitions
- TI OMAP: Various cleanups
- Tegra: Audio support for Jetson Xavier NX, SMMU support on Tegra194
- Qualcomm: lots of additions for peripherals across several SoCs,
and new support for Microsoft Surface Duo (SM8150-based), Huawei
Ascend G7.
- i.MX: Numerous additions of features across SoCs and boards.
- Allwinner: More device bindings for V3s, Forlinx OKA40i-C and
NanoPi R1S H5 boards
- MediaTek: More device bindings for mt8167, new Chromebook system
variants for mt8183
- Renesas: RZ/G2L SoC and EVK added
- Amlogic: BananaPi BPI-M5 board added"
* tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (511 commits)
arm64: dts: rockchip: add basic dts for RK3568 EVB
arm64: dts: rockchip: add core dtsi for RK3568 SoC
arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs
ARM: dts: rockchip: add vpu and vdec node for RK322x
ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188
ARM: dts: rockchip: add vpu node for RK3036
arm64: dts: ipq8074: Add QUP6 I2C node
arm64: dts: rockchip: Re-add regulator-always-on for vcc_sdio for rk3399-roc-pc
arm64: dts: rockchip: Re-add regulator-boot-on, regulator-always-on for vdd_gpu on rk3399-roc-pc
arm64: dts: rockchip: add ir-receiver for rk3399-roc-pc
arm64: dts: rockchip: Add USB-C port details for rk3399 Firefly
arm64: dts: rockchip: Sort rk3399 firefly pinmux entries
arm64: dts: rockchip: add infrared receiver node to RK3399 Firefly
arm64: dts: rockchip: add SPDIF node for rk3399-firefly
arm64: dts: rockchip: Add Rotation Property for OGA Panel
arm64: dts: qcom: sc7180: bus votes for eMMC and SD card
arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen
arm64: dts: qcom: sm8250-edo: Enable GPI DMA
arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI
arm64: dts: qcom: sm8250-edo: Enable PCIe
...
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 97fb962..6423377 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -167,6 +167,7 @@
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
+ - bananapi,bpi-m5
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
- khadas,vim3l
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
index 812ae8c..230b80d 100644
--- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
@@ -18,6 +18,7 @@
- description: BCM2711 based Boards
items:
- enum:
+ - raspberrypi,400
- raspberrypi,4-model-b
- const: brcm,bcm2711
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index e3c50f2..1c827c1 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -197,6 +197,7 @@
- boundary,imx6q-nitrogen6x
- compulab,cm-fx6 # CompuLab CM-FX6
- dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
+ - ds,imx6q-sbc # Da Sheng COM-9XX Modules
- embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
@@ -400,6 +401,17 @@
- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- const: fsl,imx6dl
+ - description: i.MX6DL based congatec QMX6 Boards
+ items:
+ - enum:
+ - ge,imx6dl-b105v2 # General Electric B105v2
+ - ge,imx6dl-b105pv2 # General Electric B105Pv2
+ - ge,imx6dl-b125v2 # General Electric B125v2
+ - ge,imx6dl-b125pv2 # General Electric B125Pv2
+ - ge,imx6dl-b155v2 # General Electric B155v2
+ - const: congatec,qmx6
+ - const: fsl,imx6dl
+
- description: i.MX6DL based DFI FS700-M60-6DL Board
items:
- const: dfi,fs700-m60-6dl
@@ -685,6 +697,7 @@
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
+ - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
index d72e92b..230bffe 100644
--- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
+++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
@@ -17,6 +17,7 @@
- items:
- enum:
- linksys,nslu2
+ - welltech,epbx100
- const: intel,ixp42x
- items:
- enum:
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index aff57a8..80a05f6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -122,6 +122,10 @@
- enum:
- mediatek,mt8195-evb
- const: mediatek,mt8195
+ - description: Google Burnet (HP Chromebook x360 11MK G3 EE)
+ items:
+ - const: google,burnet
+ - const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@@ -133,9 +137,19 @@
items:
- const: google,damu
- const: mediatek,mt8183
- - description: Google Juniper (Acer Chromebook Spin 311)
+ - description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
items:
- - const: google,juniper-sku16
+ - enum:
+ - google,fennel-sku0
+ - google,fennel-sku1
+ - google,fennel-sku6
+ - const: google,fennel
+ - const: mediatek,mt8183
+ - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
+ items:
+ - enum:
+ - google,juniper-sku16
+ - google,juniper-sku17
- const: google,juniper
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
@@ -144,6 +158,10 @@
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
+ - description: Google Kappa (HP Chromebook 11a)
+ items:
+ - const: google,kappa
+ - const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@@ -153,6 +171,13 @@
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Willow (Acer Chromebook 311 C722/C722T)
+ items:
+ - enum:
+ - google,willow-sku0
+ - google,willow-sku1
+ - const: google,willow
+ - const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 9b27e99..9720b00 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -36,17 +36,20 @@
msm8992
msm8994
msm8996
+ sa8155p
sc7180
sc7280
sdm630
sdm660
sdm845
sdx55
+ sm8150
sm8250
sm8350
The 'board' element must be one of the following strings:
+ adp
cdp
cp01-c1
dragonboard
@@ -178,6 +181,7 @@
- items:
- enum:
- qcom,sc7280-idp
+ - google,senor
- const: qcom,sc7280
- items:
@@ -200,6 +204,16 @@
- items:
- enum:
+ - qcom,sa8155p-adp
+ - const: qcom,sa8155p
+
+ - items:
+ - enum:
+ - qcom,sm8150-mtp
+ - const: qcom,sm8150
+
+ - items:
+ - enum:
- qcom,qrb5165-rb5
- qcom,sm8250-mtp
- const: qcom,sm8250
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 5fd0696..a0cce4e 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -302,6 +302,24 @@
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- const: renesas,r9a06g032
+ - description: RZ/G2UL (R9A07G043)
+ items:
+ - enum:
+ - renesas,r9a07g043u11 # RZ/G2UL Type-1
+ - renesas,r9a07g043u12 # RZ/G2UL Type-2
+ - const: renesas,r9a07g043
+
+ - description: RZ/G2{L,LC} (R9A07G044)
+ items:
+ - enum:
+ - renesas,smarc-evk # SMARC EVK
+ - enum:
+ - renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC
+ - renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
+ - renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L
+ - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
+ - const: renesas,r9a07g044
+
additionalProperties: true
...
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 4a6f772..6546b01 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -600,6 +600,11 @@
- const: zkmagic,a95x-z2
- const: rockchip,rk3318
+ - description: Rockchip RK3568 Evaluation board
+ items:
+ - const: rockchip,rk3568-evb1-v10
+ - const: rockchip,rk3568
+
additionalProperties: true
...
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index ac75002..889128a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -224,6 +224,12 @@
- const: empire-electronix,m712
- const: allwinner,sun5i-a13
+ - description: Forlinx OKA40i-C Development board
+ items:
+ - const: forlinx,oka40i-c
+ - const: forlinx,feta40i-c
+ - const: allwinner,sun8i-r40
+
- description: FriendlyARM NanoPi A64
items:
- const: friendlyarm,nanopi-a64
@@ -269,6 +275,11 @@
- const: friendlyarm,nanopi-r1
- const: allwinner,sun8i-h3
+ - description: FriendlyARM NanoPi R1S H5
+ items:
+ - const: friendlyarm,nanopi-r1s-h5
+ - const: allwinner,sun50i-h5
+
- description: FriendlyARM ZeroPi
items:
- const: friendlyarm,zeropi
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 43fd2f8..0afec83 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -301,6 +301,33 @@
additionalProperties: false
+ core-domain:
+ type: object
+ description: |
+ The vast majority of hardware blocks of Tegra SoC belong to a
+ Core power domain, which has a dedicated voltage rail that powers
+ the blocks.
+
+ properties:
+ operating-points-v2:
+ description:
+ Should contain level, voltages and opp-supported-hw property.
+ The supported-hw is a bitfield indicating SoC speedo or process
+ ID mask.
+
+ "#power-domain-cells":
+ const: 0
+
+ required:
+ - operating-points-v2
+ - "#power-domain-cells"
+
+ additionalProperties: false
+
+ core-supply:
+ description:
+ Phandle to voltage regulator connected to the SoC Core power rail.
+
required:
- compatible
- reg
@@ -325,6 +352,7 @@
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
+ core-supply = <®ulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
@@ -338,17 +366,24 @@
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ pd_core: core-domain {
+ operating-points-v2 = <&core_opp_table>;
+ #power-domain-cells = <0>;
+ };
+
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
deleted file mode 100644
index ab730ea..0000000
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ /dev/null
@@ -1,313 +0,0 @@
-Broadcom iProc Family Clocks
-
-This binding uses the common clock binding:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The iProc clock controller manages clocks that are common to the iProc family.
-An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
-LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
-comprises of several leaf clocks
-
-Required properties for a PLL and its leaf clocks:
-
-- compatible:
- Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
-Cygnus has a compatible string of "brcm,cygnus-genpll"
-
-- #clock-cells:
- Have a value of <1> since there are more than 1 leaf clock of a given PLL
-
-- reg:
- Define the base and range of the I/O address space that contain the iProc
-clock control registers required for the PLL
-
-- clocks:
- The input parent clock phandle for the PLL. For most iProc PLLs, this is an
-onboard crystal with a fixed rate
-
-- clock-output-names:
- An ordered list of strings defining the names of the clocks
-
-Example:
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- };
-
- genpll: genpll {
- #clock-cells = <1>;
- compatible = "brcm,cygnus-genpll";
- reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
- "enet_sw", "audio_125", "can";
- };
-
-Required properties for ASIU clocks:
-
-ASIU clocks are a special case. These clocks are derived directly from the
-reference clock of the onboard crystal
-
-- compatible:
- Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
-clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
-
-- #clock-cells:
- Have a value of <1> since there are more than 1 ASIU clocks
-
-- reg:
- Define the base and range of the I/O address space that contain the iProc
-clock control registers required for ASIU clocks
-
-- clocks:
- The input parent clock phandle for the ASIU clock, i.e., the onboard
-crystal
-
-- clock-output-names:
- An ordered list of strings defining the names of the ASIU clocks
-
-Example:
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- };
-
- asiu_clks: asiu_clks {
- #clock-cells = <1>;
- compatible = "brcm,cygnus-asiu-clk";
- reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
- clocks = <&osc>;
- clock-output-names = "keypad", "adc/touch", "pwm";
- };
-
-Cygnus
-------
-PLL and leaf clock compatible strings for Cygnus are:
- "brcm,cygnus-armpll"
- "brcm,cygnus-genpll"
- "brcm,cygnus-lcpll0"
- "brcm,cygnus-mipipll"
- "brcm,cygnus-asiu-clk"
- "brcm,cygnus-audiopll"
-
-The following table defines the set of PLL/clock index and ID for Cygnus.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-cygnus.h"
-
- Clock Source (Parent) Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
- keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
- adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
- pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
-
- genpll crystal 0 BCM_CYGNUS_GENPLL
- axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
- 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
- ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
- enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
- audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
- can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
-
- lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
- pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
- ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
- sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
- usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
- smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
- ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
-
- mipipll crystal 0 BCM_CYGNUS_MIPIPLL
- ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
- ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
- ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
- ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
- ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
- ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
-
- audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
- ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
- ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
- ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
-
-Hurricane 2
-------
-PLL and leaf clock compatible strings for Hurricane 2 are:
- "brcm,hr2-armpll"
-
-The following table defines the set of PLL/clock for Hurricane 2:
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
-
-Northstar and Northstar Plus
-------
-PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
- "brcm,nsp-armpll"
- "brcm,nsp-genpll"
- "brcm,nsp-lcpll0"
-
-The following table defines the set of PLL/clock index and ID for Northstar and
-Northstar Plus. These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-nsp.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
- genpll crystal 0 BCM_NSP_GENPLL
- phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
- ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
- usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
- iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
- sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
- sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
-
- lcpll0 crystal 0 BCM_NSP_LCPLL0
- pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
- sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
- ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
-
-Northstar 2
------------
-PLL and leaf clock compatible strings for Northstar 2 are:
- "brcm,ns2-genpll-scr"
- "brcm,ns2-genpll-sw"
- "brcm,ns2-lcpll-ddr"
- "brcm,ns2-lcpll-ports"
-
-The following table defines the set of PLL/clock index and ID for Northstar 2.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-ns2.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
- scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
- fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
- audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
- ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
- ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
- ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
-
- genpll_sw crystal 0 BCM_NS2_GENPLL_SW
- rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
- 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
- nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
- chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
- port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
- sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
-
- lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
- pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
- ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
- ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
- ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
- ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
- ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
-
- lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
- wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
- rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
- ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
- ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
- ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
- ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
-
-BCM63138
---------
-PLL and leaf clock compatible strings for BCM63138 are:
- "brcm,bcm63138-armpll"
-
-Stingray
------------
-PLL and leaf clock compatible strings for Stingray are:
- "brcm,sr-genpll0"
- "brcm,sr-genpll1"
- "brcm,sr-genpll2"
- "brcm,sr-genpll3"
- "brcm,sr-genpll4"
- "brcm,sr-genpll5"
- "brcm,sr-genpll6"
-
- "brcm,sr-lcpll0"
- "brcm,sr-lcpll1"
- "brcm,sr-lcpll-pcie"
-
-
-The following table defines the set of PLL/clock index and ID for Stingray.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-sr.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
- crmu_ref25m crystal N/A N/A
-
- genpll0 crystal 0 BCM_SR_GENPLL0
- clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
- clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
- clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
- clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
- clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
- clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
-
- genpll1 crystal 0 BCM_SR_GENPLL1
- clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
- clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
-
- genpll2 crystal 0 BCM_SR_GENPLL2
- clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
- clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
- clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
- clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
- clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
- clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
-
- genpll3 crystal 0 BCM_SR_GENPLL3
- clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
- clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
-
- genpll4 crystal 0 BCM_SR_GENPLL4
- clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
- clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
- clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
- clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
- clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
-
- genpll5 crystal 0 BCM_SR_GENPLL5
- clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
- clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
- clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
-
- genpll6 crystal 0 BCM_SR_GENPLL6
- clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
-
- lcpll0 crystal 0 BCM_SR_LCPLL0
- clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
- clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
- clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
- clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
-
- lcpll1 crystal 0 BCM_SR_LCPLL1
- clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
- clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
- clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
-
- lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
- clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml
new file mode 100644
index 0000000..8dc7b40
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml
@@ -0,0 +1,395 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom iProc Family Clocks
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+description: |
+ The iProc clock controller manages clocks that are common to the iProc family.
+ An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
+ LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
+ comprises of several leaf clocks
+
+ ASIU clocks are a special case. These clocks are derived directly from the
+ reference clock of the onboard crystal.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm63138-armpll
+ - brcm,cygnus-armpll
+ - brcm,cygnus-genpll
+ - brcm,cygnus-lcpll0
+ - brcm,cygnus-mipipll
+ - brcm,cygnus-asiu-clk
+ - brcm,cygnus-audiopll
+ - brcm,hr2-armpll
+ - brcm,nsp-armpll
+ - brcm,nsp-genpll
+ - brcm,nsp-lcpll0
+ - brcm,ns2-genpll-scr
+ - brcm,ns2-genpll-sw
+ - brcm,ns2-lcpll-ddr
+ - brcm,ns2-lcpll-ports
+ - brcm,sr-genpll0
+ - brcm,sr-genpll1
+ - brcm,sr-genpll2
+ - brcm,sr-genpll3
+ - brcm,sr-genpll4
+ - brcm,sr-genpll5
+ - brcm,sr-genpll6
+ - brcm,sr-lcpll0
+ - brcm,sr-lcpll1
+ - brcm,sr-lcpll-pcie
+
+ reg:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: base register
+ - description: power register
+ - description: ASIU or split status register
+
+ clocks:
+ description: The input parent clock phandle for the PLL / ASIU clock. For
+ most iProc PLLs, this is an onboard crystal with a fixed rate.
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 45
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,cygnus-armpll
+ - brcm,cygnus-genpll
+ - brcm,cygnus-lcpll0
+ - brcm,cygnus-mipipll
+ - brcm,cygnus-asiu-clk
+ - brcm,cygnus-audiopll
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Cygnus.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-cygnus.h"
+
+ Clock Source (Parent) Index ID
+ ----- --------------- ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
+ adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
+ pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
+
+ genpll crystal 0 BCM_CYGNUS_GENPLL
+ axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
+ 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
+ ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
+ enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
+ audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
+ can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
+
+ lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
+ pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
+ ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
+ sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
+ usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
+ smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
+ ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
+
+ mipipll crystal 0 BCM_CYGNUS_MIPIPLL
+ ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
+ ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
+ ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
+ ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
+ ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
+ ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+
+ audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
+ ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
+ ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
+ ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,hr2-armpll
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock for Hurricane 2:
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,nsp-armpll
+ - brcm,nsp-genpll
+ - brcm,nsp-lcpll0
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Northstar and
+ Northstar Plus. These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-nsp.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ genpll crystal 0 BCM_NSP_GENPLL
+ phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
+ ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
+ usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
+ iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
+ sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
+ sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
+
+ lcpll0 crystal 0 BCM_NSP_LCPLL0
+ pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
+ sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
+ ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,ns2-genpll-scr
+ - brcm,ns2-genpll-sw
+ - brcm,ns2-lcpll-ddr
+ - brcm,ns2-lcpll-ports
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Northstar 2.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-ns2.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
+ scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
+ fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
+ audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
+ ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
+ ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
+ ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
+
+ genpll_sw crystal 0 BCM_NS2_GENPLL_SW
+ rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
+ 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
+ nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
+ chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
+ port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
+ sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
+
+ lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
+ pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
+ ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
+ ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
+ ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
+ ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
+ ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
+
+ lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
+ wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
+ rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
+ ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
+ ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
+ ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
+ ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,sr-genpll0
+ - brcm,sr-genpll1
+ - brcm,sr-genpll2
+ - brcm,sr-genpll3
+ - brcm,sr-genpll4
+ - brcm,sr-genpll5
+ - brcm,sr-genpll6
+ - brcm,sr-lcpll0
+ - brcm,sr-lcpll1
+ - brcm,sr-lcpll-pcie
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Stingray.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-sr.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+ crmu_ref25m crystal N/A N/A
+
+ genpll0 crystal 0 BCM_SR_GENPLL0
+ clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
+ clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
+ clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
+ clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
+ clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
+ clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
+
+ genpll1 crystal 0 BCM_SR_GENPLL1
+ clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
+ clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
+
+ genpll2 crystal 0 BCM_SR_GENPLL2
+ clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
+ clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
+ clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
+ clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
+ clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
+ clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
+
+ genpll3 crystal 0 BCM_SR_GENPLL3
+ clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
+ clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
+
+ genpll4 crystal 0 BCM_SR_GENPLL4
+ clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
+ clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
+ clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
+ clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
+ clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
+
+ genpll5 crystal 0 BCM_SR_GENPLL5
+ clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
+ clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
+ clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
+
+ genpll6 crystal 0 BCM_SR_GENPLL6
+ clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
+
+ lcpll0 crystal 0 BCM_SR_LCPLL0
+ clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
+ clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
+ clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
+ clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
+
+ lcpll1 crystal 0 BCM_SR_LCPLL1
+ clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
+ clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
+ clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
+
+ lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
+ clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,cygnus-genpll
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: genpll
+ - const: axi21
+ - const: 250mhz
+ - const: ihost_sys
+ - const: enet_sw
+ - const: audio_125
+ - const: can
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nsp-lcpll0
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: lcpll0
+ - const: pcie_phy
+ - const: sdio
+ - const: ddr_phy
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nsp-genpll
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: genpll
+ - const: phy
+ - const: ethernetclk
+ - const: usbclk
+ - const: iprocfast
+ - const: sata1
+ - const: sata2
+
+required:
+ - reg
+ - clocks
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ osc1: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ genpll@301d000 {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x301d000 0x2c>, <0x301c020 0x4>;
+ clocks = <&os1c>;
+ clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+ - |
+ osc2: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ asiu_clks@301d048 {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x301d048 0xc>, <0x180aa024 0x4>;
+ clocks = <&osc2>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
+ };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
deleted file mode 100644
index 9acea9d..0000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra114 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra114-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra114-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra114-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA114_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
deleted file mode 100644
index 7f02fb4..0000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in the header files
- <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
- to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
- (for Tegra124-specific clocks).
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-- nvidia,external-memory-controller : phandle of the EMC driver.
-
-The node should contain a "emc-timings" subnode for each supported RAM type (see
-field RAM_CODE in register PMC_STRAPPING_OPT_A).
-
-Required properties for "emc-timings" nodes :
-- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
- is used for.
-
-Each "emc-timings" node should contain a "timing" subnode for every supported
-EMC clock rate.
-
-Required properties for "timing" nodes :
-- clock-frequency : Should contain the memory clock rate to which this timing
-relates.
-- nvidia,parent-clock-frequency : Should contain the rate at which the current
-parent of the EMC clock should be running at this timing.
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- - emc-parent : the clock that should be the parent of the EMC clock at this
-timing.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock@60006000 {
- compatible = "nvidia,tegra124-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- nvidia,external-memory-controller = <&emc>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA124_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <112400000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-
- clock@60006000 {
- emc-timings-3 {
- nvidia,ram-code = <3>;
-
- timing-12750000 {
- clock-frequency = <12750000>;
- nvidia,parent-clock-frequency = <408000000>;
- clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "emc-parent";
- };
- timing-20400000 {
- clock-frequency = <20400000>;
- nvidia,parent-clock-frequency = <408000000>;
- clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "emc-parent";
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
new file mode 100644
index 0000000..ec7ab14
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Clock and Reset Controller
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The Clock and Reset (CAR) is the HW module responsible for muxing and gating
+ Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
+
+ CLKGEN provides the registers to program the PLLs. It controls most of
+ the clock source programming and most of the clock dividers.
+
+ CLKGEN input signals include the external clock for the reference frequency
+ (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
+
+ Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
+
+ RSTGEN provides the registers needed to control resetting of each block in
+ the Tegra system.
+
+properties:
+ compatible:
+ const: nvidia,tegra124-car
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ nvidia,external-memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle of the external memory controller node
+
+patternProperties:
+ "^emc-timings-[0-9]+$":
+ type: object
+ properties:
+ nvidia,ram-code:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
+ this timing set is used for
+
+ patternProperties:
+ "^timing-[0-9]+$":
+ type: object
+ properties:
+ clock-frequency:
+ description:
+ external memory clock rate in Hz
+ minimum: 1000000
+ maximum: 1000000000
+
+ nvidia,parent-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ rate of parent clock in Hz
+ minimum: 1000000
+ maximum: 1000000000
+
+ clocks:
+ items:
+ - description: parent clock of EMC
+
+ clock-names:
+ items:
+ - const: emc-parent
+
+ required:
+ - clock-frequency
+ - nvidia,parent-clock-frequency
+ - clocks
+ - clock-names
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+
+ car: clock-controller@60006000 {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ usb-controller@c5004000 {
+ compatible = "nvidia,tegra20-ehci";
+ reg = <0xc5004000 0x4000>;
+ clocks = <&car TEGRA124_CLK_USB2>;
+ resets = <&car TEGRA124_CLK_USB2>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
deleted file mode 100644
index 6c5901b..0000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra20 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra20-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra20-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra20-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA20_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
new file mode 100644
index 0000000..459d2a52
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Clock and Reset Controller
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The Clock and Reset (CAR) is the HW module responsible for muxing and gating
+ Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
+
+ CLKGEN provides the registers to program the PLLs. It controls most of
+ the clock source programming and most of the clock dividers.
+
+ CLKGEN input signals include the external clock for the reference frequency
+ (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
+
+ Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
+
+ RSTGEN provides the registers needed to control resetting of each block in
+ the Tegra system.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-car
+ - nvidia,tegra30-car
+ - nvidia,tegra114-car
+ - nvidia,tegra210-car
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+
+ car: clock-controller@60006000 {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ usb-controller@c5004000 {
+ compatible = "nvidia,tegra20-ehci";
+ reg = <0xc5004000 0x4000>;
+ clocks = <&car TEGRA20_CLK_USB2>;
+ resets = <&car TEGRA20_CLK_USB2>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
deleted file mode 100644
index 26f237f..0000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-NVIDIA Tegra210 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra210-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra210-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra210-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA210_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k>;
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
deleted file mode 100644
index 63618cd..0000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra30 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra30-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra30-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra30-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA30_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 96c914e..2015f50 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -73,7 +73,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
- scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
wm8731: wm8731@1a {
compatible = "wm8731";
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 19c7bd48..d3f05d5 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -52,10 +52,11 @@
- description: MAC RX clock
- description: For MPU family, used for power mode
- description: For MPU family, used for PHY without quartz
+ - description: PTP clock
clock-names:
minItems: 3
- maxItems: 5
+ maxItems: 6
contains:
enum:
- stmmaceth
@@ -63,6 +64,7 @@
- mac-clk-rx
- ethstp
- eth-ck
+ - ptp_ref
st,syscon:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index 8c60e69..5ffd0f5 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -42,22 +42,22 @@
Examples:
- cpm_comphy: phy@120000 {
+ CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
- marvell,system-controller = <&cpm_syscon0>;
- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
- <&CP110_LABEL(clk) 1 18>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
+ <&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
- cpm_comphy0: phy@0 {
+ CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- cpm_comphy1: phy@1 {
+ CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
index a96e6db..eb248f2 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
@@ -66,6 +66,16 @@
power-supply: true
+ resets:
+ description: |
+ A number of phandles to resets that need to be asserted during
+ power-up sequencing of the domain. The resets belong to devices
+ located inside the power domain, which need to be held in reset
+ across the power-up sequence. So no means to specify what each
+ reset is in a generic power-domain binding.
+ minItems: 1
+ maxItems: 4
+
required:
- '#power-domain-cells'
- reg
diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
new file mode 100644
index 0000000..84ddc77
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L System Controller (SYSC)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The RZ/G2L System Controller (SYSC) performs system control of the LSI and
+ supports following functions,
+ - External terminal state capture function
+ - 34-bit address space access function
+ - Low power consumption control
+ - WDT stop control
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: CA55/CM33 Sleep/Software Standby Mode request interrupt
+ - description: CA55 Software Standby Mode release request interrupt
+ - description: CM33 Software Standby Mode release request interrupt
+ - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt
+
+ interrupt-names:
+ items:
+ - const: lpm_int
+ - const: ca55stbydone_int
+ - const: cm33stbyr_int
+ - const: ca55_deny
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0x11020000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int",
+ "ca55_deny";
+ };
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 54a7700..800d511 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -25,6 +25,9 @@
- const: allwinner,sun8i-a83t-pwm
- const: allwinner,sun8i-h3-pwm
- items:
+ - const: allwinner,sun8i-v3s-pwm
+ - const: allwinner,sun7i-a20-pwm
+ - items:
- const: allwinner,sun50i-a64-pwm
- const: allwinner,sun5i-a13-pwm
- items:
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
index a16e37b..39b66e9 100644
--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
@@ -20,6 +20,9 @@
- const: allwinner,sun6i-a31-i2s
- const: allwinner,sun8i-a83t-i2s
- const: allwinner,sun8i-h3-i2s
+ - items:
+ - const: allwinner,sun8i-v3-i2s
+ - const: allwinner,sun8i-h3-i2s
- const: allwinner,sun50i-a64-codec-i2s
- items:
- const: allwinner,sun50i-a64-i2s
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
index 9718358..26eca21 100644
--- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
+++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
@@ -12,12 +12,15 @@
properties:
compatible:
- enum:
+ oneOf:
# FIXME: This is documented in the PRCM binding, but needs to be
# migrated here at some point
# - allwinner,sun8i-a23-codec-analog
- - allwinner,sun8i-h3-codec-analog
- - allwinner,sun8i-v3s-codec-analog
+ - const: allwinner,sun8i-h3-codec-analog
+ - items:
+ - const: allwinner,sun8i-v3-codec-analog
+ - const: allwinner,sun8i-h3-codec-analog
+ - const: allwinner,sun8i-v3s-codec-analog
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 1c7cf32..53fd24b 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -12,11 +12,18 @@
properties:
compatible:
- enum:
- - allwinner,sun4i-a10-timer
- - allwinner,sun8i-a23-timer
- - allwinner,sun8i-v3s-timer
- - allwinner,suniv-f1c100s-timer
+ oneOf:
+ - enum:
+ - allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
+ - allwinner,suniv-f1c100s-timer
+ - items:
+ - enum:
+ - allwinner,sun50i-a64-timer
+ - allwinner,sun50i-h6-timer
+ - allwinner,sun50i-h616-timer
+ - const: allwinner,sun8i-a23-timer
reg:
maxItems: 1
@@ -34,8 +41,8 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun4i-a10-timer
+ enum:
+ - allwinner,sun4i-a10-timer
then:
properties:
@@ -46,8 +53,8 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun8i-a23-timer
+ enum:
+ - allwinner,sun8i-a23-timer
then:
properties:
@@ -58,20 +65,9 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun8i-v3s-timer
-
- then:
- properties:
- interrupts:
- minItems: 3
- maxItems: 3
-
- - if:
- properties:
- compatible:
- items:
- const: allwinner,suniv-f1c100s-timer
+ enum:
+ - allwinner,sun8i-v3s-timer
+ - allwinner,suniv-f1c100s-timer
then:
properties:
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 2bbc27a..07fb0d2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -249,6 +249,8 @@
description: Colorful GRP, Shenzhen Xueyushi Technology Ltd.
"^compulab,.*":
description: CompuLab Ltd.
+ "^congatec,.*":
+ description: congatec GmbH
"^coreriver,.*":
description: CORERIVER Semiconductor Co.,Ltd.
"^corpro,.*":
@@ -315,6 +317,8 @@
description: DPTechnics
"^dragino,.*":
description: Dragino Technology Co., Limited
+ "^ds,.*":
+ description: DaSheng, Inc.
"^dserve,.*":
description: dServe Technology B.V.
"^dynaimage,.*":
@@ -409,6 +413,8 @@
description: Firefly
"^focaltech,.*":
description: FocalTech Systems Co.,Ltd
+ "^forlinx,.*":
+ description: Baoding Forlinx Embedded Technology Co., Ltd.
"^frida,.*":
description: Shenzhen Frida LCD Co., Ltd.
"^friendlyarm,.*":
@@ -1252,6 +1258,8 @@
description: Western Digital Corp.
"^we,.*":
description: Würth Elektronik GmbH.
+ "^welltech,.*":
+ description: Welltech Computer Co., Limited.
"^wetek,.*":
description: WeTek Electronics, limited.
"^wexler,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index b0a4a8b..1b012948 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1850,6 +1850,7 @@
F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
+F: arch/arm/boot/dts/gemini*
F: arch/arm/mach-gemini/
F: drivers/crypto/gemini/
F: drivers/net/ethernet/cortina/
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f8f09c5..863347b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -88,6 +88,7 @@
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
+ bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
@@ -240,6 +241,7 @@
integratorcp.dtb
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-linksys-nslu2.dtb \
+ intel-ixp42x-welltech-epbx100.dtb \
intel-ixp43x-gateworks-gw2358.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \
@@ -513,8 +515,14 @@
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-dms-ba16.dtb \
+ imx6q-ds.dtb \
imx6q-emcon-avari.dtb \
imx6q-evi.dtb \
+ imx6dl-b105pv2.dtb \
+ imx6dl-b105v2.dtb \
+ imx6dl-b125v2.dtb \
+ imx6dl-b125pv2.dtb \
+ imx6dl-b155v2.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
imx6q-gw52xx.dtb \
@@ -725,7 +733,8 @@
imx28-m28evk.dtb \
imx28-sps1.dtb \
imx28-ts4600.dtb \
- imx28-tx28.dtb
+ imx28-tx28.dtb \
+ imx28-xea.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += \
ste-nomadik-s8815.dtb \
ste-nomadik-nhk15.dtb
@@ -1234,6 +1243,7 @@
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
+ sun8i-r40-oka40i-c.dtb \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
@@ -1415,6 +1425,7 @@
mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
+ aspeed-ast2600-evb-a1.dtb \
aspeed-ast2600-evb.dtb \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-ampere-mtjade.dtb \
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 3ea2861..1103a2c 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -393,10 +393,10 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
-&gpio3 {
+&gpio3_target {
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 86cad99..8011664 100644
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -101,7 +101,7 @@
};
&gpio3 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 69acaf4..0afcc2e 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -436,7 +436,7 @@
};
&gpio3 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 7615327..74db0fc 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -101,7 +101,7 @@
};
&gpio1 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
output-high;
@@ -118,7 +118,7 @@
/* an external pulldown on U21 pin 4. */
&gpio3 {
- bt_aud_in {
+ bt-aud-in-hog {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-low;
diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index 36d963d..688e14e 100644
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -333,7 +333,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
@@ -496,7 +496,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
/* WLS1271 WiFi */
wlcore: wlcore@1 {
compatible = "ti,wl1271";
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 902e295..9cf39c9 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -495,7 +495,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index d5f8d5e..001657b 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -510,7 +510,7 @@
&epwmss2 {
status = "okay";
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
@@ -646,7 +646,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index e923d06..5e598ac 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -458,14 +458,14 @@
};
&gpio3 {
- p4 {
+ pr1-mii-ctl-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PR1_MII_CTRL";
};
- p10 {
+ mux-mii-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index 4e90f9c..8121a19 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -150,7 +150,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
index 98d8ed4..39e5d2c 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
@@ -353,7 +353,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
index f841afb2..5403e47 100644
--- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
+++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
@@ -25,10 +25,6 @@
regulator-always-on;
};
-&mmc1 {
- vmmc-supply = <&vmmcsd_fixed>;
-};
-
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
pinctrl-names = "default";
@@ -37,68 +33,6 @@
status = "okay";
};
-&am33xx_pinmux {
- nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- >;
- };
-
- nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
- >;
- };
-
- mcasp0_pins: mcasp0-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
- >;
- };
-
- flash_enable: flash-enable {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */
- >;
- };
-
- imu_interrupt: imu-interrupt {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */
- >;
- };
-
- ethernet_interrupt: ethernet-interrupt{
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */
- >;
- };
-};
-
&lcdc {
status = "okay";
@@ -167,10 +101,6 @@
};
};
-&rtc {
- system-power-controller;
-};
-
&mcasp0 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
@@ -267,6 +197,66 @@
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
+ nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ >;
+ };
+
+ nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+ >;
+ };
+
+ mcasp0_pins: mcasp0-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
+ >;
+ };
+
+ flash_enable: flash-enable {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */
+ >;
+ };
+
+ imu_interrupt: imu-interrupt {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */
+ >;
+ };
+
+ ethernet_interrupt: ethernet-interrupt{
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */
+ >;
+ };
+
user_leds_s0: user-leds-s0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
@@ -427,6 +417,7 @@
&mmc1 {
status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
@@ -434,6 +425,7 @@
};
&rtc {
+ system-power-controller;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index 1eaa265..2bfe60d 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -140,14 +140,14 @@
};
&gpio1 {
- hmtc_rst {
+ hmtc-rst-hog {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_reset";
};
- hmtc_prog {
+ hmtc-prog-hog {
gpio-hog;
gpios = <27 GPIO_ACTIVE_LOW>;
output-high;
@@ -156,14 +156,14 @@
};
&gpio3 {
- zgb_rst {
+ zgb-rst-hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_LOW>;
output-low;
line-name = "zigbee_reset";
};
- zgb_boot {
+ zgb-boot-hog {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 039a9ab..859e760 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -1486,7 +1486,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
+ mbox_wkupm3: mbox-wkup-m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
@@ -1789,7 +1789,7 @@
};
};
- target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
+ gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xae000 0x4>,
<0xae010 0x4>,
@@ -1995,15 +1995,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap0: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap0: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <31>;
- interrupt-names = "ecap0";
status = "disabled";
};
@@ -2017,8 +2014,7 @@
};
ehrpwm0: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
@@ -2056,15 +2052,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap1: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap1: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <47>;
- interrupt-names = "ecap1";
status = "disabled";
};
@@ -2078,8 +2071,7 @@
};
ehrpwm1: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
@@ -2117,15 +2109,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap2: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap2: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <61>;
- interrupt-names = "ecap2";
status = "disabled";
};
@@ -2139,8 +2128,7 @@
};
ehrpwm2: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 6e4d05d..e267768 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -786,7 +786,7 @@
pinctrl-0 = <&gpio0_pins>;
status = "okay";
- p23 {
+ sel-emmc-nand-hog {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
/* SelEMMCorNAND selects between eMMC and NAND:
@@ -813,13 +813,16 @@
status = "okay";
};
+&gpio5_target {
+ ti,no-reset-on-init;
+};
+
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
- ti,no-reset-on-init;
- p8 {
+ sel-lcd-hdmi-hog {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index e217ffc..40ef397 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -194,7 +194,7 @@
ranges = <0x0 0x9000 0x1000>;
uart0: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -712,7 +712,7 @@
ranges = <0x0 0x22000 0x1000>;
uart1: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -740,7 +740,7 @@
ranges = <0x0 0x24000 0x1000>;
uart2: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1168,7 +1168,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
+ mbox_wkupm3: mbox-wkup-m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
@@ -1399,7 +1399,7 @@
ranges = <0x0 0xa6000 0x1000>;
uart3: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1427,7 +1427,7 @@
ranges = <0x0 0xa8000 0x1000>;
uart4: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1455,7 +1455,7 @@
ranges = <0x0 0xaa000 0x1000>;
uart5: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1747,10 +1747,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1760,8 +1759,7 @@
ehrpwm0: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
@@ -1799,10 +1797,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap1: ecap@100 {
+ ecap1: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1812,8 +1809,7 @@
ehrpwm1: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
@@ -1851,10 +1847,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1864,8 +1859,7 @@
ehrpwm2: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
@@ -1905,8 +1899,7 @@
ehrpwm3: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
@@ -1946,8 +1939,7 @@
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
@@ -1987,8 +1979,7 @@
ehrpwm5: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
@@ -2070,7 +2061,7 @@
};
};
- target-module@22000 { /* 0x48322000, ap 116 64.0 */
+ gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x22000 0x4>,
<0x22010 0x4>,
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index f517d1e..aae0af1 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -725,7 +725,7 @@
pinctrl-0 = <&display_mux_pins>;
status = "okay";
- p1 {
+ sel-lcd-hdmi-hog {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
@@ -860,7 +860,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_default>;
pinctrl-1 = <&spi0_pins_sleep>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&spi1 {
@@ -868,7 +868,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_default>;
pinctrl-1 = <&spi1_pins_sleep>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&usb2_phy1 {
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 0d5fe2b..aed81568 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -454,20 +454,20 @@
&mailbox5 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
status = "okay";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
status = "okay";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
status = "okay";
};
};
@@ -610,12 +610,11 @@
>;
};
-&gpio3 {
- status = "okay";
+&gpio3_target {
ti,no-reset-on-init;
};
-&gpio2 {
+&gpio2_target {
status = "okay";
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 8bec21e..583a241 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -13,7 +13,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
new file mode 100644
index 0000000..dd71480
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2021 IBM Corp.
+
+#include "aspeed-ast2600-evb.dts"
+
+/ {
+ model = "AST2600 A1 EVB";
+
+ /delete-node/regulator-vcc-sdhci0;
+ /delete-node/regulator-vcc-sdhci1;
+ /delete-node/regulator-vccq-sdhci0;
+ /delete-node/regulator-vccq-sdhci1;
+};
+
+/delete-node/ &sdc;
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 2772796..b7eb552 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "AST2600 EVB";
@@ -21,6 +22,46 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ vcc_sdhci0: regulator-vcc-sdhci0 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHCI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci0: regulator-vccq-sdhci0 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
+
+ vcc_sdhci1: regulator-vcc-sdhci1 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHCI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci1: regulator-vccq-sdhci1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
};
&mdio0 {
@@ -107,7 +148,8 @@
&emmc {
non-removable;
bus-width = <4>;
- max-frequency = <52000000>;
+ max-frequency = <100000000>;
+ clk-phase-mmc-hs200 = <9>, <225>;
};
&rtc {
@@ -121,37 +163,7 @@
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- u-boot@0 {
- reg = <0x0 0xe0000>; // 896KB
- label = "u-boot";
- };
-
- u-boot-env@e0000 {
- reg = <0xe0000 0x20000>; // 128KB
- label = "u-boot-env";
- };
-
- kernel@100000 {
- reg = <0x100000 0x900000>; // 9MB
- label = "kernel";
- };
-
- rofs@a00000 {
- reg = <0xa00000 0x2000000>; // 32MB
- label = "rofs";
- };
-
- rwfs@6000000 {
- reg = <0x2a00000 0x1600000>; // 22MB
- label = "rwfs";
- };
- };
+#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -245,3 +257,46 @@
&uhci {
status = "okay";
};
+
+&sdc {
+ status = "okay";
+};
+
+/*
+ * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
+ * toggled by GPIO pins.
+ * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the
+ * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to
+ * a 1.8v and a 3.3v power load switch that provides signal voltage to
+ * sdhci0 bus.
+ * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled.
+ * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal
+ * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled,
+ * sdhci0 signal voltage becomes 1.8v.
+ * AST2600-A2 EVB also supports toggling signal voltage for sdhci1.
+ * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3
+ * as power-switch-gpio.
+ */
+&sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ sdhci-caps-mask = <0x7 0x0>;
+ sdhci,wp-inverted;
+ vmmc-supply = <&vcc_sdhci0>;
+ vqmmc-supply = <&vccq_sdhci0>;
+ clk-phase-sd-hs = <7>, <200>;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ sdhci-caps-mask = <0x7 0x0>;
+ sdhci,wp-inverted;
+ vmmc-supply = <&vcc_sdhci1>;
+ vqmmc-supply = <&vccq_sdhci1>;
+ clk-phase-sd-hs = <7>, <200>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
index 6aeb47c..79d1784 100644
--- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
@@ -34,7 +34,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
leds {
compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
index 8f5ec22..57b0c45 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
@@ -9,7 +9,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
@@ -110,6 +110,30 @@
linux,code = <ASPEED_GPIO(Q, 5)>;
};
+ psu1_vin_good {
+ label = "PSU1_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 4)>;
+ };
+
+ psu2_vin_good {
+ label = "PSU2_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 5)>;
+ };
+
+ psu1_present {
+ label = "PSU1_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 0)>;
+ };
+
+ psu2_present {
+ label = "PSU2_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 1)>;
+ };
+
};
gpioA0mux: mux-controller {
@@ -280,7 +304,7 @@
m25p,fast-read;
label = "bmc";
/* spi-max-frequency = <50000000>; */
-#include "openbmc-flash-layout.dtsi"
+#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -332,6 +356,16 @@
status = "okay";
};
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
&mac1 {
status = "okay";
pinctrl-names = "default";
@@ -426,6 +460,19 @@
status = "okay";
};
+&i2c10 {
+ status = "okay";
+ adm1278@10 {
+ compatible = "adi,adm1278";
+ reg = <0x10>;
+ };
+
+ adm1278@11 {
+ compatible = "adi,adm1278";
+ reg = <0x11>;
+ };
+};
+
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
@@ -529,8 +576,9 @@
"S1_DDR_SAVE","","",
/*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
"","",
- /*H0-H7*/ "","","","","","","","",
- /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","",
+ /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
+ /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
+ "","","","","",
/*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
"","","","",
/*K0-K7*/ "","","","","","","","",
@@ -540,7 +588,8 @@
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
- /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
+ /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
+ "OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
index c2ece0b..3395de96e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
index 2c29ac0..7c6af7f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index dcab6e7..33e413c 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -15,7 +15,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
index 5ef88c3..01dace8 100644
--- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
@@ -55,7 +55,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
index 2fb8b14..90a3f48 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
@@ -280,7 +280,7 @@
chosen {
stdout-path = &uart1;
- bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
+ bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon";
};
ast-adc-hwmon {
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index 7b4b2b1..b6b1635 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -37,7 +37,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
index 3295c8c..d26a9e1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
@@ -202,6 +202,35 @@
linux,code = <12>;
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* RTC battery fault LED at the back */
+ led-rtc-battery {
+ gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ /* BMC Card fault LED at the back */
+ led-bmc {
+ gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ /* Enclosure Identify LED at the back */
+ led-rear-enc-id0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ /* Enclosure fault LED at the back */
+ led-rear-enc-fault0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ /* PCIE slot power LED */
+ led-pcieslot-power {
+ gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>;
+ };
+ };
};
&gpio0 {
@@ -214,7 +243,7 @@
/*F0-F7*/ "PIN_HOLE_RESET_IN_N","","",
"PIN_HOLE_RESET_OUT_N","","","","",
/*G0-G7*/ "","","","","","","","",
- /*H0-H7*/ "","","","","","","","",
+ /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
@@ -222,7 +251,7 @@
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
- /*P0-P7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","led-pcieslot-power","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","",
/*S0-S7*/ "","","","","","","","",
@@ -353,10 +382,47 @@
&i2c1 {
status = "okay";
+};
- pca2: pca9552@61 {
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps";
+ reg = <0x69>;
+ };
+
+ power-supply@6a {
+ compatible = "ibm,cffps";
+ reg = <0x6a>;
+ };
+
+ power-supply@6b {
+ compatible = "ibm,cffps";
+ reg = <0x6b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ pca2: pca9552@65 {
compatible = "nxp,pca9552";
- reg = <0x61>;
+ reg = <0x65>;
#address-cells = <1>;
#size-cells = <0>;
@@ -424,12 +490,222 @@
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
-
};
- pca3: pca9552@62 {
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+
+ pca_cable_card_c01: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c01-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c01-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+
+ i2c4mux0chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca_cable_card_c02: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c02-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c02-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+
+ i2c4mux0chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ pca_cable_card_c03: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c03-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c03-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ pca3: pca9552@66 {
compatible = "nxp,pca9552";
- reg = <0x62>;
+ reg = <0x66>;
#address-cells = <1>;
#size-cells = <0>;
@@ -512,87 +788,6 @@
};
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-
- eeprom@54 {
- compatible = "atmel,24c128";
- reg = <0x54>;
- };
-
- power-supply@68 {
- compatible = "ibm,cffps";
- reg = <0x68>;
- };
-
- power-supply@69 {
- compatible = "ibm,cffps";
- reg = <0x69>;
- };
-
- power-supply@6a {
- compatible = "ibm,cffps";
- reg = <0x6a>;
- };
-
- power-supply@6b {
- compatible = "ibm,cffps";
- reg = <0x6b>;
- };
-};
-
-&i2c4 {
- status = "okay";
-
- i2c-switch@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- i2c-mux-idle-disconnect;
-
- i2c4mux0chn0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- eeprom@52 {
- compatible = "atmel,24c64";
- reg = <0x52>;
- };
- };
-
- i2c4mux0chn1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- i2c4mux0chn2: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- eeprom@51 {
- compatible = "atmel,24c64";
- reg = <0x51>;
- };
- };
- };
-};
-
-&i2c5 {
- status = "okay";
-
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -609,6 +804,62 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca_cable_card_c04: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c04-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c04-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn1: i2c@1 {
@@ -619,6 +870,62 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
+
+ pca_cable_card_c05: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c05-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c05-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn2: i2c@2 {
@@ -629,6 +936,62 @@
compatible = "atmel,24c64";
reg = <0x52>;
};
+
+ pca_cable_card_c06: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c06-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c06-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn3: i2c@3 {
@@ -639,6 +1002,62 @@
compatible = "atmel,24c64";
reg = <0x53>;
};
+
+ pca_cable_card_c07: pca9551@63 {
+ compatible = "nxp,pca9551";
+ reg = <0x63>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c07-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c07-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
};
};
@@ -659,8 +1078,64 @@
#size-cells = <0>;
reg = <0>;
eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca_cable_card_c08: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c08-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c08-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
};
};
@@ -672,6 +1147,62 @@
compatible = "atmel,24c64";
reg = <0x52>;
};
+
+ pca_cable_card_c09: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c09-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c09-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c6mux0chn2: i2c@2 {
@@ -682,6 +1213,62 @@
compatible = "atmel,24c64";
reg = <0x53>;
};
+
+ pca_cable_card_c10: pca9551@63 {
+ compatible = "nxp,pca9551";
+ reg = <0x63>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c10-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c10-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c6mux0chn3: i2c@3 {
@@ -692,12 +1279,1013 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
+
+ pca_cable_card_c11: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c11-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c11-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+ };
+
+ pca_pcie_slot: pca9552@65 {
+ compatible = "nxp,pca9552";
+ reg = <0x65>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@1 {
+ label = "pcieslot-c01";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "pcieslot-c02";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "pcieslot-c03";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "pcieslot-c04";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "pcieslot-c05";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "pcieslot-c06";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "pcieslot-c07";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "pcieslot-c08";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "pcieslot-c09";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "pcieslot-c10";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "pcieslot-c11";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
};
};
};
&i2c7 {
status = "okay";
+
+ pic0_dimm: pca9552@31 {
+ compatible = "ibm,pca9552";
+ reg = <0x31>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm8";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm9";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm10";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm11";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm12";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm13";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm14";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm15";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic1_dimm: pca9552@32 {
+ compatible = "ibm,pca9552";
+ reg = <0x32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm16";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm17";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm18";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm19";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm20";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm21";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm22";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm23";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm24";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm25";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm26";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm27";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm28";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm29";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm30";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm31";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic2_dimm: pca9552@33 {
+ compatible = "ibm,pca9552";
+ reg = <0x33>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm32";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm33";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm34";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm35";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm36";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm37";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm38";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm39";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm40";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm41";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm42";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm43";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm44";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm45";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm46";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm47";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic3_dimm: pca9552@30 {
+ compatible = "ibm,pca9552";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm48";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm49";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm50";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm51";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm52";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm53";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm54";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm55";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm56";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm57";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm58";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm59";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm60";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm61";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm62";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm63";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic0_vrm_misc: pca9552@34 {
+ compatible = "ibm,pca9552";
+ reg = <0x34>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "planar";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "tpm";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "cpu3-c61";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "cpu0-c14";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "opencapi-connector3";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "opencapi-connector4";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "opencapi-connector5";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@8 {
+ label = "vrm4";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "vrm5";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "vrm6";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "vrm7";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "vrm12";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "vrm13";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "vrm14";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "vrm15";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic1_vrm_misc: pca9552@35 {
+ compatible = "ibm,pca9552";
+ reg = <0x35>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "dasd-backplane";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "power-distribution";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "cpu1-c19";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "cpu2-c56";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "opencapi-connector0";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "opencapi-connector1";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "opencapi-connector2";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@8 {
+ label = "vrm0";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "vrm1";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "vrm2";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "vrm3";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "vrm8";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "vrm9";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "vrm10";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "vrm11";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
&i2c8 {
@@ -863,6 +2451,48 @@
compatible = "atmel,24c32";
reg = <0x50>;
};
+
+ pca_oppanel: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "front-sys-id0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "front-check-log0";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "front-enc-fault1";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "front-sys-pwron0";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
i2c14mux0chn3: i2c@3 {
@@ -901,6 +2531,138 @@
};
};
+ pca_fan_nvme: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "nvme4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "nvme5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "nvme6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "nvme7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "nvme8";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "nvme9";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "fan0";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "fan1";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "fan2";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "fan3";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
pca0: pca9552@61 {
compatible = "nxp,pca9552";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts
index f7fd3b3..342546a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts
@@ -19,33 +19,3 @@
reg = <0x6b>;
};
};
-
-&fan0 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan1 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan2 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan3 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan4 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan5 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
index 0759389..1752f325 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
index 80c92e0..5a98a19 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory {
diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
index 6e9baf3..d5b7d28 100644
--- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
index c29e5f4..8f543cc 100644
--- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -27,7 +27,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
index 084c455..bcc1820 100644
--- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
@@ -27,7 +27,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts
index 7331991..3ef8358 100644
--- a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
index 42b37a2..c0847636 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
index 15c1f0a..a52a289 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
@@ -57,7 +57,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
index 8503152..7d38d12 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
index 91dced7..3d4bdad 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index eb4e93a..cd660c1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index fd2e014..084f548 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -9,7 +9,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
index d56b5ed..4816486 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
index c1478d2..e863ec0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
@@ -13,7 +13,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200n8";
+ bootargs = "console=ttyS4,115200n8 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 01074b6..328ef47 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 85d58a6..230f358 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index 4bcc820..7ae4ea0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -17,7 +17,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
index 03c1614..61bc74b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
@@ -14,7 +14,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
index a68ff06..9605e53 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -28,7 +28,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts
index bc16ad2..50f3c6a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory@80000000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d733c1f..329eaee 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -264,6 +264,7 @@
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
+ syscon = <&syscon>;
status = "disabled";
interrupts = <0x19>;
};
diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index 7028e21..7e90d71 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -862,11 +862,21 @@
groups = "SGPM1";
};
+ pinctrl_sgpm2_default: sgpm2_default {
+ function = "SGPM2";
+ groups = "SGPM2";
+ };
+
pinctrl_sgps1_default: sgps1_default {
function = "SGPS1";
groups = "SGPS1";
};
+ pinctrl_sgps2_default: sgps2_default {
+ function = "SGPS2";
+ groups = "SGPS2";
+ };
+
pinctrl_sioonctrl_default: sioonctrl_default {
function = "SIOONCTRL";
groups = "SIOONCTRL";
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 0025c88..8ecb786 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -460,7 +460,7 @@
status = "disabled";
};
- nand: nand@18046000 {
+ nand_controller: nand-controller@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;
diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi
index e8df458..84cda16 100644
--- a/arch/arm/boot/dts/bcm-hr2.dtsi
+++ b/arch/arm/boot/dts/bcm-hr2.dtsi
@@ -179,7 +179,7 @@
status = "disabled";
};
- nand: nand@26000 {
+ nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x26000 0x600>,
<0x11b408 0x600>,
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b4d2cc7..748df79 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -269,7 +269,7 @@
dma-coherent;
};
- nand: nand@26000 {
+ nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
<0x11b408 0x600>,
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 3b4ab94..f24bdd0 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
-#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
model = "Raspberry Pi 4 Model B";
@@ -15,25 +13,12 @@
stdout-path = "serial1:115200n8";
};
- /* Will be filled by the bootloader */
- memory@0 {
- device_type = "memory";
- reg = <0 0 0>;
- };
-
- aliases {
- emmc2bus = &emmc2bus;
- ethernet0 = &genet;
- pcie0 = &pcie0;
- blconfig = &blconfig;
- };
-
leds {
- act {
+ led-act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
@@ -79,31 +64,15 @@
status = "okay";
};
-&firmware {
- firmware_clocks: clocks {
- compatible = "raspberrypi,firmware-clocks";
- #clock-cells = <1>;
- };
-
- expgpio: gpio {
- compatible = "raspberrypi,firmware-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "BT_ON",
- "WL_ON",
- "PWR_LED_OFF",
- "GLOBAL_RESET",
- "VDD_SD_IO_SEL",
- "CAM_GPIO",
- "SD_PWR_ON",
- "";
- status = "okay";
- };
-
- reset: reset {
- compatible = "raspberrypi,firmware-reset";
- #reset-cells = <1>;
- };
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "";
};
&gpio {
@@ -180,23 +149,13 @@
};
&hdmi0 {
- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
- clock-names = "hdmi", "bvb", "audio", "cec";
- wifi-2.4ghz-coexistence;
status = "okay";
};
&hdmi1 {
- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
- clock-names = "hdmi", "bvb", "audio", "cec";
- wifi-2.4ghz-coexistence;
status = "okay";
};
-&hvs {
- clocks = <&firmware_clocks 4>;
-};
-
&pixelvalve0 {
status = "okay";
};
@@ -219,22 +178,6 @@
status = "okay";
};
-&rmem {
- /*
- * RPi4's co-processor will copy the board's bootloader configuration
- * into memory for the OS to consume. It'll also update this node with
- * its placement information.
- */
- blconfig: nvram@0 {
- compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x0 0x0>;
- no-map;
- status = "disabled";
- };
-};
-
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
@@ -309,10 +252,6 @@
status = "okay";
};
-&vchiq {
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-};
-
&vc4 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts
new file mode 100644
index 0000000..f4d2fc2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711-rpi-4-b.dts"
+
+/ {
+ compatible = "raspberrypi,400", "brcm,bcm2711";
+ model = "Raspberry Pi 400";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ leds {
+ /delete-node/ led-act;
+
+ led-pwr {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "SD_OC_N";
+};
+
+&genet_mdio {
+ clock-frequency = <1950000>;
+};
+
+&pm {
+ /delete-property/ system-power-controller;
+};
diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi
new file mode 100644
index 0000000..ca266c5
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm2835-rpi.dtsi"
+
+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
+
+/ {
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0>;
+ };
+
+ aliases {
+ emmc2bus = &emmc2bus;
+ ethernet0 = &genet;
+ pcie0 = &pcie0;
+ blconfig = &blconfig;
+ };
+};
+
+&firmware {
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+ };
+
+ reset: reset {
+ compatible = "raspberrypi,firmware-reset";
+ #reset-cells = <1>;
+ };
+};
+
+&hdmi0 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hdmi1 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hvs {
+ clocks = <&firmware_clocks 4>;
+};
+
+&rmem {
+ /*
+ * RPi4's co-processor will copy the board's bootloader configuration
+ * into memory for the OS to consume. It'll also update this node with
+ * its placement information.
+ */
+ blconfig: nvram@0 {
+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x0>;
+ no-map;
+ status = "disabled";
+ };
+};
+
+&vchiq {
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 720beec..b8a4096 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -413,7 +413,7 @@
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
- emmc2: emmc2@7e340000 {
+ emmc2: mmc@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
@@ -1087,5 +1087,6 @@
};
&vec {
+ compatible = "brcm,bcm2711-vec";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 6c8ce39..40b9405 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -14,11 +14,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 17fdd48..11edb58 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -14,7 +14,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index b0355c2..1b435c6 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 33b3b5c..a23c25c 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 2b69957..1b63d6b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
index 58059c2..e4e6b6ab 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
@@ -5,7 +5,7 @@
/ {
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index f65448c..33b2b77 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -23,7 +23,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 6dd93c6..6f9b3a9 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -18,7 +18,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index d94357b..87ddcad 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -4,7 +4,7 @@
leds {
compatible = "gpio-leds";
- act {
+ led-act {
label = "ACT";
default-state = "keep";
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index 0455a68..d8af8ee 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
index 28be033..77099a7 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
@@ -19,11 +19,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index 3734314..6101026 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -20,11 +20,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 054ecaa..dd4a486 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -20,7 +20,7 @@
};
leds {
- act {
+ led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
index 925cb37..828a205 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -14,7 +14,7 @@
* Since there is no upstream GPIO driver yet,
* remove the incomplete node.
*/
- /delete-node/ act;
+ /delete-node/ led-act;
};
reg_3v3: fixed-regulator {
diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
index 20322de..e2fd961 100644
--- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "otg";
- g-rx-fifo-size = <558>;
+ g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
/*
* According to dwc2 the sum of all device EP
diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
index 1409d1b..0ff0e9e 100644
--- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "peripheral";
- g-rx-fifo-size = <558>;
+ g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 256 512 512 512 768 768>;
};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index b83a864..0f3be55 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -420,7 +420,7 @@
status = "disabled";
};
- sdhci: sdhci@7e300000 {
+ sdhci: mmc@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index 8636600..c81944c 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -24,8 +24,8 @@
reg = <0x00000000 0x08000000>;
};
- nand: nand@18028000 {
- nandcs@0 {
+ nand_controller: nand-controller@18028000 {
+ nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index e635a15..a6e2aeb 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -25,8 +25,8 @@
<0x88000000 0x08000000>;
};
- nand: nand@18028000 {
- nandcs@0 {
+ nand_controller: nand-controller@18028000 {
+ nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
index 2a8f731..6282363 100644
--- a/arch/arm/boot/dts/bcm47094.dtsi
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -11,7 +11,7 @@
&pinctrl {
compatible = "brcm,bcm4709-pinmux";
- pinmux_mdio: mdio {
+ pinmux_mdio: mdio-pins {
groups = "mdio_grp";
function = "mdio";
};
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
index 925a7c9..be9a00f 100644
--- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
@@ -6,8 +6,8 @@
*/
/ {
- nand@18028000 {
- nandcs: nandcs@0 {
+ nand-controller@18028000 {
+ nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 7db72a2..f920892 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -458,18 +458,18 @@
function = "spi";
};
- pinmux_i2c: i2c {
+ pinmux_i2c: i2c-pins {
groups = "i2c_grp";
function = "i2c";
};
- pinmux_pwm: pwm {
+ pinmux_pwm: pwm-pins {
groups = "pwm0_grp", "pwm1_grp",
"pwm2_grp", "pwm3_grp";
function = "pwm";
};
- pinmux_uart1: uart1 {
+ pinmux_uart1: uart1-pins {
groups = "uart1_grp";
function = "uart1";
};
@@ -501,7 +501,7 @@
reg = <0x18004000 0x14>;
};
- nand: nand@18028000 {
+ nand_controller: nand-controller@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
@@ -520,27 +520,27 @@
<0x1811b408 0x004>,
<0x180293a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "spi_lr_fullness_reached",
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
- "spi_lr_overhead",
- "mspi_done",
- "mspi_halted";
+ "spi_lr_overread";
clocks = <&iprocmed>;
clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
- spi_nor: spi-nor@0 {
+ spi_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 9c0325c..cca49a2 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -203,7 +203,7 @@
status = "disabled";
};
- nand: nand@2000 {
+ nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
index 8313b7c..f92d2cf 100644
--- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
+++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
@@ -14,10 +14,10 @@
};
};
-&nand {
+&nand_controller {
status = "okay";
- nandcs@1 {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <1>;
nand-ecc-step-size = <512>;
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 58f67c9..5ac2042 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -148,7 +148,7 @@
reg-names = "aon-ctrl", "aon-sram";
};
- nand: nand@3e2800 {
+ nand_controller: nand-controller@3e2800 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index b2d323f..a76c74b 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -82,8 +82,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts
index 046c59f..de40bd5 100644
--- a/arch/arm/boot/dts/bcm953012k.dts
+++ b/arch/arm/boot/dts/bcm953012k.dts
@@ -49,8 +49,8 @@
};
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index b4a1392..dda3e11 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -60,8 +60,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 3378683..ea3c6b88 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -68,8 +68,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index 5443fc0..1f73885 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index e1e3c26..b6b9ca8 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index f161ba2..ecf426f 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -90,8 +90,8 @@
};
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 83cb877d..8ca18da 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -78,8 +78,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 4e106ce..9747378d 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -78,8 +78,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index cda6cc2..0f92b77 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -89,8 +89,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index ffbff00..9e984ca 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -68,8 +68,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
index 5b17727..df5c8ab 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -31,10 +31,10 @@
status = "okay";
};
-&nand {
+&nand_controller {
status = "okay";
- nandcs@0 {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index 3fd39c4..5475dab 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 7cf31b6..c3942b4 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -574,8 +574,7 @@
status = "disabled";
};
ehrpwm0: pwm@300000 {
- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
@@ -584,8 +583,7 @@
status = "disabled";
};
ehrpwm1: pwm@302000 {
- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
@@ -593,9 +591,8 @@
power-domains = <&psc1 17>;
status = "disabled";
};
- ecap0: ecap@306000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap0: pwm@306000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
clocks = <&psc1 20>;
@@ -603,9 +600,8 @@
power-domains = <&psc1 20>;
status = "disabled";
};
- ecap1: ecap@307000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap1: pwm@307000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
clocks = <&psc1 20>;
@@ -613,9 +609,8 @@
power-domains = <&psc1 20>;
status = "disabled";
};
- ecap2: ecap@308000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap2: pwm@308000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
clocks = <&psc1 20>;
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 3551a64..a9e7274 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -314,8 +314,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
- dmas = <&edma 58 0 &edma 59 0>;
- dma-names = "tx", "rx";
};
i2c2: i2c@4802a000 {
@@ -325,8 +323,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
- dmas = <&edma 60 0 &edma 61 0>;
- dma-names = "tx", "rx";
};
intc: interrupt-controller@48200000 {
@@ -351,7 +347,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <0 0 0>;
};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 38530db..87deb6a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -319,7 +319,7 @@
};
pcf_lcd: gpio@20 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
@@ -330,7 +330,7 @@
};
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -362,11 +362,11 @@
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi
index a25749a..a5bdc64 100644
--- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi
+++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi
@@ -5,17 +5,17 @@
&mailbox5 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
status = "okay";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 648d23f..956a26d 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -1159,7 +1159,7 @@
ranges = <0x0 0x20000 0x1000>;
uart3: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1343,7 +1343,7 @@
};
};
- target-module@55000 { /* 0x48055000, ap 13 0e.0 */
+ gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55000 0x4>,
<0x55010 0x4>,
@@ -1376,7 +1376,7 @@
};
};
- target-module@57000 { /* 0x48057000, ap 15 06.0 */
+ gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x57000 0x4>,
<0x57010 0x4>,
@@ -1562,7 +1562,7 @@
ranges = <0x0 0x66000 0x1000>;
uart5: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1594,7 +1594,7 @@
ranges = <0x0 0x68000 0x1000>;
uart6: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1626,7 +1626,7 @@
ranges = <0x0 0x6a000 0x1000>;
uart1: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1658,7 +1658,7 @@
ranges = <0x0 0x6c000 0x1000>;
uart2: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1690,7 +1690,7 @@
ranges = <0x0 0x6e000 0x1000>;
uart4: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2424,7 +2424,7 @@
ranges = <0x0 0x20000 0x1000>;
uart7: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2454,7 +2454,7 @@
ranges = <0x0 0x22000 0x1000>;
uart8: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2484,7 +2484,7 @@
ranges = <0x0 0x24000 0x1000>;
uart9: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2561,7 +2561,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -2607,7 +2607,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap1: ecap@100 {
+ ecap1: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -2653,7 +2653,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -4508,7 +4508,7 @@
ranges = <0x0 0xb000 0x1000>;
uart10: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 6d2cca6..a643644 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -187,7 +187,7 @@
};
&pcf_hdmi {
- p0 {
+ hdmi-i2c-disable-hog {
/*
* PM_OEn to High: Disable routing I2C3 to PM_I2C
* With this PM_SEL(p3) should not matter
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index b65b2dd..f128252 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -226,7 +226,7 @@
};
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -256,7 +256,7 @@
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
@@ -268,7 +268,7 @@
*/
lines-initial-states = <0x0f2b>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f3e934e..9061726 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -77,12 +77,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -90,7 +90,7 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi
index b1147a4..3256631 100644
--- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi
+++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi
@@ -6,7 +6,7 @@
#include "dra7-ipu-dsp-common.dtsi"
&mailbox6 {
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index b4e07d9..cfb39dd 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -145,12 +145,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -158,12 +158,12 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 9bd01ae..e2b7fcb 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -158,12 +158,6 @@
regulator-max-microvolt = <1800000>;
};
- clk_ov5640_fixed: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
@@ -355,7 +349,7 @@
};
pcf_lcd: pcf8757@20 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
@@ -366,7 +360,7 @@
};
pcf_gpio_21: pcf8757@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
@@ -377,11 +371,11 @@
};
pcf_hdmi: pcf8575@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -406,27 +400,6 @@
};
};
-&i2c5 {
- status = "okay";
- clock-frequency = <400000>;
-
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
-
- clocks = <&clk_ov5640_fixed>;
- clock-names = "xclk";
-
- port {
- csi2_cam0: endpoint {
- remote-endpoint = <&csi2_phy0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
&cpu0 {
vdd-supply = <&buck10_reg>;
};
@@ -573,14 +546,6 @@
};
};
-&csi2_0 {
- csi2_phy0: endpoint {
- remote-endpoint = <&csi2_cam0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
-};
-
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index c52b9cf..f6ba5e4 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -653,7 +653,7 @@
mmc-pwrseq = <&wlan_pwrseq>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4334-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx1>;
diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts
index 525ff3d2..55922176 100644
--- a/arch/arm/boot/dts/exynos4210-i9100.dts
+++ b/arch/arm/boot/dts/exynos4210-i9100.dts
@@ -314,7 +314,8 @@
};
&fimc_1 {
- status = "okay";
+ /* Back camera not implemented */
+ status = "disabled";
assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
@@ -330,7 +331,8 @@
};
&fimc_3 {
- status = "okay";
+ /* Back camera not implemented */
+ status = "disabled";
assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
@@ -806,7 +808,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index d2406c9..3eb8df3 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -521,7 +521,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index dd44ad2..f0528532 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -614,7 +614,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
index 4583d34..b3726d4 100644
--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -163,6 +163,7 @@
<1025000>, <950000>,
<918750>, <900000>,
<875000>, <831250>;
+ wakeup-source;
regulators {
ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index fc77c1b..968c794 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -668,6 +668,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&max77686_irq>;
pinctrl-names = "default";
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts
index c49dbb7..2c79214 100644
--- a/arch/arm/boot/dts/exynos4412-n710x.dts
+++ b/arch/arm/boot/dts/exynos4412-n710x.dts
@@ -50,8 +50,8 @@
reg = <0x48>;
interrupt-parent = <&gpm2>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- x-size = <720>;
- y-size = <1280>;
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1280>;
avdd-supply = <&ldo23_reg>;
vdd-supply = <&ldo24_reg>;
};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 5bd0586..5b1d459 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -282,6 +282,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index e1f6de5..5479ef0 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -144,6 +144,7 @@
<1200000>, <1200000>,
<1200000>, <1200000>,
<1200000>, <1200000>;
+ wakeup-source;
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi
index 9e75089..22c3086 100644
--- a/arch/arm/boot/dts/exynos4412-p4note.dtsi
+++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi
@@ -325,6 +325,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&max77686_irq>;
pinctrl-names = "default";
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index a161f623..a771542 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -218,6 +218,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s5m8767_irq>;
+ wakeup-source;
vinb1-supply = <&main_dc_reg>;
vinb2-supply = <&main_dc_reg>;
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index 949c072..884fef5 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -190,6 +190,7 @@
pinctrl-names = "default";
pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>,
<&pmic_dvs_3>;
+ wakeup-source;
#clock-cells = <1>;
inl1-supply = <&buck5_reg>;
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 1aad485..dfc7f14 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -352,6 +352,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s2mps11_irq>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index d506da9..a4f0e3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -132,6 +132,7 @@
pmic@66 {
compatible = "samsung,s2mps11-pmic";
reg = <0x66>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6d690b1..e7958db 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -512,6 +512,7 @@
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s2mps11_irq>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
index 20c222b3..d91f7fa 100644
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
@@ -22,7 +22,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index ede7822..1c24f9b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -24,7 +24,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
index 2fc3e86..982752e 100644
--- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
+++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
@@ -22,7 +22,7 @@
* Green LED is much brighter than the others
* so limit its max brightness
*/
- max_brightness = <127>;
+ max-brightness = <127>;
linux,default-trigger = "mmc0";
};
@@ -30,7 +30,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index cc39289..c79a2a0 100644
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -61,9 +61,9 @@
#size-cells = <0>;
/* Collides with IDE pins, that's cool (we do not use them) */
- gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
@@ -169,7 +169,7 @@
* The touchpad input is connected to a GPIO bit-banged
* I2C bus.
*/
- gpio-i2c {
+ i2c {
compatible = "i2c-gpio";
/* Collides with ICE */
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
@@ -492,8 +492,7 @@
display-controller@6a000000 {
status = "okay";
- port@0 {
- reg = <0>;
+ port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
index c6f3d90..eba1c94 100644
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -82,7 +82,7 @@
/* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
- gpio-i2c {
+ i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
@@ -140,7 +140,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
/* Uses MDC and MDIO */
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
index 43c45f7..13112a8 100644
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -62,7 +62,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts
index 9611ddf..0ebda4e 100644
--- a/arch/arm/boot/dts/gemini-rut1xx.dts
+++ b/arch/arm/boot/dts/gemini-rut1xx.dts
@@ -56,7 +56,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
@@ -125,18 +125,6 @@
};
};
- ethernet@60000000 {
- status = "okay";
-
- ethernet-port@0 {
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
- ethernet-port@1 {
- /* Not used in this platform */
- };
- };
-
usb@68000000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts
index a0916d3..c78e55f 100644
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -87,9 +87,9 @@
#address-cells = <1>;
#size-cells = <0>;
/* Check pin collisions */
- gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts
index 0c6e6d3..1b64cc8 100644
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -72,9 +72,9 @@
#address-cells = <1>;
#size-cells = <0>;
/* Check pin collisions */
- gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts
index 3a2761d..5602ba8 100644
--- a/arch/arm/boot/dts/gemini-wbd111.dts
+++ b/arch/arm/boot/dts/gemini-wbd111.dts
@@ -68,7 +68,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts
index 52b4dbc..a4a260c 100644
--- a/arch/arm/boot/dts/gemini-wbd222.dts
+++ b/arch/arm/boot/dts/gemini-wbd222.dts
@@ -67,7 +67,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
index 065ed10..cc053af 100644
--- a/arch/arm/boot/dts/gemini.dtsi
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -191,7 +191,7 @@
};
rtc@45000000 {
- compatible = "cortina,gemini-rtc";
+ compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_RTC>;
@@ -286,6 +286,7 @@
clock-names = "PCLK", "PCICLK";
pinctrl-names = "default";
pinctrl-0 = <&pci_default_pins>;
+ device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -356,6 +357,14 @@
};
};
+ crypto: crypto@62000000 {
+ compatible = "cortina,sl3516-crypto";
+ reg = <0x62000000 0x10000>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_SECURITY>;
+ clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
+ };
+
ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
@@ -409,8 +418,6 @@
clock-names = "PCLK", "TVE";
pinctrl-names = "default";
pinctrl-0 = <&tvc_default_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 905900b..cf48ec1 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. Hi3620 SoC
+ * HiSilicon Ltd. Hi3620 SoC
*
- * Copyright (C) 2012-2013 Hisilicon Ltd.
+ * Copyright (C) 2012-2013 HiSilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
index 0314763..f3faf24 100644
--- a/arch/arm/boot/dts/hip01-ca9x2.dts
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP01 SoC
+ * HiSilicon Ltd. HiP01 SoC
*
- * Copyright (C) 2014 Hisilicon Ltd.
+ * Copyright (C) 2014 HiSilicon Ltd.
* Copyright (C) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
index 2a79636..e17f36b 100644
--- a/arch/arm/boot/dts/hip01.dtsi
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP01 SoC
+ * HiSilicon Ltd. HiP01 SoC
*
- * Copyright (c) 2014 Hisilicon Ltd.
+ * Copyright (c) 2014 HiSilicon Ltd.
* Copyright (c) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index bccf5ba..2424cc5 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP04 SoC
+ * HiSilicon Ltd. HiP04 SoC
*
- * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 HiSilicon Ltd.
* Copyright (C) 2013-2014 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 22b122d..7758c19 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
- * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 HiSilicon Limited.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 9721138..dc991ba 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
- * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 HiSilicon Limited.
*/
#include <dt-bindings/clock/hix5hd2-clock.h>
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index f984b70..908caf8 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -563,15 +563,15 @@
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000
-#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000
+#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000
-#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000
+#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001
-#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000
+#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001
@@ -580,18 +580,18 @@
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000
#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000
-#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000
+#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001
#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001
-#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000
+#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000
#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002
-#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000
+#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000
#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000
diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/imx28-lwe.dtsi
new file mode 100644
index 0000000..bb971e6
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-lwe.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+
+/ {
+ aliases {
+ spi2 = &ssp3;
+ };
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x08000000>;
+ };
+
+ reg_3v3: regulator-reg-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_5v: regulator-reg-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_fec_3v3: regulator-reg-fec-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clks 53>;
+ assigned-clock-rates = <12000000>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&spi3_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a>;
+ bus-width = <8>;
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&ssp3 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "env0";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition@90000 {
+ label = "env1";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "swupdate";
+ reg = <0x500000 0x800000>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_b>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/imx28-xea.dts
new file mode 100644
index 0000000..a400c108
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-xea.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx28-lwe.dtsi"
+
+/ {
+ compatible = "lwn,imx28-xea", "fsl,imx28";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_b>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a &hog_pins_tiva>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__GPIO_0_0
+ MX28_PAD_GPMI_D02__GPIO_0_2
+ MX28_PAD_GPMI_D05__GPIO_0_5
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ MX28_PAD_GPMI_RDY0__GPIO_0_20
+ MX28_PAD_GPMI_RDY1__GPIO_0_21
+ MX28_PAD_GPMI_RDY2__GPIO_0_22
+ MX28_PAD_GPMI_RDN__GPIO_0_24
+ MX28_PAD_GPMI_CLE__GPIO_0_27
+ MX28_PAD_LCD_VSYNC__GPIO_1_28
+ MX28_PAD_SSP1_SCK__GPIO_2_12
+ MX28_PAD_SSP1_CMD__GPIO_2_13
+ MX28_PAD_SSP2_SS1__GPIO_2_20
+ MX28_PAD_SSP2_SS2__GPIO_2_21
+ MX28_PAD_LCD_D00__GPIO_1_0
+ MX28_PAD_LCD_D01__GPIO_1_1
+ MX28_PAD_LCD_D02__GPIO_1_2
+ MX28_PAD_LCD_D03__GPIO_1_3
+ MX28_PAD_LCD_D04__GPIO_1_4
+ MX28_PAD_LCD_D05__GPIO_1_5
+ MX28_PAD_LCD_D06__GPIO_1_6
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ hog_pins_tiva: hog@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY3__GPIO_0_23
+ MX28_PAD_GPMI_WRN__GPIO_0_25
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ hog_pins_coding: hog@2 {
+ reg = <2>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D01__GPIO_0_1
+ MX28_PAD_GPMI_D03__GPIO_0_3
+ MX28_PAD_GPMI_D04__GPIO_0_4
+ MX28_PAD_GPMI_D06__GPIO_0_6
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+®_fec_3v3 {
+ gpio = <&gpio0 0 0>;
+};
+
+®_usb_5v {
+ gpio = <&gpio0 2 0>;
+};
+
+&spi2_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ >;
+};
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 16addb3..7d49704 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -206,7 +206,7 @@
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
- lan9221: lan9221@5,0 {
+ lan9221: ethernet@5,0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lan9221>;
compatible = "smsc,lan9221", "smsc,lan9115";
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 9a2e1fd..6208fbb 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -24,7 +24,7 @@
reg = <0xf4000000 0x3ff0000>;
ranges;
- lan9220@f4000000 {
+ ethernet@f4000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0xf4000000 0x2000000>;
phy-mode = "mii";
diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts
new file mode 100644
index 0000000..411aa72d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B105Pv2";
+ compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts
new file mode 100644
index 0000000..d011127
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b105v2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B105v2";
+ compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts
new file mode 100644
index 0000000..ca840fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B125Pv2";
+ compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h60";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts
new file mode 100644
index 0000000..81e5a9c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b125v2.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B125v2";
+ compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h60";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts
new file mode 100644
index 0000000..c861937
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b155v2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B155v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B155v2";
+ compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g156xtn01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h84";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
new file mode 100644
index 0000000..ec5b664
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5Pv2
+// patient monitor series
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-qmx6.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ /* Do not allow frequencies above 800MHz */
+ cpus {
+ cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+
+ cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+ };
+
+ reg_syspwr: regulator-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ reg_5v_pmc: regulator-5v-pmc {
+ compatible = "regulator-fixed";
+ regulator-name = "5V PMC";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v0_audio: regulator-5v0-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "5V0_AUDIO";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * This must be always-on for da7212, which has some not
+ * properly documented dependencies for it's speaker supply
+ * pin. The issue manifests as speaker volume being very low.
+ */
+ regulator-always-on;
+ };
+
+
+ reg_3v3_audio: regulator-3v3-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+ pinctrl-0 = <&pinctrl_q7_hda_reset>;
+ pinctrl-names = "default";
+ gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_2v5_audio: regulator-2v5-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "2V5_AUDIO";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ vin-supply = <®_3v3_audio>;
+
+ };
+
+ reg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+ regulator-name = "WLAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_sdio_power>;
+ gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <70000>;
+ };
+
+ reg_bl: regulator-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_syspwr>;
+ pinctrl-0 = <&pinctrl_q7_lcd_power>;
+ pinctrl-names = "default";
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ usb_power: regulator-usb-power {
+ compatible = "regulator-fixed";
+ regulator-name = "USB POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ charger: battery-charger {
+ compatible = "gpio-charger"; /* ti,bq24172 */
+ charger-type = "mains";
+ gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>;
+ charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>,
+ <&tca6424a 12 GPIO_ACTIVE_HIGH>;
+ charge-current-limit-mapping = <1300000 0x0>,
+ <700000 0x1>,
+ <0 0x2>;
+ charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_spi_cs1>;
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ };
+
+ power-button-key {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_sleep_button>;
+
+ power-button {
+ label = "power button";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ rotary-encoder-key {
+ compatible = "gpio-keys";
+
+ rotary-encoder-press {
+ label = "rotary-encoder press";
+ gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ linux,can-disable;
+ };
+ };
+
+ rotary-encoder {
+ compatible = "rotary-encoder";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>;
+ gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>;
+ rotary-encoder,relative-axis;
+ rotary-encoder,steps-per-period = <2>;
+ wakeup-source;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
+
+ alarm1 {
+ label = "alarm:red";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm2 {
+ label = "alarm:yellow";
+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm3 {
+ label = "alarm:blue";
+ gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_backlight_enable>;
+ power-supply = <®_bl>;
+ pwms = <&pwm4 0 5000000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <179>;
+ enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel {
+ backlight = <&backlight>;
+ power-supply = <®_lcd>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets = "Speaker", "Ext Spk";
+ simple-audio-card,audio-routing = "Ext Spk", "LINE";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+};
+
+&audmux {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ battery: battery@b {
+ compatible = "ti,bq20z65", "sbs,sbs-battery";
+ reg = <0x0b>;
+ sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>;
+ sbs,i2c-retry-count = <5>;
+ power-supplies = <&charger>;
+ };
+
+ codec: audio-codec@1a {
+ compatible = "dlg,da7212";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <®_2v5_audio>;
+ VDDSP-supply = <®_5v0_audio>;
+ VDDMIC-supply = <®_3v3_audio>;
+ VDDIO-supply = <®_3v3_audio>;
+ clocks = <&clk_ext_audio_codec>;
+ clock-names = "mclk";
+ };
+};
+
+&i2c5 {
+ tca6424a: gpio-controller@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN",
+ "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF",
+ "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0",
+ "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "",
+ "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL",
+ "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2";
+
+ };
+
+ tmp75: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ vs-supply = <®_3v3>;
+ interrupt-parent = <&tca6424a>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ status = "okay";
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&usb_power>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+
+ /*
+ * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N.
+ * On QMX6 this is not connceted to the i.MX6, but to the USB Hub
+ * from &usbh1. This means, that we cannot easily detect and handle
+ * over-current events. Fortunately the regulator limits the current
+ * automatically, so the hardware is still protected.
+ */
+};
+
+&usdhc4 {
+ /* WiFi module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ wakeup-source;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ vmmc-supply = <®_wlan>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio7>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+
+ tcxo-clock-frequency = <26000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
new file mode 100644
index 0000000..a326a33
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5v2
+// patient monitor series
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ reg_3v3_acm: regulator-3v3-acm {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3 ACM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+};
+
+&i2c1 {
+ tca6416: gpio-controller@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_3v3_acm>;
+ gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2",
+ "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1",
+ "ACM2_CL2", "", "", "",
+ "", "", "", "";
+
+ /*
+ * The interrupt pin is connected to &tca6424a pin 1, but the Linux
+ * TCA6424 driver cannot handle low type interrupts at the moment
+ * (and support cannot be added without some ugly hacks). Since this
+ * controller does not have any input type GPIOs, just pretend
+ * that the interrupt pin is unconnected.
+ */
+ };
+};
+
+&i2c5 {
+ mpl3115a2: pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ vcc-supply = <®_3v3_acm>;
+
+ /*
+ * The MPL3115 interrupts are connected to pin 22 and 23
+ * of &tca6424a, but the binding does not yet support
+ * interrupts.
+ */
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts
index 4d0d3d3..60fe5f1 100644
--- a/arch/arm/boot/dts/imx6dl-plym2m.dts
+++ b/arch/arm/boot/dts/imx6dl-plym2m.dts
@@ -138,8 +138,6 @@
interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>;
pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
touchscreen-max-pressure = <4095>;
@@ -147,7 +145,9 @@
ti,vref-delay-usecs = /bits/ 16 <100>;
ti,x-plate-ohms = /bits/ 16 <800>;
ti,y-plate-ohms = /bits/ 16 <300>;
-
+ ti,debounce-max = /bits/ 16 <3>;
+ ti,debounce-tol = /bits/ 16 <70>;
+ ti,debounce-rep = /bits/ 16 <3>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts
index ae6da24..190d266 100644
--- a/arch/arm/boot/dts/imx6dl-prtvt7.dts
+++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts
@@ -21,14 +21,11 @@
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- pwms = <&pwm1 0 500000>;
+ pwms = <&pwm1 0 500000 0>;
brightness-levels = <0 20 81 248 1000>;
default-brightness-level = <20>;
num-interpolated-steps = <21>;
power-supply = <®_bl_12v0>;
- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
keys {
@@ -223,6 +220,24 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
+
+ touchscreen@0 {
+ compatible = "ti,tsc2046";
+ reg = <0>;
+ pinctrl-0 = <&pinctrl_tsc>;
+ pinctrl-names ="default";
+ spi-max-frequency = <100000>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>;
+ pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ touchscreen-max-pressure = <4095>;
+ ti,vref-delay-usecs = /bits/ 16 <100>;
+ ti,x-plate-ohms = /bits/ 16 <800>;
+ ti,y-plate-ohms = /bits/ 16 <300>;
+ ti,debounce-max = /bits/ 16 <3>;
+ ti,debounce-tol = /bits/ 16 <70>;
+ ti,debounce-rep = /bits/ 16 <3>;
+ wakeup-source;
+ };
};
&i2c1 {
@@ -261,7 +276,6 @@
};
&pwm1 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -276,8 +290,6 @@
};
&ssi1 {
- #sound-dai-cells = <0>;
- fsl,mode = "ac97-slave";
status = "okay";
};
@@ -285,10 +297,6 @@
status = "disabled";
};
-&vpu {
- status = "disabled";
-};
-
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
@@ -300,12 +308,6 @@
>;
};
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
- >;
- };
-
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
new file mode 100644
index 0000000..150d6985
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for i.MX6DL based congatec QMX6
+// System on Module
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+// Copyright 2016 congatec AG
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ memory@10000000 {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c2>;
+
+ i2c5: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ audmux_ssi1 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_SYN)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
+ >;
+ };
+
+ audmux_aud6 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT6>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+ >;
+ };
+};
+
+&clks {
+ clocks = <&rtc_sqw>;
+ clock-names = "ckil";
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf032b", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "user";
+ reg = <0x0100000 0x2fc000>;
+ };
+
+ partition@3fc000 {
+ label = "reserved";
+ reg = <0x03fc000 0x4000>;
+ read-only;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@6 {
+ reg = <6>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ rtc: m41t62@68 {
+ compatible = "st,m41t62";
+ reg = <0x68>;
+
+ rtc_sqw: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&i2c6 {
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /*
+ * keep VGEN3, VGEN4 and VGEN5 enabled in order to
+ * maintain backward compatibility with hw-rev. A.0
+ */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* supply voltage for eMMC */
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&pcie {
+ reset-gpio = <&gpio1 20 0>;
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+®_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1c_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbh1 {
+ /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+};
+
+&usdhc2 {
+ /* MicroSD card slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc3 {
+ /* eMMC module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ qmx6mux: imx6qdl-qmx6 {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
+ MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */
+ MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */
+ MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */
+ >;
+ };
+
+ /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
+ pinctrl_enet: enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+ pinctrl_i2c2: i2c2 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_phy_reset: phy-reset {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
+ >;
+ };
+
+ pinctrl_q7_backlight_enable: q7-backlight-enable {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
+ >;
+ };
+
+ pinctrl_q7_gpio0: q7-gpio0 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
+ >;
+ };
+
+ pinctrl_q7_gpio1: q7-gpio1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
+ >;
+ };
+
+ pinctrl_q7_gpio2: q7-gpio2 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
+ >;
+ };
+
+ pinctrl_q7_gpio3: q7-gpio3 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
+ >;
+ };
+
+ pinctrl_q7_gpio4: q7-gpio4 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
+ >;
+ };
+
+ pinctrl_q7_gpio5: q7-gpio5 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
+ >;
+ };
+
+ pinctrl_q7_gpio6: q7-gpio6 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
+ >;
+ };
+
+ pinctrl_q7_gpio7: q7-gpio7 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
+ >;
+ };
+
+ pinctrl_q7_hda_reset: q7-hda-reset {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
+ >;
+ };
+
+ pinctrl_q7_lcd_power: lcd-power {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
+ >;
+ };
+
+ pinctrl_q7_sdio_power: q7-sdio-power {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
+ >;
+ };
+
+ pinctrl_q7_sleep_button: q7-sleep-button {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
+ >;
+ };
+
+ pinctrl_q7_spi_cs1: spi-cs1 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
+ >;
+ };
+
+ /* SPI1 bus does not leave System on Module */
+ pinctrl_spi1: spi1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ /* Debug connector on Q7 module */
+ pinctrl_uart2: uart2 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
+ >;
+ };
+
+ pinctrl_usbotg: usbotg {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
+ >;
+ };
+
+ /* µSD card slot on Q7 module */
+ pinctrl_usdhc2: usdhc2 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
+ >;
+ };
+
+ /* eMMC module on Q7 module */
+ pinctrl_usdhc3: usdhc3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
+ >;
+ };
+
+ pinctrl_wdog: wdog {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 065d3ab..e7d9bfb 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -106,6 +106,8 @@
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
+ qca,smarteee-tw-us-1g = <24>;
+ qca,clk-out-frequency = <125000000>;
};
};
};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
index 9148a01..cb8b539 100644
--- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
+++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
@@ -11,6 +11,8 @@
aliases: aliases {
ethernet1 = ð1;
ethernet2 = ð2;
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc4;
};
backlight: backlight {
@@ -345,6 +347,7 @@
solomon,height = <64>;
solomon,width = <128>;
solomon,page-offset = <0>;
+ solomon,col-offset = <4>;
solomon,prechargep2 = <15>;
reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
vbat-supply = <&sw2_reg>;
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index d0768ae..4bf51f3 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -12,10 +12,20 @@
/ {
aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
mmc0 = &usdhc2;
mmc1 = &usdhc3;
mmc2 = &usdhc4;
mmc3 = &usdhc1;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart5;
+ serial2 = &uart4;
+ serial3 = &uart2;
+ serial4 = &uart3;
};
memory@10000000 {
@@ -23,6 +33,19 @@
reg = <0x10000000 0x40000000>;
};
+ reg_eth_vio: regulator-eth-vio {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_vio";
+ vin-supply = <&sw2_reg>;
+ };
+
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
@@ -96,30 +119,40 @@
reg = <0>;
max-speed = <100>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- reset-post-delay-us = <1000>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
};
};
};
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ltc3676: pmic@3c {
@@ -203,7 +236,7 @@
pagesize = <16>;
};
- rtc@56 {
+ rtc_i2c: rtc@56 {
compatible = "microcrystal,rv3029";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_hw300>;
@@ -260,6 +293,11 @@
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1
+ >;
+ };
+
+ pinctrl_enet_vio: enet-vio-grp {
+ fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
>;
};
@@ -285,6 +323,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -292,6 +337,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -299,6 +351,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
pinctrl_pmic_hw300: pmic-hw300-grp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index fa2307d8..c713ac0 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -112,7 +112,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen2_1v2_eth>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/imx6q-ds.dts
new file mode 100644
index 0000000..b0a63a1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ds.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
+//
+// Based on imx6qdl-sabresd.dtsi which is:
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-ds.dtsi"
+
+/ {
+ model = "DaSheng i.MX6 Quad Com-9xx Board";
+ compatible = "ds,imx6q-sbc", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/imx6qdl-ds.dtsi
new file mode 100644
index 0000000..f7e5175
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-ds.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
+//
+// Based on imx6qdl-sabresd.dtsi which is:
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov2659_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>;
+ status = "okay";
+
+ m25p80: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ reg = <1>;
+ qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ ov2659: camera@30 {
+ compatible = "ovti,ov2659";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov2659>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xvclk";
+ reg = <0x30>;
+ powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ port {
+ ov2659_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ link-frequencies = /bits/ 64 <70000000>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi1_gpio: ecspi1grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmi_cec: hdmicecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov2659: ov2659grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
+ >;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 7bd658b..f323620 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -322,8 +322,8 @@
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
>;
};
@@ -410,6 +410,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f824c9ab..0c01054 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -97,8 +97,11 @@
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
+ audio-asrc = <&asrc>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
@@ -545,6 +548,13 @@
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
index eb25d21..b9e3057 100644
--- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
@@ -40,6 +40,27 @@
};
};
+ counter-0 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter0>;
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-1 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter1>;
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-2 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter2>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -254,7 +275,7 @@
&gpio2 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
+ "count0", "count1", "count2", "", "", "", "", "",
"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
"", "", "", "", "", "", "", "ON_SWITCH",
@@ -572,6 +593,24 @@
>;
};
+ pinctrl_counter0: counter0grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
+ >;
+ };
+
+ pinctrl_counter1: counter1grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
+ >;
+ };
+
+ pinctrl_counter2: counter2grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
index b9b698f..bf86b63 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
@@ -142,7 +142,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 5a1e10d..779cc536 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -60,38 +60,26 @@
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "mx6ul-wm8960";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&dailink_master>;
- simple-audio-card,frame-master = <&dailink_master>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
+ sound-wm8960 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai2>;
+ audio-codec = <&codec>;
+ audio-asrc = <&asrc>;
+ hp-det-gpio = <&gpio5 4 0>;
+ audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "Speaker", "SPK_RP",
- "Speaker", "SPK_RN",
- "LINPUT1", "Mic Jack",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
-
- simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- dailink_master: simple-audio-card,codec {
- sound-dai = <&codec>;
- clocks = <&clks IMX6UL_CLK_SAI2>;
- };
+ "RINPUT1", "AMIC",
+ "RINPUT2", "AMIC",
+ "Mic Jack", "MICB",
+ "AMIC", "MICB";
};
spi4 {
@@ -145,6 +133,10 @@
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
+ wlf,hp-cfg = <3 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
};
camera@3c {
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index ac0751b..4a0d837 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -164,6 +164,13 @@
"LINPUT1", "AMIC",
"AMIC", "MICB";
};
+
+ sound-hdmi {
+ compatible = "fsl,imx-audio-sii902x";
+ model = "sii902x-audio";
+ audio-cpu = <&sai3>;
+ hdmi-out;
+ };
};
&adc1 {
diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
index 8fcd958..5b8dcc1 100644
--- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
@@ -90,20 +90,71 @@
timeout-ms = <5000>;
};
- /* The first 16MB region on the expansion bus */
- flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- bank-width = <2>;
- /*
- * 8 MB of Flash in 0x20000 byte blocks
- * mapped in at 0x50000000
- */
- reg = <0x50000000 0x800000>;
+ gpio-beeper {
+ compatible = "gpio-beeper";
+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ };
- partitions {
- compatible = "redboot-fis";
- /* Eraseblock at 0x7e0000 */
- fis-index-block = <0x3f>;
+ soc {
+ bus@50000000 {
+ /* The first 16MB region at CS0 on the expansion bus */
+ flash@0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 8 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
+ */
+ reg = <0x00000000 0x800000>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x7e0000 */
+ fis-index-block = <0x3f>;
+ };
+ };
+ };
+
+ pci@c0000000 {
+ status = "ok";
+
+ /*
+ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
+ * We have slots (IDSEL) 1, 2 and 3.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
+ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
+ };
+
+ ethernet@c8009000 {
+ status = "ok";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
new file mode 100644
index 0000000..8415850
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+
+/ {
+ model = "Welltech EPBX100";
+ compatible = "welltech,epbx100", "intel,ixp42x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+ /* 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
+ stdout-path = "uart0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ flash@50000000 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 16 MB of Flash
+ */
+ reg = <0x50000000 0x1000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "RedBoot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "zImage";
+ reg = <0x00080000 0x00100000>;
+ read-only;
+ };
+ partition@180000 {
+ label = "ramdisk";
+ reg = <0x00180000 0x00300000>;
+ read-only;
+ };
+ partition@480000 {
+ label = "User";
+ reg = <0x00480000 0x00b60000>;
+ read-only;
+ };
+ partition@fe0000 {
+ label = "FIS directory";
+ reg = <0x00fe0000 0x001f000>;
+ read-only;
+ };
+ partition@fff000 {
+ label = "RedBoot config";
+ reg = <0x00fff000 0x0001000>;
+ read-only;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi
index a9622ca..5fa063e 100644
--- a/arch/arm/boot/dts/intel-ixp42x.dtsi
+++ b/arch/arm/boot/dts/intel-ixp42x.dtsi
@@ -7,6 +7,10 @@
/ {
soc {
+ pci@c0000000 {
+ compatible = "intel,ixp42x-pci";
+ };
+
interrupt-controller@c8003000 {
compatible = "intel,ixp42x-interrupt";
};
diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
index ba1163a..60a1228 100644
--- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
+++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
@@ -76,19 +76,97 @@
};
};
- flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- bank-width = <2>;
- /*
- * 32 MB of Flash in 0x20000 byte blocks
- * mapped in at 0x50000000
- */
- reg = <0x50000000 0x2000000>;
+ soc {
+ bus@50000000 {
+ flash@0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 32 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
+ */
+ reg = <0x00000000 0x2000000>;
- partitions {
- compatible = "redboot-fis";
- /* Eraseblock at 0x1fe0000 */
- fis-index-block = <0xff>;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x1fe0000 */
+ fis-index-block = <0xff>;
+ };
+ };
+ };
+
+ pci@c0000000 {
+ status = "ok";
+
+ /*
+ * In the boardfile for the Cambria from OpenWRT the interrupts
+ * are assigned one per IDSEL, so all 4 interrupts from IDSEL
+ * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
+ * connected to IRQ 10 etc. I find this highly unlikely so I
+ * have instead assumed that they are rotated (swizzled) like
+ * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
+ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
+ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
+ <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
+ /* IDSEL 4 */
+ <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
+ <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
+ /* IDSEL 6 */
+ <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
+ <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
+ <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
+ <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
+ /* IDSEL 15 */
+ <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
+ <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
+ };
+
+ ethernet@c800a000 {
+ status = "ok";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ ethernet@c800c000 {
+ status = "ok";
+ queue-rx = <&qmgr 2>;
+ queue-txready = <&qmgr 19>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+ intel,npe-handle = <&npe 0>;
};
};
};
diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi
index 494fb2f..1d0817c 100644
--- a/arch/arm/boot/dts/intel-ixp43x.dtsi
+++ b/arch/arm/boot/dts/intel-ixp43x.dtsi
@@ -8,6 +8,10 @@
/ {
soc {
+ pci@c0000000 {
+ compatible = "intel,ixp43x-pci";
+ };
+
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};
diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
index f8cd506..cce49e8 100644
--- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
+++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
@@ -30,5 +30,38 @@
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ /* This is known as EthB1 */
+ ethernet@c800d000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800d000 0x1000>;
+ status = "disabled";
+ intel,npe = <1>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB2 */
+ ethernet@c800e000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800e000 0x1000>;
+ status = "disabled";
+ intel,npe = <2>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB3 */
+ ethernet@c800f000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800f000 0x1000>;
+ status = "disabled";
+ intel,npe = <3>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
};
};
diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index d4a0958..a50427a 100644
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -14,12 +14,61 @@
compatible = "simple-bus";
interrupt-parent = <&intcon>;
+ /*
+ * The IXP4xx expansion bus is a set of 16 or 32MB
+ * windows in the 256MB space from 0x50000000 to
+ * 0x5fffffff.
+ */
+ bus@50000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x50000000 0x10000000>;
+ dma-ranges = <0x00000000 0x50000000 0x10000000>;
+ };
+
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
+ pci@c0000000 {
+ /* compatible filled in by per-soc device tree */
+ reg = <0xc0000000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>,
+ <10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ ranges =
+ /*
+ * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
+ * done in 4 chunks of 16MB each.
+ */
+ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
+ /* 64KB I/O space at 0x4c000000 */
+ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
+
+ /*
+ * This needs to map to the start of physical memory so
+ * PCI devices can see all (hopefully) memory. This is done
+ * using 4 1:1 16MB windows, so the RAM should not be more than
+ * 64 MB for this to work. If your memory is anywhere else
+ * than at 0x0 you need to alter this.
+ */
+ dma-ranges =
+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ /* Each unique DTS using PCI must specify the swizzling */
+ };
+
uart0: serial@c8000000 {
compatible = "intel,xscale-uart";
reg = <0xc8000000 0x1000>;
@@ -61,9 +110,50 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
- npe@c8006000 {
+ npe: npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+ /* NPE-C contains a crypto accelerator */
+ crypto {
+ compatible = "intel,ixp4xx-crypto";
+ intel,npe-handle = <&npe 2>;
+ queue-rx = <&qmgr 30>;
+ queue-txready = <&qmgr 29>;
+ };
+ };
+
+ /* This is known as EthB */
+ ethernet@c8009000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc8009000 0x1000>;
+ status = "disabled";
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ intel,npe-handle = <&npe 1>;
+ };
+
+ /* This is known as EthC */
+ ethernet@c800a000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800a000 0x1000>;
+ status = "disabled";
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ intel,npe-handle = <&npe 2>;
+ };
+
+ /* This is known as EthA */
+ ethernet@c800c000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800c000 0x1000>;
+ status = "disabled";
+ intel,npe = <0>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
};
};
};
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 14e26a4..d800f26 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -544,20 +544,15 @@
};
};
-&k2g_clks {
- /* on the board 22.5792MHz is connected to AUDOSC_IN */
- assigned-clocks = <&k2g_clks 0x4c 2>;
- assigned-clock-rates = <22579200>;
-};
-
&mcasp2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcasp2_pins>;
- assigned-clocks = <&k2g_clks 0x6 1>;
- assigned-clock-parents = <&k2g_clks 0x6 2>;
+ assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>;
+ assigned-clock-parents = <0>, <&k2g_clks 0x6 2>;
+ assigned-clock-rates = <22579200>, <0>;
status = "okay";
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 05a7501..3719829 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -242,7 +242,7 @@
status = "disabled";
};
- msgmgr: msgmgr@2a00000 {
+ msgmgr: mailbox@2a00000 {
compatible = "ti,k2g-message-manager";
#mbox-cells = <2>;
reg-names = "queue_proxy_region",
@@ -254,7 +254,7 @@
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
};
- pmmc: pmmc@2921c00 {
+ pmmc: system-controller@2921c00 {
compatible = "ti,k2g-sci";
/*
* In case of rare platforms that does not use k2g as
@@ -272,7 +272,7 @@
#power-domain-cells = <1>;
};
- k2g_clks: clocks {
+ k2g_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 8bae6ed..bd0e864 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,7 @@
compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
reg = <0x84c0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ fifo-size = <128>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 075d583..2273295 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -60,6 +60,14 @@
clock-frequency = <32768>;
status = "disabled";
};
+
+ xtal_div2: xtal_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
soc: soc {
@@ -101,6 +109,12 @@
mask = <0x79>;
};
+ watchdog@6000 {
+ compatible = "mstar,msc313e-wdt";
+ reg = <0x6000 0x1f>;
+ clocks = <&xtal_div2>;
+ };
+
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
reg = <0x201310 0x40>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f9c2a99..5750ca1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -120,8 +120,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
};
i2c2: i2c@48072000 {
@@ -131,8 +129,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
};
mcspi1: spi@48098000 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 494bf69..bb529a2 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -192,16 +192,15 @@
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
- interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_iva: iva {
+ mbox_iva: mbox-iva {
ti,mbox-tx = <2 1 3>;
ti,mbox-rx = <3 1 3>;
};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d19d8ba..23115ba 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -284,7 +284,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
index b4109f4..e6ba30a 100644
--- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
@@ -195,7 +195,7 @@
* for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
*/
&gpio2 {
- en_usb2_port {
+ en-usb2-port-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
output-low;
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
index fd84bbf..9ce8d812 100644
--- a/arch/arm/boot/dts/omap3-gta04a5.dts
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -37,7 +37,7 @@
};
&gpio5 {
- irda_en {
+ irda-en-hog {
gpio-hog;
gpios = <(175-160) GPIO_ACTIVE_HIGH>;
output-high; /* activate gpio_175 to disable IrDA receiver */
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index c5b9da0..64b7e6f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -403,8 +403,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48070000 0x80>;
interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
@@ -414,8 +412,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48072000 0x80>;
interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
@@ -425,8 +421,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48060000 0x80>;
interrupts = <61>;
- dmas = <&sdma 25 &sdma 26>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
@@ -440,7 +434,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index 9972167..46b8f9e 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -600,11 +600,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index d8f1362..45435bb 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -149,7 +149,7 @@
&gpio8 {
/* TI trees use GPIO instead of msecure, see also muxing */
- p234 {
+ msecure-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index b148b28..06cc3a1 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -616,11 +616,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
index 91163867..31f59de 100644
--- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
+++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
@@ -9,27 +9,27 @@
#size-cells = <1>;
u-boot@0 {
- reg = <0x0 0x60000>; // 384KB
+ reg = <0x0 0xe0000>; // 896KB
label = "u-boot";
};
- u-boot-env@60000 {
- reg = <0x60000 0x20000>; // 128KB
+ u-boot-env@e0000 {
+ reg = <0xe0000 0x20000>; // 128KB
label = "u-boot-env";
};
- kernel@80000 {
- reg = <0x80000 0x500000>; // 5MB
+ kernel@100000 {
+ reg = <0x100000 0x900000>; // 9MB
label = "kernel";
};
- rofs@580000 {
- reg = <0x580000 0x2a80000>; // 42.5MB
+ rofs@a00000 {
+ reg = <0xa00000 0x2000000>; // 32MB
label = "rofs";
};
- rwfs@3000000 {
- reg = <0x3000000 0x1000000>; // 16MB
+ rwfs@6000000 {
+ reg = <0x2a00000 0x1600000>; // 22MB
label = "rwfs";
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 282b89c..f7ea2e5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -216,6 +216,10 @@
};
};
+&adm_dma {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
@@ -251,6 +255,39 @@
status = "okay";
};
+&hs_phy_1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ nandcs@0 {
+ compatible = "qcom,nandcs";
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "RouterBoard NAND 1 Boot";
+ reg = <0x0000000 0x0800000>;
+ };
+
+ main@800000 {
+ label = "RouterBoard NAND 1 Main";
+ reg = <0x0800000 0x7800000>;
+ };
+ };
+ };
+};
+
&qcom_pinmux {
buttons_pins: buttons_pins {
mux {
@@ -305,4 +342,25 @@
input-disable;
};
};
+
+ usb1_pwr_en_pins: usb1_pwr_en_pins {
+ mux {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&ss_phy_1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-0 = <&usb1_pwr_en_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 98995ea..7bcf5ef 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
@@ -46,6 +48,228 @@
};
};
+ thermal-zones {
+ tsens_tz_sensor0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor3 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor4 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor5 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor6 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor7 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor8 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor9 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor10 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x0>;
@@ -185,6 +409,31 @@
bias-pull-up;
};
};
+
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
intc: interrupt-controller@2000000 {
@@ -226,6 +475,26 @@
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
};
+ adm_dma: dma-controller@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_PBUS_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
+ qcom,ee = <0>;
+
+ status = "disabled";
+ };
+
saw0: regulator@2089000 {
compatible = "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
@@ -403,6 +672,28 @@
status = "disabled";
};
+ nand: nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
@@ -436,6 +727,12 @@
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ tsens_calib: calib@400 {
+ reg = <0x400 0xb>;
+ };
+ tsens_calib_backup: calib_backup@410 {
+ reg = <0x410 0xb>;
+ };
};
gcc: clock-controller@900000 {
@@ -443,6 +740,38 @@
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
};
tcsr: syscon@1a400000 {
@@ -450,6 +779,14 @@
reg = <0x1a400000 0x100>;
};
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
@@ -718,6 +1055,94 @@
status = "disabled";
};
+ hs_phy_0: phy@100f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ss_phy_0: phy@100f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb3_0: usb3@100f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_0_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ hs_phy_1: phy@110f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ ss_phy_1: phy@110f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_1: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_1_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index dd1b976..a227968 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -47,7 +47,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -56,6 +55,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -77,6 +77,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -98,6 +99,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -119,6 +121,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -750,6 +753,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 6e37b8d..7e5e09d 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -49,7 +49,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -59,6 +58,7 @@
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index ace2086..8419683 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,7 +49,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -59,6 +58,7 @@
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index be33bda..f877c51 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -64,7 +64,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -73,6 +72,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -83,6 +83,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -645,6 +646,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index a1d7f6e..13ef1e9 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -25,7 +25,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -34,6 +33,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -44,6 +44,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -537,6 +538,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index c9f87358..95efbaf 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -166,6 +166,7 @@
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -177,6 +178,7 @@
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -188,6 +190,7 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index d2240b8..4658453 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -145,7 +145,7 @@
status = "okay";
clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
- clock-names = "du", "dclkin.0";
+ clock-names = "du.0", "dclkin.0";
ports {
port@0 {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 74d7e90..39fc58f 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -198,6 +198,7 @@
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -209,6 +210,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -220,6 +222,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -463,6 +466,7 @@
reg = <0xfff80000 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
+ clock-names = "du.0";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 2dad074..fa6d986 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -81,6 +81,9 @@
keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
one {
linux,code = <KEY_1>;
label = "SW2-1";
@@ -659,6 +662,11 @@
groups = "audio_clk_a";
function = "audio_clk";
};
+
+ keyboard_pins: keyboard {
+ pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
+ bias-pull-up;
+ };
};
ðer {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index de29394..ed6dd4f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -69,7 +69,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -78,6 +77,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -99,6 +99,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -120,6 +121,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -141,6 +143,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -162,6 +165,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -173,6 +177,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -184,6 +189,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -195,6 +201,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -768,6 +775,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 61e881b..2a8b6fd 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -81,7 +81,7 @@
keyboard {
compatible = "gpio-keys";
- pinctrl-0 = <&sw2_pins>;
+ pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
@@ -622,7 +622,7 @@
function = "audio_clk";
};
- sw2_pins: sw2 {
+ keyboard_pins: keyboard {
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
bias-pull-up;
};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 9d8320f..0ccc162 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -68,7 +68,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -77,6 +76,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -97,6 +97,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -728,6 +729,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index c100ae9..62aa9f6 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -112,6 +112,9 @@
keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-1 {
linux,code = <KEY_1>;
label = "SW2-1";
@@ -235,6 +238,11 @@
function = "du1";
};
+ keyboard_pins: keyboard {
+ pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
+ bias-pull-up;
+ };
+
pmic_irq_pins: pmicirq {
groups = "intc_irq2";
function = "intc";
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 253e8bf..9cdb738 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -45,7 +45,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -54,6 +53,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@@ -64,6 +64,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@@ -537,6 +538,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 87fa57a..479e0fd 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -64,9 +64,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
- gpio-keys {
+ keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
@@ -567,6 +570,11 @@
function = "audio_clk";
};
+ keyboard_pins: keyboard {
+ pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
+ bias-pull-up;
+ };
+
vin0_pins: vin0 {
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
function = "vin0";
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 6d74475..dea4b1e 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -60,7 +60,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +68,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -89,6 +89,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index f9dba56..f330d79 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Alt";
@@ -94,6 +95,42 @@
#size-cells = <1>;
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
+ one {
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ };
+ two {
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ };
+ three {
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ };
+ four {
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
vga-encoder {
compatible = "adi,adv7123";
@@ -319,6 +356,11 @@
groups = "usb1";
function = "usb1";
};
+
+ keyboard_pins: keyboard {
+ pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
+ bias-pull-up;
+ };
};
&cmt0 {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index eb89a27a..cafa304 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -45,9 +45,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
- gpio-keys {
+ keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-3 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
@@ -358,6 +361,11 @@
function = "du1";
};
+ keyboard_pins: keyboard {
+ pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
+ bias-pull-up;
+ };
+
ssi_pins: sound {
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 330dc51..eac9ed8 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -62,7 +62,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -71,6 +70,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -81,6 +81,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -598,6 +599,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 7154b82..e817eba 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -390,7 +390,7 @@
};
};
- sleep {
+ suspend {
global_pwroff: global-pwroff {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d5..ffa9bc7 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/power/rk3036-power.h>
/ {
#address-cells = <1>;
@@ -111,10 +112,32 @@
assigned-clock-rates = <100000000>;
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3036_PD_GPU>;
resets = <&cru SRST_GPU>;
status = "disabled";
};
+ vpu: video-codec@10108000 {
+ compatible = "rockchip,rk3036-vpu";
+ reg = <0x10108000 0x800>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3036_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@10108800 {
+ compatible = "rockchip,iommu";
+ reg = <0x10108800 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3036_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
@@ -124,6 +147,7 @@
resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
+ power-domains = <&power RK3036_PD_VIO>;
status = "disabled";
vop_out: port {
@@ -140,13 +164,28 @@
compatible = "rockchip,iommu";
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3036_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_vio: qos@1012f000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -302,6 +341,37 @@
compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
+ power: power-controller {
+ compatible = "rockchip,rk3036-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3036_PD_VIO {
+ reg = <RK3036_PD_VIO>;
+ clocks = <&cru ACLK_LCDC>,
+ <&cru HCLK_LCDC>,
+ <&cru SCLK_LCDC>;
+ pm_qos = <&qos_vio>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3036_PD_VPU {
+ reg = <RK3036_PD_VPU>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3036_PD_GPU {
+ reg = <RK3036_PD_GPU>;
+ clocks = <&cru SCLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x1d8>;
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index eba7a13..390aa33 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -12,6 +12,11 @@
model = "bq Curie 2";
compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index 6b12165..a66d915 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -10,6 +10,10 @@
model = "MarsBoard RK3066";
compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index eed9e60..9790bc6 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -10,6 +10,11 @@
model = "Rikomagic MK808";
compatible = "rikomagic,mk808", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 3095184..12b2e59 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -11,6 +11,12 @@
model = "Rayeager PX2";
compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &emmc;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
@@ -58,7 +64,7 @@
};
/* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */
- vcc_stdby: 5v-stdby-regulator {
+ vcc_stdby: stdby-regulator {
compatible = "regulator-fixed";
regulator-name = "5v_stdby";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 252750c..f5a665b 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -217,7 +217,7 @@
<150000000>, <75000000>;
};
- timer@2000e000 {
+ timer2: timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -238,7 +238,7 @@
};
};
- timer@20038000 {
+ timer0: timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
@@ -246,7 +246,7 @@
clock-names = "timer", "pclk";
};
- timer@2003a000 {
+ timer1: timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -266,30 +266,6 @@
status = "disabled";
};
- usbphy: phy {
- compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- usbphy0: usb-phy@17c {
- #phy-cells = <0>;
- reg = <0x17c>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
-
- usbphy1: usb-phy@188 {
- #phy-cells = <0>;
- reg = <0x188>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
- };
-
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
@@ -702,6 +678,34 @@
power-domains = <&power RK3066_PD_GPU>;
};
+&grf {
+ compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3066a-usb-phy",
+ "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@17c {
+ reg = <0x17c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ usbphy1: usb-phy@188 {
+ reg = <0x188>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
@@ -755,7 +759,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3066_PD_VIO {
+ power-domain@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@@ -780,21 +784,24 @@
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3066_PD_VIDEO {
+ power-domain@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
- pd_gpu@RK3066_PD_GPU {
+ power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -861,6 +868,10 @@
pinctrl-0 = <&uart3_xfer>;
};
+&vpu {
+ power-domains = <&power RK3066_PD_VIDEO>;
+};
+
&wdt {
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
index 66a0ff1..85d3fce 100644
--- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts
+++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
@@ -13,6 +13,12 @@
model = "BQ Edison2 Quad-Core";
compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &emmc;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index c32e1d4..39c6042 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -11,6 +11,11 @@
model = "Rockchip PX3-EVB";
compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &emmc;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index b0fef82..36c0945 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -11,6 +11,10 @@
model = "Radxa Rock";
compatible = "radxa,rock", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 2298a8d8..793a1b9 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -150,16 +150,16 @@
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
+ clock-names = "pclk", "timer";
};
timer6: timer@200380a0 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x200380a0 0x20>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
+ clock-names = "pclk", "timer";
};
i2s0: i2s@1011a000 {
@@ -214,30 +214,6 @@
};
};
- usbphy: phy {
- compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- usbphy0: usb-phy@10c {
- #phy-cells = <0>;
- reg = <0x10c>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
-
- usbphy1: usb-phy@11c {
- #phy-cells = <0>;
- reg = <0x11c>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
- };
-
pinctrl: pinctrl {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
@@ -662,6 +638,34 @@
power-domains = <&power RK3188_PD_GPU>;
};
+&grf{
+ compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3188-usb-phy",
+ "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@10c {
+ reg = <0x10c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ usbphy1: usb-phy@11c {
+ reg = <0x11c>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+ };
+};
+
&i2c0 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
@@ -699,7 +703,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3188_PD_VIO {
+ power-domain@RK3188_PD_VIO {
reg = <RK3188_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@@ -719,21 +723,24 @@
<&qos_cif0>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3188_PD_VIDEO {
+ power-domain@RK3188_PD_VIDEO {
reg = <RK3188_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
- pd_gpu@RK3188_PD_GPU {
+ power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -794,6 +801,11 @@
pinctrl-0 = <&uart3_xfer>;
};
+&vpu {
+ compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
+ power-domains = <&power RK3188_PD_VIDEO>;
+};
+
&wdt {
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 208f212..75af99c 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
/ {
#address-cells = <1>;
@@ -190,7 +191,65 @@
status = "disabled";
};
- u2phy0: usb2-phy@760 {
+ power: power-controller {
+ compatible = "rockchip,rk3228-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3228_PD_VIO {
+ reg = <RK3228_PD_VIO>;
+ clocks = <&cru ACLK_HDCP>,
+ <&cru SCLK_HDCP>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_iep>,
+ <&qos_rga_r>,
+ <&qos_rga_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VOP {
+ reg = <RK3228_PD_VOP>;
+ clocks =<&cru ACLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_VOP>;
+ pm_qos = <&qos_vop>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VPU {
+ reg = <RK3228_PD_VPU>;
+ clocks = <&cru ACLK_VPU>,
+ <&cru HCLK_VPU>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_RKVDEC {
+ reg = <RK3228_PD_RKVDEC>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ pm_qos = <&qos_rkvdec_r>,
+ <&qos_rkvdec_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_GPU {
+ reg = <RK3228_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ u2phy0: usb2phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
@@ -217,7 +276,7 @@
};
};
- u2phy1: usb2-phy@800 {
+ u2phy1: usb2phy@800 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0800 0x0c>;
clocks = <&cru SCLK_OTGPHY1>;
@@ -379,7 +438,6 @@
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
@@ -390,7 +448,6 @@
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
@@ -401,7 +458,6 @@
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
@@ -412,7 +468,6 @@
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
@@ -517,7 +572,7 @@
pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_pin>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@@ -550,30 +605,54 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3228_PD_GPU>;
resets = <&cru SRST_GPU_A>;
status = "disabled";
};
+ vpu: video-codec@20020000 {
+ compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
+ reg = <0x20020000 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3228_PD_VPU>;
+ };
+
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
+ vdec: video-codec@20030000 {
+ compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
+ reg = <0x20030000 0x480>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <300000000>, <300000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3228_PD_RKVDEC>;
};
vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ #iommu-cells = <0>;
};
vop: vop@20050000 {
@@ -585,6 +664,7 @@
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
+ power-domains = <&power RK3228_PD_VOP>;
status = "disabled";
vop_out: port {
@@ -602,9 +682,9 @@
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VOP>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -615,6 +695,7 @@
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3228_PD_VIO>;
resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
reset-names = "core", "axi", "ahb";
};
@@ -623,10 +704,10 @@
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
+ power-domains = <&power RK3228_PD_VIO>;
+ #iommu-cells = <0>;
status = "disabled";
};
@@ -800,6 +881,51 @@
status = "disabled";
};
+ qos_iep: qos@31030080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030080 0x20>;
+ };
+
+ qos_rga_w: qos@31030100 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030100 0x20>;
+ };
+
+ qos_hdcp: qos@31030180 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030180 0x20>;
+ };
+
+ qos_rga_r: qos@31030200 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030200 0x20>;
+ };
+
+ qos_vpu: qos@31040000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31040000 0x20>;
+ };
+
+ qos_gpu: qos@31050000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31050000 0x20>;
+ };
+
+ qos_vop: qos@31060000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31060000 0x20>;
+ };
+
+ qos_rkvdec_r: qos@31070000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070000 0x20>;
+ };
+
+ qos_rkvdec_w: qos@31070080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070080 0x20>;
+ };
+
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index 44bb5e6..76363b8 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -218,7 +218,7 @@
flash0-supply = <&vcc_flash>;
flash1-supply = <&vccio_pmu>;
gpio30-supply = <&vccio_pmu>;
- gpio1830 = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index aa50f8e..b156a83 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -379,10 +379,10 @@
audio-supply = <&vcc_18>;
bb-supply = <&vcc_io>;
dvp-supply = <&vcc_io>;
- flash0-suuply = <&vcc_18>;
+ flash0-supply = <&vcc_18>;
flash1-supply = <&vcc_lan>;
gpio30-supply = <&vcc_io>;
- gpio1830 = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 05557ad..9c5a779 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -196,8 +196,8 @@
compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
display-subsystem {
@@ -765,7 +765,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
- pd_vio@RK3288_PD_VIO {
+ power-domain@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@@ -801,19 +801,21 @@
<&qos_vio2_rga_r>,
<&qos_vio2_rga_w>,
<&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
};
/*
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@RK3288_PD_HEVC {
+ power-domain@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>;
+ #power-domain-cells = <0>;
};
/*
@@ -821,22 +823,24 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@RK3288_PD_VIDEO {
+ power-domain@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
};
/*
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@RK3288_PD_GPU {
+ power-domain@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>;
+ #power-domain-cells = <0>;
};
};
@@ -1582,7 +1586,7 @@
drive-strength = <12>;
};
- sleep {
+ suspend {
global_pwroff: global-pwroff {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 755c946..616a828 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -21,9 +21,6 @@
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
- mshc0 = &emmc;
- mshc1 = &mmc0;
- mshc2 = &mmc1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -50,6 +47,18 @@
status = "disabled";
};
+ vpu: video-codec@10104000 {
+ compatible = "rockchip,rk3066-vpu";
+ reg = <0x10104000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
+ clock-names = "aclk_vdpu", "hclk_vdpu",
+ "aclk_vepu", "hclk_vepu";
+ };
+
L2: cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
@@ -256,7 +265,7 @@
};
grf: grf@20008000 {
- compatible = "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x20008000 0x200>;
};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 884872c..9bd0acf 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -265,7 +265,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,rv1108-usb2phy";
reg = <0x100 0x0c>;
clocks = <&cru SCLK_USBPHY>;
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
index 5c1e12d..c6f39147 100644
--- a/arch/arm/boot/dts/s5pv210-goni.dts
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -358,15 +358,6 @@
reg = <0x4a>;
interrupt-parent = <&gpj0>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-
- atmel,x-line = <17>;
- atmel,y-line = <11>;
- atmel,x-size = <800>;
- atmel,y-size = <480>;
- atmel,burst-length = <0x21>;
- atmel,threshold = <0x28>;
- atmel,orientation = <1>;
-
vdd-supply = <&tsp_reg>;
};
};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index e47e1ca..f6e3e6f 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -794,7 +794,7 @@
0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
- 0x0003ff00 0x8002a800 0x00000000 /* pioD */
+ 0xb003ff00 0x8002a800 0x00000000 /* pioD */
0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
>;
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
index 3cc9a239..a61a078 100644
--- a/arch/arm/boot/dts/sd5203.dts
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2020 Hisilicon Limited.
+ * Copyright (c) 2020 HiSilicon Limited.
*
* DTS file for Hisilicon SD5203 Board
*/
diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi
index a16a00f..d0fe3f9 100644
--- a/arch/arm/boot/dts/ste-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-ab8500.dtsi
@@ -34,7 +34,7 @@
#clock-cells = <1>;
};
- ab8500_gpio: ab8500-gpio {
+ ab8500_gpio: ab8500-gpiocontroller {
compatible = "stericsson,ab8500-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -42,15 +42,15 @@
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
- interrupts = <32 IRQ_TYPE_LEVEL_HIGH
- 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
+ <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "HW_CONV_END", "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_tvout_reg>;
#address-cells = <1>;
@@ -219,13 +219,13 @@
ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
@@ -242,8 +242,8 @@
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi
index cc045b2..0defc15 100644
--- a/arch/arm/boot/dts/ste-ab8505.dtsi
+++ b/arch/arm/boot/dts/ste-ab8505.dtsi
@@ -31,7 +31,7 @@
#clock-cells = <1>;
};
- ab8505_gpio: ab8505-gpio {
+ ab8505_gpio: ab8505-gpiocontroller {
compatible = "stericsson,ab8505-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -39,8 +39,8 @@
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
@@ -182,13 +182,13 @@
ab8500_usb: ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
@@ -205,8 +205,8 @@
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 4946743..3ccb7b5 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -9,7 +9,7 @@
soc {
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&gpio2_default_mode>,
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
index 8d59202..37e5940 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
@@ -104,6 +104,9 @@
* <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
* <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
*/
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@1e {
/* Magnetometer */
@@ -136,6 +139,9 @@
/* INT2 would need to be open drain */
interrupts = <18 IRQ_TYPE_EDGE_RISING>,
<19 IRQ_TYPE_EDGE_RISING>;
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@f {
/* Magnetometer */
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
index 70f0583..00ce9d7 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
@@ -89,10 +89,12 @@
<19 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&accel_tvk_mode>;
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@1e {
compatible = "st,lsm303dlm-magn";
- st,drdy-int-pin = <1>;
reg = <0x1e>;
vdd-supply = <&ab8500_ldo_aux1_reg>;
vddio-supply = <&db8500_vsmps2_reg>;
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 13d21619..c97e8d2 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -209,7 +209,7 @@
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
};
ab8500_usb {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index b344b37..40f1d7c 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -376,7 +376,7 @@
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/*
* AB8500 GPIOs are numbered starting from 1, so the first
* index 0 is what in the datasheet is called "GPIO1", and
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
index 0d43ee6..40df7c6 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
@@ -121,7 +121,7 @@
#size-cells = <0>;
wifi@1 {
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 (WLAN_HOST_WAKE) */
@@ -162,6 +162,7 @@
pinctrl-1 = <&u0_a_1_sleep>;
bluetooth {
+ /* BCM4334B0 actually */
compatible = "brcm,bcm4330-bt";
/* GPIO222 (BT_VREG_ON) */
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index f243698..25af066 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
@@ -401,8 +401,7 @@
status = "okay";
wifi@1 {
- /* Actually BRCM4330 */
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 WL_HOST_WAKE */
interrupt-parent = <&gpio6>;
@@ -436,6 +435,7 @@
status = "okay";
bluetooth {
+ /* BCM4330B1 actually */
compatible = "brcm,bcm4330-bt";
/* GPIO222 rail BT_VREG_EN to BT_REG_ON */
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
@@ -583,10 +583,9 @@
accelerometer@08 {
compatible = "bosch,bma222";
reg = <0x08>;
- /* FIXME: no idea about this */
- mount-matrix = "1", "0", "0",
- "0", "1", "0",
- "0", "0", "1";
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V
vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
index d28a007..94afd7a 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
@@ -211,7 +211,7 @@
#size-cells = <0>;
wifi@1 {
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 WL_HOST_WAKE */
interrupt-parent = <&gpio6>;
@@ -247,6 +247,7 @@
/* FIXME: not quite working yet, probably needs regulators */
bluetooth {
+ /* BCM4334B0 actually */
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 7e10ae7..9ac1ffe 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -119,17 +119,15 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 0>;
};
- button@1 {
+ button-1 {
label = "Tamper";
linux,code = <KEY_RESTART>;
gpios = <&gpioc 13 0>;
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index ca8c192..327613f 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -81,12 +81,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 4774163..155d9ff 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -45,7 +45,7 @@
/ {
soc {
- pinctrl: pin-controller {
+ pinctrl: pin-controller@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 3dc068b..075ac57 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -81,12 +81,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 0>;
diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
index 3e7a17d..e10d7a1 100644
--- a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
@@ -42,54 +42,50 @@
#include "stm32f4-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller {
- compatible = "st,stm32f429-pinctrl";
+&pinctrl {
+ compatible = "st,stm32f429-pinctrl";
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 0 160 8>;
};
};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index f6530d7..8748d58 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -283,8 +283,6 @@
};
timers13: timers@40001c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@@ -299,8 +297,6 @@
};
timers14: timers@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@@ -633,8 +629,6 @@
};
timers10: timers@40014400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@@ -649,8 +643,6 @@
};
timers11: timers@40014800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
@@ -709,7 +701,7 @@
status = "disabled";
};
- rcc: rcc@40023810 {
+ rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 2e1b3bb..8c982ae 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -104,12 +104,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
index fff54266..6bf6026 100644
--- a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
@@ -42,55 +42,51 @@
#include "stm32f4-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller {
- compatible = "st,stm32f469-pinctrl";
+&pinctrl {
+ compatible = "st,stm32f469-pinctrl";
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 6>,
+ <&pinctrl 12 156 4>;
+ };
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
- };
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 3 163 5>;
};
};
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
index fe4cfda..1cf8a23 100644
--- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- pinctrl: pin-controller {
+ pinctrl: pin-controller@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index e1df603..014b416 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -265,8 +265,6 @@
};
timers13: timers@40001c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@@ -281,8 +279,6 @@
};
timers14: timers@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@@ -364,9 +360,9 @@
status = "disabled";
};
- i2c3: i2c@40005C00 {
+ i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
- reg = <0x40005C00 0x400>;
+ reg = <0x40005c00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
@@ -531,8 +527,6 @@
};
timers10: timers@40014400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@@ -547,8 +541,6 @@
};
timers11: timers@40014800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 0ce7fbc..be943b7 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -75,12 +75,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 05ecdf9..6e42ca2 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -485,8 +485,6 @@
};
lptimer4: timer@58002c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
@@ -501,8 +499,6 @@
};
lptimer5: timer@58003000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 060baa8..5b60ecb 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -118,6 +118,39 @@
};
};
+ dcmi_pins_b: dcmi-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_b: dcmi-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index fcd3230..bd289bf 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1369,8 +1369,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
- <&mdma1 22 0x2 0x100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+ <&mdma1 22 0x2 0x10100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1416,12 +1416,6 @@
status = "disabled";
};
- stmmac_axi_config_0: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
@@ -1447,6 +1441,12 @@
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
+
+ stmmac_axi_config_0: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
};
usbh_ohci: usb@5800c000 {
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index 674b2d3..5670b23 100644
--- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -89,7 +89,7 @@
};
&pinctrl {
- ltdc_pins: ltdc {
+ ltdc_pins: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
<STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
index 113c48b..a4b14ef 100644
--- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
@@ -184,8 +184,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -208,7 +206,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -219,13 +216,13 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
index 6cf49a0..2d94610 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
@@ -173,8 +173,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -197,7 +195,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -213,7 +210,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -269,7 +266,7 @@
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
mmc-ddr-3_3v;
status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
index a7ffec8..be1dd5e 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
@@ -64,7 +64,7 @@
pinctrl-0 = <&sdmmc1_b4_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
index 5523f41..c5ea08fe 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -34,7 +34,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #size-cells = <0>;
poll-interval = <20>;
/*
@@ -60,7 +59,6 @@
gpio-keys {
compatible = "gpio-keys";
- #size-cells = <0>;
button-1 {
label = "TA2-GPIO-B";
@@ -184,12 +182,11 @@
};
- polytouch@38 {
- compatible = "edt,edt-ft5x06";
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
reg = <0x38>;
interrupt-parent = <&gpiog>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
- linux,wakeup;
};
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
index 272a1a6..2af0a67 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -123,7 +123,6 @@
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
- phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
@@ -132,6 +131,13 @@
phy0: ethernet-phy@1 {
reg = <1>;
+ /* LAN8710Ai */
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
+ clocks = <&rcc ETHCK_K>;
+ reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
interrupt-parent = <&gpioi>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
@@ -144,7 +150,7 @@
pinctrl-1 = <&fmc_sleep_pins_b>;
status = "okay";
- ksz8851: ks8851mll@1,0 {
+ ksz8851: ethernet@1,0 {
compatible = "micrel,ks8851-mll";
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
@@ -327,8 +333,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -350,7 +354,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -366,7 +369,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -431,7 +434,7 @@
#size-cells = <0>;
status = "okay";
- flash0: mx66l51235l@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
index 013ae36..2b0ac60 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -198,7 +198,7 @@
#size-cells = <0>;
status = "okay";
- flash0: spi-flash@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
index 713485a..6706d83 100644
--- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
@@ -146,8 +146,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -171,7 +169,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -182,13 +179,13 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 7344c37..2beddbb 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -198,7 +198,7 @@
};
link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ sound-dai = <&codec 0>;
};
};
@@ -238,7 +238,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
new file mode 100644
index 0000000..265e0fa
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include "sun8i-r40.dtsi"
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+&mmc2 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_aldo2>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <®_dcdc1>;
+ vcc-pc-supply = <®_aldo2>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pf-supply = <®_dldo4>;
+ vcc-pg-supply = <®_dldo1>;
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pa";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
new file mode 100644
index 0000000..0bd1336
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+/dts-v1/;
+#include "sun8i-r40-feta40i.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Forlinx OKA40i-C";
+ compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40";
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5; /* RS485 */
+ serial7 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-5 { /* this is how the leds are labeled on the board */
+ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-6 {
+ gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
+ };
+};
+
+&ahci {
+ ahci-supply = <®_dldo4>;
+ phy-supply = <®_eldo2>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_dcdc1>;
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
+ status = "okay";
+};
+
+&mmc3 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_dc1sw {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-lcd";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pg_pins>;
+ status = "okay";
+};
+
+&uart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pi_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5ad3b9..291f478 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -357,6 +357,8 @@
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC3>;
reset-names = "ahb";
+ pinctrl-0 = <&mmc3_pins>;
+ pinctrl-names = "default";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
@@ -602,6 +604,15 @@
};
/omit-if-no-ref/
+ mmc3_pins: mmc3-pins {
+ pins = "PI4", "PI5", "PI6",
+ "PI7", "PI8", "PI9";
+ function = "mmc3";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
spi0_pc_pins: spi0-pc-pins {
pins = "PC0", "PC1", "PC2";
function = "spi0";
@@ -631,20 +642,65 @@
function = "spi1";
};
+ /omit-if-no-ref/
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
+ /omit-if-no-ref/
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI18", "PI19";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
+ pins = "PI16", "PI17";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
uart3_pg_pins: uart3-pg-pins {
pins = "PG6", "PG7";
function = "uart3";
};
+ /omit-if-no-ref/
uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
pins = "PG8", "PG9";
function = "uart3";
};
+
+ /omit-if-no-ref/
+ uart4_pg_pins: uart4-pg-pins {
+ pins = "PG10", "PG11";
+ function = "uart4";
+ };
+
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH6", "PH7";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
+ uart7_pi_pins: uart7-pi-pins {
+ pins = "PI20", "PI21";
+ function = "uart7";
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
index c279e135..186c30c 100644
--- a/arch/arm/boot/dts/sun8i-v3.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3.dtsi
@@ -1,14 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*/
#include "sun8i-v3s.dtsi"
+/ {
+ soc {
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_pins>;
+ resets = <&ccu RST_BUS_I2S0>;
+ status = "disabled";
+ };
+ };
+};
+
&ccu {
compatible = "allwinner,sun8i-v3-ccu";
};
+&codec_analog {
+ compatible = "allwinner,sun8i-v3-codec-analog",
+ "allwinner,sun8i-h3-codec-analog";
+};
+
&emac {
/delete-property/ phy-handle;
/delete-property/ phy-mode;
@@ -25,6 +51,11 @@
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
+ i2s0_pins: i2s0-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "i2s";
+ };
+
uart1_pg_pins: uart1-pg-pins {
pins = "PG6", "PG7";
function = "uart1";
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index db5cd0b..752ad05 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -49,16 +49,18 @@
compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
"allwinner,sun8i-v3s";
+ aliases {
+ ethernet0 = &emac;
+ };
+
leds {
/* The LEDs use PG0~2 pins, which conflict with MMC1 */
status = "disabled";
};
};
-&mmc1 {
- broken-cd;
- bus-width = <4>;
- vmmc-supply = <®_vcc3v3>;
+&emac {
+ allwinner,leds-active-low;
status = "okay";
};
@@ -94,3 +96,10 @@
voltage = <800000>;
};
};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index eb4cb63..b30bc1a 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -172,6 +173,15 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-v3s-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
@@ -275,6 +285,8 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
@@ -422,6 +434,15 @@
clocks = <&osc24M>;
};
+ pwm: pwm@1c21400 {
+ compatible = "allwinner,sun8i-v3s-pwm",
+ "allwinner,sun7i-a20-pwm";
+ reg = <0x01c21400 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x400>;
@@ -429,6 +450,25 @@
status = "disabled";
};
+ codec: codec@1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3s-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_BUS_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ allwinner,codec-analog-controls = <&codec_analog>;
+ status = "disabled";
+ };
+
+ codec_analog: codec-analog@1c23000 {
+ compatible = "allwinner,sun8i-v3s-codec-analog";
+ reg = <0x01c23000 0x4>;
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -436,6 +476,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -447,6 +489,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -458,6 +502,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
@@ -537,6 +583,8 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 0b678af..8b38f12 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -283,7 +283,7 @@
reg = <0x0 0x60007000 0x0 0x1000>;
};
- actmon@6000c800 {
+ actmon: actmon@6000c800 {
compatible = "nvidia,tegra124-actmon";
reg = <0x0 0x6000c800 0x0 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -295,6 +295,7 @@
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
+ #cooling-cells = <2>;
};
gpio: gpio@6000d000 {
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index 2298fc0..1976c38 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -420,11 +420,14 @@
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
gpio-controller;
#gpio-cells = <2>;
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+
gpio-cfg = <
0x0000 /* MIC_LR_OUT# GPIO, output, low */
0x0000 /* FM2018-enable GPIO, output, low */
@@ -759,7 +762,7 @@
mmc-pwrseq = <&brcm_wifi_pwrseq>;
vmmc-supply = <&vdd_3v3_sys>;
- vqmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8_sys>;
/* Azurewave AW-NH611 BCM4329 */
wifi@1 {
@@ -1030,7 +1033,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
nvidia,headset;
@@ -1056,15 +1059,15 @@
trips {
trip0: cpu-alert0 {
- /* start throttling at 50C */
- temperature = <50000>;
+ /* start throttling at 60C */
+ temperature = <60000>;
hysteresis = <200>;
type = "passive";
};
trip1: cpu-crit {
- /* shut down at 60C */
- temperature = <60000>;
+ /* shut down at 70C */
+ temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
@@ -1085,6 +1088,7 @@
emc-tables@0 {
nvidia,ram-code = <0>; /* elpida-8gb */
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1182,6 +1186,7 @@
emc-tables@1 {
nvidia,ram-code = <1>; /* elpida-4gb */
+ reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1279,6 +1284,7 @@
emc-tables@2 {
nvidia,ram-code = <2>; /* hynix-8gb */
+ reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1376,6 +1382,7 @@
emc-tables@3 {
nvidia,ram-code = <3>; /* hynix-4gb */
+ reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 86494cb..ae4312e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -748,7 +748,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index a348ca3..b31c9bc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -84,7 +84,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 940a9f3..3180bff 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
#include "tegra20.dtsi"
#include "tegra20-cpu-opp.dtsi"
#include "tegra20-cpu-opp-microvolt.dtsi"
@@ -318,6 +320,7 @@
nvidia,ram-code = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0>;
emc-table@166500 {
reg = <166500>;
@@ -497,9 +500,10 @@
};
};
- adt7461@4c {
+ adt7461: temperature-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
+ #thermal-sensor-cells = <1>;
};
};
@@ -654,11 +658,46 @@
cpu0: cpu@0 {
cpu-supply = <&cpu_vdd_reg>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
cpu-supply = <&cpu_vdd_reg>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <500>; /* milliseconds */
+ polling-delay = <1500>; /* milliseconds */
+
+ thermal-sensors = <&adt7461 1>;
+
+ trips {
+ trip0: cpu-alert0 {
+ /* start throttling at 80C */
+ temperature = <80000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: cpu-crit {
+ /* shut down at 85C */
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 378f23b2..5811b70 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -52,7 +52,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index c24d4a3..92d494b 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -911,7 +911,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 44ced60..10ff09d 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -61,7 +61,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 99a356c..5a2578b 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -709,7 +709,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index dc773b1..ae8300b 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -927,7 +927,6 @@
compatible = "ti,bq27541";
reg = <0x55>;
power-supplies = <&power_supply>;
- monitored-battery = <&battery_cell>;
};
power_supply: charger@6a {
@@ -1252,13 +1251,6 @@
};
thermal-zones {
- skin-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <0>; /* milliseconds */
-
- thermal-sensors = <&nct72 0>;
- };
-
cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
@@ -1274,8 +1266,8 @@
};
trip1: cpu-crit {
- /* shut down at 60C */
- temperature = <60000>;
+ /* shut down at 65C */
+ temperature = <65000>;
hysteresis = <2000>;
type = "critical";
};
@@ -1287,7 +1279,9 @@
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
};
};
};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
index 17b6682..53966fa 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
@@ -182,4 +182,13 @@
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
+
+ pmc@7000e400 {
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x3c>;
+ nvidia,reg-addr = <0x41>;
+ nvidia,reg-data = <0xe0>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
index b97da45..9365ae6 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
@@ -144,7 +144,16 @@
};
vdd_3v3_sys: regulator@1 {
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ pmc@7000e400 {
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3f>;
+ nvidia,reg-data = <0x80>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 2dff14b..d9dd115 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -630,7 +630,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts
index 9a10e0d..ab8744f 100644
--- a/arch/arm/boot/dts/tegra30-ouya.dts
+++ b/arch/arm/boot/dts/tegra30-ouya.dts
@@ -463,7 +463,9 @@
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
};
};
};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 44a6dbb..c577c19 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -410,7 +410,7 @@
reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
};
- actmon@6000c800 {
+ actmon: actmon@6000c800 {
compatible = "nvidia,tegra30-actmon";
reg = <0x6000c800 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -422,6 +422,7 @@
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
+ #cooling-cells = <2>;
};
gpio: gpio@6000d000 {
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680..a96d9d2 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -25,6 +25,7 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
index 79adea3..5b44a97 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
@@ -25,6 +25,11 @@
/* Backlight configuration differs per PinePhone revision. */
};
+ bt_sco_codec: bt-sco-codec {
+ #sound-dai-cells = <1>;
+ compatible = "linux,bt-sco";
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -91,6 +96,8 @@
};
&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&aif3_pins>;
status = "okay";
};
@@ -426,6 +433,7 @@
&sound {
status = "okay";
+ simple-audio-card,name = "PinePhone";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
simple-audio-card,widgets = "Microphone", "Headset Microphone",
"Microphone", "Internal Microphone",
@@ -447,6 +455,23 @@
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
"MIC2", "Headset Microphone";
+
+ simple-audio-card,dai-link@2 {
+ format = "dsp_a";
+ frame-master = <&link2_codec>;
+ bitclock-master = <&link2_codec>;
+ bitclock-inversion;
+
+ link2_cpu: cpu {
+ sound-dai = <&bt_sco_codec 0>;
+ };
+
+ link2_codec: codec {
+ sound-dai = <&codec 2>;
+ dai-tdm-slot-num = <1>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
};
&uart0 {
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 5b30e6c..6ddb717 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -131,12 +131,10 @@
};
sound: sound {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-a64-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "DACL",
@@ -145,12 +143,19 @@
"ADCR", "Right ADC";
status = "disabled";
- cpudai: simple-audio-card,cpu {
- sound-dai = <&dai>;
- };
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+ mclk-fs = <128>;
- link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ link0_cpu: cpu {
+ sound-dai = <&dai>;
+ };
+
+ link0_codec: codec {
+ sound-dai = <&codec 0>;
+ };
};
};
@@ -659,6 +664,18 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ aif2_pins: aif2-pins {
+ pins = "PB4", "PB5", "PB6", "PB7";
+ function = "aif2";
+ };
+
+ /omit-if-no-ref/
+ aif3_pins: aif3-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "aif3";
+ };
+
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
@@ -799,6 +816,23 @@
};
};
+ timer@1c20c00 {
+ compatible = "allwinner,sun50i-a64-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun50i-a64-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
@@ -880,7 +914,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
@@ -1325,13 +1359,5 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- wdt0: watchdog@1c20ca0 {
- compatible = "allwinner,sun50i-a64-wdt",
- "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
};
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
new file mode 100644
index 0000000..55bcdf8
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 5081586..30d396e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -271,6 +271,15 @@
};
};
+ timer@3009000 {
+ compatible = "allwinner,sun50i-h6-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x03009000 0xa0>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h6-wdt",
"allwinner,sun6i-a31-wdt";
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index a58ccec..faa0a79 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -48,6 +48,7 @@
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 895c43c..3f5254ee 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1871,6 +1871,7 @@
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 793d48f..00c6f532 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2317,6 +2317,7 @@
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 3d00404..6b457b2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -301,6 +301,7 @@
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
index 66d6752..3cf4ecb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
@@ -171,11 +171,16 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
+ audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
@@ -198,8 +203,20 @@
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
@@ -214,7 +231,7 @@
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
@@ -454,10 +471,26 @@
status = "okay";
};
+&tdmin_a {
+ status = "okay";
+};
+
&tdmout_a {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
new file mode 100644
index 0000000..effaa13
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m5", "amlogic,sm1";
+ model = "Banana Pi BPI-M5";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ key {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* TOFIX: handle CVBS_DET on SARADC channel 0 */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M5";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
+ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "Lineout", "ACODEC LOLP",
+ "Lineout", "ACODEC LORP";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub on the BPI-M5 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
index 06de0b1..f2c0981 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
@@ -32,6 +32,19 @@
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ model = "G12B-KHADAS-VIM3L";
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 13", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
+ };
};
&cpu0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
index 8c327c0..8c30ce6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
@@ -23,18 +23,6 @@
};
};
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
model = "ODROID-C4";
};
@@ -58,8 +46,3 @@
&ir {
linux,rc-map-name = "rc-odroid";
};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
index bf15700..f3f9532 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
@@ -44,6 +44,32 @@
};
};
+ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
+ p12v_0: regulator-p12v_0 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
+ p12v_1: regulator-p12v_1 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
sound {
model = "ODROID-HC4";
};
@@ -90,7 +116,25 @@
status = "disabled";
};
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+};
+
+&usb2_phy0 {
+ status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
index d14716b..fd0ad85 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
@@ -46,8 +46,13 @@
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
gpios-states = <0>;
states = <3300000 0>,
@@ -78,6 +83,8 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index c309517..3d8b1f4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -401,6 +401,16 @@
status = "disabled";
};
+ toacodec: audio-controller@740 {
+ compatible = "amlogic,sm1-toacodec",
+ "amlogic,g12a-toacodec";
+ reg = <0x0 0x740 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOACODEC";
+ resets = <&clkc_audio AUD_RESET_TOACODEC>;
+ status = "disabled";
+ };
+
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 1cc7fdc..8e7a669 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -568,13 +568,13 @@
clocks {
compatible = "arm,scpi-clocks";
- scpi_dvfs: scpi-dvfs {
+ scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
};
- scpi_clk: scpi-clk {
+ scpi_clk: clocks-1 {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>;
@@ -582,7 +582,7 @@
};
};
- scpi_devpd: scpi-power-domains {
+ scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index 998e240..11eae3e 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
+ bcm2711-rpi-4-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts
new file mode 100644
index 0000000..b9000f5
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "arm/bcm2711-rpi-400.dts"
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
index 8060178..a5a64d1 100644
--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
@@ -306,7 +306,7 @@
interrupt-names = "nand";
status = "okay";
- nandcs: nandcs@0 {
+ nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 2ffb2c9..7b04dfe 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -470,7 +470,7 @@
status = "disabled";
};
- uart0: uart@100000 {
+ uart0: serial@100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
@@ -481,7 +481,7 @@
status = "disabled";
};
- uart1: uart@110000 {
+ uart1: serial@110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
@@ -492,7 +492,7 @@
status = "disabled";
};
- uart2: uart@120000 {
+ uart2: serial@120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
@@ -503,7 +503,7 @@
status = "disabled";
};
- uart3: uart@130000 {
+ uart3: serial@130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 773d9ab..cbcc01a6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -391,6 +391,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
reg = <0x66>;
samsung,s2mps11-wrstbi-ground;
+ wakeup-source;
s2mps13_osc: clocks {
compatible = "samsung,s2mps13-clk";
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 44890d5..25806c4 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -41,6 +41,7 @@
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
index 6290e2f..e856258 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -24,6 +24,10 @@
status = "okay";
};
+&pcie1 {
+ status = "okay";
+};
+
&qspi {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 9058cfa..50a72cd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -238,35 +238,35 @@
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x60000 0x100 0x60e00 0x18>;
+ reg = <0x60000 0x100>, <0x60e00 0x18>;
ranges = <0x0 0x60100 0x500>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x00 0x20 0x100 0x100>;
+ reg = <0x00 0x20>, <0x100 0x100>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x20 0x20 0x200 0x100>;
+ reg = <0x20 0x20>, <0x200 0x100>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x40 0x20 0x300 0x100>;
+ reg = <0x40 0x20>, <0x300 0x100>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x60 0x20 0x400 0x100>;
+ reg = <0x60 0x20>, <0x400 0x100>;
};
};
};
@@ -522,8 +522,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1012a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9322c6a..d7b5272 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -275,6 +275,10 @@
status = "okay";
};
+&optee {
+ status = "okay";
+};
+
&sai4 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index a30249e..b2e3e5d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -88,7 +88,7 @@
};
firmware {
- optee {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
@@ -617,8 +617,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
@@ -644,8 +644,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,19 +990,19 @@
msi-map = <0 &its 0x17 0xe>;
iommu-map = <0 &smmu 0x17 0xe>;
/* PF0-6 BAR0 - non-prefetchable memory */
- ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
+ ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
/* PF0-6 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
+ 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
/* PF0: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
+ 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
/* PF0: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
+ 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
+ 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
/* PF1: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
+ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
+ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 28c51e5..01b01e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -869,8 +869,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
@@ -895,8 +895,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 128 0x4>,
<0 127 0x4>;
@@ -921,8 +921,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 162 0x4>,
<0 161 0x4>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3945830..687fea6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -773,8 +773,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -799,8 +799,8 @@
pcie_ep1: pcie_ep@3400000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x40 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -809,8 +809,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -835,8 +835,8 @@
pcie_ep2: pcie_ep@3500000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x48 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -845,8 +845,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -871,8 +871,8 @@
pcie_ep3: pcie_ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x50 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 8ffbc9f..2fa6cfb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -536,8 +536,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -562,8 +562,8 @@
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x20 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <24>;
num-ob-windows = <256>;
@@ -573,8 +573,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -599,8 +599,8 @@
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x28 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
@@ -609,8 +609,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -635,8 +635,8 @@
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x30 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 76ab68d..6f6667b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -120,32 +120,32 @@
};
&pcie1 {
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie2 {
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie3 {
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie4 {
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index da24dc1..c3dc381 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -121,8 +121,8 @@
&pcie1 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
@@ -130,8 +130,8 @@
&pcie2 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
@@ -139,8 +139,8 @@
&pcie3 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
@@ -148,8 +148,8 @@
&pcie4 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x38 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 135ac82..801ba96 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -929,7 +929,6 @@
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "dspi";
spi-num-chipselects = <5>;
- bus-num = <0>;
};
esdhc: esdhc@2140000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 0551f6f..c4b1a59 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1089,8 +1089,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1117,8 +1117,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1145,8 +1145,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1173,8 +1173,8 @@
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1201,8 +1201,8 @@
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
+ <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1229,8 +1229,8 @@
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
+ <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e1e81ca..a79f42a96 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -77,9 +77,12 @@
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&enet0_lpcg IMX_LPCG_CLK_2>,
- <&enet0_lpcg IMX_LPCG_CLK_1>,
+ <&enet0_lpcg IMX_LPCG_CLK_3>,
<&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
@@ -94,9 +97,12 @@
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&enet1_lpcg IMX_LPCG_CLK_2>,
- <&enet1_lpcg IMX_LPCG_CLK_1>,
+ <&enet1_lpcg IMX_LPCG_CLK_3>,
<&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
@@ -152,15 +158,19 @@
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet0_ipg_root_clk",
- "enet0_tx_clk",
- "enet0_ahb_clk",
- "enet0_ipg_clk",
- "enet0_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet0_lpcg_timer_clk",
+ "enet0_lpcg_txc_sampling_clk",
+ "enet0_lpcg_ahb_clk",
+ "enet0_lpcg_rgmii_txc_clk",
+ "enet0_lpcg_ipg_clk",
+ "enet0_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_0>;
};
@@ -170,15 +180,19 @@
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet1_ipg_root_clk",
- "enet1_tx_clk",
- "enet1_ahb_clk",
- "enet1_ipg_clk",
- "enet1_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet1_lpcg_timer_clk",
+ "enet1_lpcg_txc_sampling_clk",
+ "enet1_lpcg_ahb_clk",
+ "enet1_lpcg_rgmii_txc_clk",
+ "enet1_lpcg_ipg_clk",
+ "enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 6518f08..e033d025 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -314,6 +314,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
new file mode 100644
index 0000000..5a1e9df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -0,0 +1,1019 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7901 i.MX8MM board";
+ compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
+ ethernet3 = &lan3;
+ ethernet4 = &lan4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led01_red";
+ gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led02_red";
+ gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led03_red";
+ gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led04_red";
+ gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led05_red";
+ gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-a {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator-ioexp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_ioexp>;
+ compatible = "regulator-fixed";
+ regulator-name = "ioexp";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator-isouart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_isouart>;
+ compatible = "regulator-fixed";
+ regulator-name = "iso_uart";
+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_usb2_vbus";
+ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ status = "okay";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin_aux1";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vin_aux2";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_0p95";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_soc";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_arm";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p8";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p2";
+ };
+
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ leds_gpio: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ switch: switch@5f {
+ compatible = "microchip,ksz9897";
+ reg = <0x5f>;
+ pinctrl-0 = <&pinctrl_ksz>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ phy-mode = "rgmii-id";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1: port@0 {
+ reg = <0>;
+ label = "lan1";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan2: port@1 {
+ reg = <1>;
+ label = "lan2";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan3: port@2 {
+ reg = <2>;
+ label = "lan3";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan4: port@3 {
+ reg = <3>;
+ label = "lan4";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ crypto@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
+ cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_ksz: kszgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
+ >;
+ };
+
+ pinctrl_reg_isouart: regisouartgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
+ >;
+ };
+
+ pinctrl_reg_ioexp: regioexpgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
+ >;
+ };
+
+ pinctrl_reg_usb2: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41
+ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
+ >;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
+ >;
+ };
+
+ pinctrl_uart4_gpio: uart4gpiogrp {
+ fsl,pins = <
+
+ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02b..e7648c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -261,6 +261,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mm_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -271,117 +272,125 @@
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
- sai1: sai@30010000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30010000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
- <&clk IMX8MM_CLK_SAI1_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ spba2: spba-bus@30000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x100000>;
+ ranges;
- sai2: sai@30020000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30020000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
- <&clk IMX8MM_CLK_SAI2_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai1: sai@30010000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30010000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
+ <&clk IMX8MM_CLK_SAI1_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai3: sai@30030000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30030000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
- <&clk IMX8MM_CLK_SAI3_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai2: sai@30020000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30020000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
+ <&clk IMX8MM_CLK_SAI2_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai5: sai@30050000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30050000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
- <&clk IMX8MM_CLK_SAI5_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai3: sai@30030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30030000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
+ <&clk IMX8MM_CLK_SAI3_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai6: sai@30060000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30060000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
- <&clk IMX8MM_CLK_SAI6_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai5: sai@30050000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30050000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+ <&clk IMX8MM_CLK_SAI5_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- micfil: audio-controller@30080000 {
- compatible = "fsl,imx8mm-micfil";
- reg = <0x30080000 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_PDM_IPG>,
- <&clk IMX8MM_CLK_PDM_ROOT>,
- <&clk IMX8MM_AUDIO_PLL1_OUT>,
- <&clk IMX8MM_AUDIO_PLL2_OUT>,
- <&clk IMX8MM_CLK_EXT3>;
- clock-names = "ipg_clk", "ipg_clk_app",
- "pll8k", "pll11k", "clkext3";
- dmas = <&sdma2 24 25 0x80000000>;
- dma-names = "rx";
- status = "disabled";
- };
+ sai6: sai@30060000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30060000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
+ <&clk IMX8MM_CLK_SAI6_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- spdif1: spdif@30090000 {
- compatible = "fsl,imx35-spdif";
- reg = <0x30090000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
- <&clk IMX8MM_CLK_24M>, /* rxtx0 */
- <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
- <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
- <&clk IMX8MM_CLK_DUMMY>; /* spba */
- clock-names = "core", "rxtx0",
- "rxtx1", "rxtx2",
- "rxtx3", "rxtx4",
- "rxtx5", "rxtx6",
- "rxtx7", "spba";
- dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
- dma-names = "rx", "tx";
- status = "disabled";
+ micfil: audio-controller@30080000 {
+ compatible = "fsl,imx8mm-micfil";
+ reg = <0x30080000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PDM_IPG>,
+ <&clk IMX8MM_CLK_PDM_ROOT>,
+ <&clk IMX8MM_AUDIO_PLL1_OUT>,
+ <&clk IMX8MM_AUDIO_PLL2_OUT>,
+ <&clk IMX8MM_CLK_EXT3>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "pll11k", "clkext3";
+ dmas = <&sdma2 24 25 0x80000000>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ spdif1: spdif@30090000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x30090000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */
+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MM_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
};
gpio1: gpio@30200000 {
@@ -670,80 +679,88 @@
ranges = <0x30800000 0x30800000 0x400000>,
<0x8000000 0x8000000 0x10000000>;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
- <&clk IMX8MM_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
- <&clk IMX8MM_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
- <&clk IMX8MM_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
- <&clk IMX8MM_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
- <&clk IMX8MM_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+ <&clk IMX8MM_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
- <&clk IMX8MM_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+ <&clk IMX8MM_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+ <&clk IMX8MM_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index c35eeaf..54eaf3d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
@@ -120,6 +120,9 @@
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index a0dddba..85e65f8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -193,6 +193,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 4dac4da..d4231e0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -245,6 +245,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -255,7 +256,7 @@
#size-cells = <1>;
ranges;
- spba: spba-bus@30000000 {
+ spba2: spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -681,80 +682,88 @@
#size-cells = <1>;
ranges;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
- <&clk IMX8MN_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
- <&clk IMX8MN_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
- <&clk IMX8MN_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
- <&clk IMX8MN_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
- <&clk IMX8MN_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+ <&clk IMX8MN_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
- <&clk IMX8MN_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+ <&clk IMX8MN_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+ <&clk IMX8MN_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 2c28e58..7b99fad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -81,6 +81,26 @@
status = "disabled";/* can2 pin conflict with pdm */
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
@@ -104,6 +124,92 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1045000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -177,6 +283,26 @@
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
@@ -229,6 +355,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
@@ -236,6 +369,12 @@
>;
};
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index f3965ec..aa78e0d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -65,6 +65,20 @@
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ som_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -217,6 +231,17 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c2d51a4..9f7c7f5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -37,6 +37,7 @@
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
+ spi0 = &flexspi;
};
cpus {
@@ -407,7 +408,6 @@
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
- <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
@@ -423,7 +423,6 @@
<500000000>,
<400000000>,
<800000000>,
- <400000000>,
<393216000>,
<361267200>;
};
@@ -761,6 +760,21 @@
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ compatible = "nxp,imx8mp-fspi";
+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+ <&clk IMX8MP_CLK_QSPI_ROOT>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 85b0452..4d2035e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ vph-supply = <&vgen5_reg>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
index 81d2692..f70fb32 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
@@ -34,6 +34,30 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ ddc-i2c-bus = <&ddc_i2c_bus>;
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
@@ -70,6 +94,9 @@
};
};
+&dphy {
+ status = "okay";
+};
&fec1 {
pinctrl-names = "default";
@@ -91,6 +118,15 @@
};
};
+/* Release reset of the USB Host HUB */
+&gpio1 {
+ usb-host-reset-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -174,6 +210,98 @@
};
};
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pca9546: i2cmux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c4@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+ };
+
+ ddc_i2c_bus: i2c4@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ max7323: gpio-expander@68 {
+ compatible = "maxim,max7323";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7323>;
+ gpio-controller;
+ reg = <0x68>;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&hdmi_out_in>;
+ };
+ };
+ };
+};
+
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -190,6 +318,29 @@
status = "okay";
};
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_0>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+ status = "okay";
+};
+
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
@@ -321,6 +472,19 @@
>;
};
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_max7323: max7323grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
+ >;
+ };
+
pinctrl_reg_arm_dram: reg-arm-dramgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
@@ -339,6 +503,12 @@
>;
};
+ pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
@@ -353,6 +523,18 @@
>;
};
+ pinctrl_usb3_0: usb3-0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
+ >;
+ };
+
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e..91df9c5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1383,6 +1383,14 @@
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
@@ -1413,6 +1421,14 @@
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
index d607f2f6..79a55a0f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
@@ -3,7 +3,7 @@
/*
* dtsi for Hisilicon Hi3660 Coresight
*
- * Copyright (C) 2016-2018 Hisilicon Ltd.
+ * Copyright (C) 2016-2018 HiSilicon Ltd.
*
* Author: Wanglai Shi <shiwanglai@hisilicon.com>
*
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 963300e..f68580d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey960 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*
*/
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index cab89dc..f1ec87c 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3660 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index 7f9f988..d8abf44 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey970 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*
*/
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 8830795..20698cf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3670 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*/
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
index 7b3010f..3f387f4 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
@@ -2,7 +2,7 @@
/*
* dtsi file for Hisilicon Hi6220 coresight
*
- * Copyright (C) 2017 Hisilicon Ltd.
+ * Copyright (C) 2017 HiSilicon Ltd.
*
* Author: Pengcheng Li <lipengcheng8@huawei.com>
* Leo Yan <leo.yan@linaro.org>
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 91d0867..3df2afb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey Development Board
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*
*/
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index d426c6c..dde9371 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi6220 SoC
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index 369b69b..40f3e00 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4aed8d4..7b2abd1 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index 9f4a930..35af5d3 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 7deca5f7..70d7732 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
index 81a2312..c3df678 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2172d80..6baf6a6 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index 53e817c..ce2bcdd 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -109,10 +109,8 @@
};
firmware {
- turris-mox-rwtm {
- compatible = "cznic,turris-mox-rwtm";
- mboxes = <&rwtm 0>;
- status = "okay";
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 6ffbb09..5db81a4 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -504,4 +504,12 @@
};
};
};
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware";
+ mboxes = <&rwtm 0>;
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
index d9bbbfa..4a23f65 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
@@ -29,6 +29,7 @@
};
&ap_sdhci0 {
- compatible = "marvell,armada-ap807-sdhci";
+ compatible = "marvell,armada-ap807-sdhci",
+ "marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index 2c2af00..97586095 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -260,7 +260,7 @@
};
partition@200000 {
label = "Linux";
- reg = <0x200000 0xd00000>;
+ reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index a1c50ad..4f68ebe 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -13,8 +13,16 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 1c5639e..9029051 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
+#include <dt-bindings/power/mt8167-power.h>
#include "mt8167-pinfunc.h"
@@ -34,6 +35,73 @@
#clock-cells = <1>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8167-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT8167_POWER_DOMAIN_MM {
+ reg = <MT8167_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_VDEC {
+ reg = <MT8167_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>,
+ <&topckgen CLK_TOP_RG_VDEC>;
+ clock-names = "mm", "vdec";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_ISP {
+ reg = <MT8167_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
+ <&topckgen CLK_TOP_RG_SLOW_MFG>;
+ clock-names = "axi_mfg", "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,infracfg = <&infracfg>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_2D {
+ reg = <MT8167_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG {
+ reg = <MT8167_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_CONN {
+ reg = <MT8167_POWER_DOMAIN_CONN>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -57,5 +125,58 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ mmsys: mmsys@14000000 {
+ compatible = "mediatek,mt8167-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi@14017000 {
+ compatible = "mediatek,mt8167-smi-common";
+ reg = <0 0x14017000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb0: larb@14016000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x14016000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb1: larb@15001000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB1_SMI>,
+ <&imgsys CLK_IMG_LARB1_SMI>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
+ };
+
+ larb2: larb@16010000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
+ };
+
+ iommu: m4u@10203000 {
+ compatible = "mediatek,mt8167-m4u";
+ reg = <0 0x10203000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+ #iommu-cells = <1>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 003a565..22f271b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1459,14 +1459,11 @@
clock-names = "apb", "smi";
};
- vcodec_enc: vcodec@18002000 {
+ vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+ reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1477,29 +1474,12 @@
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
- <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
jpegdec: jpegdec@18004000 {
@@ -1531,5 +1511,27 @@
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";
};
+
+ vcodec_enc_vp8: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-enc-vp8";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents =
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index edff1e0..7bc0a6a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -42,6 +42,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
new file mode 100644
index 0000000..a8d6f32
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google burnet board";
+ compatible = "google,burnet", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c0 {
+ touchscreen@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+ post-power-on-delay-ms = <200>;
+ hid-descr-addr = <0x0020>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
new file mode 100644
index 0000000..ef6257c
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku1 board";
+ compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
+
+ pwmleds {
+ compatible = "pwm-leds";
+ keyboard_backlight: keyboard-backlight {
+ label = "cros_ec::kbd_backlight";
+ pwms = <&cros_ec_pwm 0>;
+ max-brightness = <1023>;
+ };
+ };
+};
+
+&cros_ec_pwm {
+ status = "okay";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
new file mode 100644
index 0000000..899c2e4
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku6 board";
+ compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
new file mode 100644
index 0000000..bbe6c33
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
new file mode 100644
index 0000000..e8c41f6
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel14 sku0 board";
+ compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts
new file mode 100644
index 0000000..b3f46c1
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google kappa board";
+ compatible = "google,kappa", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
new file mode 100644
index 0000000..6f1aa69
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-juniper.dtsi"
+
+/ {
+ model = "Google kenzo sku17 board";
+ compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
new file mode 100644
index 0000000..281265f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku0";
+ compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
new file mode 100644
index 0000000..22e56bd
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku1";
+ compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
new file mode 100644
index 0000000..76d3354
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_JUNIPER";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
index 4049dff..d8826c8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -92,6 +92,14 @@
};
};
+&cros_ec {
+ cros_ec_pwm: ec-pwm {
+ compatible = "google,cros-ec-pwm";
+ #pwm-cells = <1>;
+ status = "disabled";
+ };
+};
+
&dsi0 {
status = "okay";
/delete-node/panel@0;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
index b442e38..28966a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
@@ -88,11 +88,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -101,11 +103,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
index 2f5234a..3aa7940 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
@@ -62,11 +62,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c64";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcamio_reg>;
};
};
@@ -75,11 +77,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
index fbc471c..30c183c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
@@ -71,11 +71,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -84,11 +86,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index ff56bcf..ae549d5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -279,6 +279,11 @@
};
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -816,6 +821,10 @@
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
};
+
+ cbas {
+ compatible = "google,cros-cbas";
+ };
};
};
@@ -847,6 +856,20 @@
status = "okay";
};
+&thermal_zones {
+ tboard1 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor1>;
+ };
+
+ tboard2 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor2>;
+ };
+};
+
&u3phy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index 0aff5eb..ee91282 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -68,6 +68,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c5e822b6..f90df64 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -197,6 +197,91 @@
};
};
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <625000>, <850000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <631250>, <850000>;
+ };
+
+ opp-340000000 {
+ opp-hz = /bits/ 64 <340000000>;
+ opp-microvolt = <637500>, <850000>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <643750>, <850000>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-microvolt = <650000>, <850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <656250>, <850000>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <662500>, <850000>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ opp-microvolt = <675000>, <850000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <687500>, <850000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <700000>, <850000>;
+ };
+
+ opp-580000000 {
+ opp-hz = /bits/ 64 <580000000>;
+ opp-microvolt = <712500>, <850000>;
+ };
+
+ opp-620000000 {
+ opp-hz = /bits/ 64 <620000000>;
+ opp-microvolt = <725000>, <850000>;
+ };
+
+ opp-653000000 {
+ opp-hz = /bits/ 64 <653000000>;
+ opp-microvolt = <743750>, <850000>;
+ };
+
+ opp-698000000 {
+ opp-hz = /bits/ 64 <698000000>;
+ opp-microvolt = <768750>, <868750>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <793750>, <893750>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <825000>, <925000>;
+ };
+ };
+
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
@@ -673,7 +758,7 @@
nvmem-cell-names = "calibration-data";
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
@@ -1118,6 +1203,26 @@
#clock-cells = <1>;
};
+ gpu: gpu@13040000 {
+ compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+ interrupts =
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+
+ power-domains =
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
+ <&spm MT8183_POWER_DOMAIN_MFG_2D>;
+ power-domain-names = "core0", "core1", "core2";
+
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
@@ -1263,13 +1368,14 @@
};
smi_common: smi@14019000 {
- compatible = "mediatek,mt8183-smi-common", "syscon";
+ compatible = "mediatek,mt8183-smi-common";
reg = <0 0x14019000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
imgsys: syscon@15020000 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 683743f..74c1a5d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -817,7 +817,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-tx2-hda";
+ nvidia,model = "NVIDIA Jetson TX2 HDA";
status = "okay";
};
@@ -1109,6 +1109,6 @@
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
<&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
- label = "jetson-tx2-ape";
+ label = "NVIDIA Jetson TX2 APE";
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9f75bbf..d02f6bf 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1082,7 +1082,7 @@
};
smmu: iommu@12000000 {
- compatible = "arm,mmu-500";
+ compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
reg = <0 0x12000000 0 0x800000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -1152,6 +1152,8 @@
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
};
host1x@13e00000 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index d618f19..96bd01c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -554,7 +554,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-hda";
+ nvidia,model = "NVIDIA Jetson AGX Xavier HDA";
status = "okay";
};
@@ -831,7 +831,7 @@
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
- label = "jetson-xavier-ape";
+ label = "NVIDIA Jetson AGX Xavier APE";
widgets =
"Microphone", "CVB-RT MIC Jack",
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index d1d7722..836a7e0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -15,6 +15,577 @@
interrupt-controller@2a40000 {
status = "okay";
};
+
+ ahub@2900800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0_ep: endpoint {
+ remote-endpoint = <&admaif0_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1_ep: endpoint {
+ remote-endpoint = <&admaif1_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2_ep: endpoint {
+ remote-endpoint = <&admaif2_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3_ep: endpoint {
+ remote-endpoint = <&admaif3_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4_ep: endpoint {
+ remote-endpoint = <&admaif4_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5_ep: endpoint {
+ remote-endpoint = <&admaif5_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6_ep: endpoint {
+ remote-endpoint = <&admaif6_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7_ep: endpoint {
+ remote-endpoint = <&admaif7_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8_ep: endpoint {
+ remote-endpoint = <&admaif8_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9_ep: endpoint {
+ remote-endpoint = <&admaif9_ep>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10_ep: endpoint {
+ remote-endpoint = <&admaif10_ep>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11_ep: endpoint {
+ remote-endpoint = <&admaif11_ep>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12_ep: endpoint {
+ remote-endpoint = <&admaif12_ep>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13_ep: endpoint {
+ remote-endpoint = <&admaif13_ep>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14_ep: endpoint {
+ remote-endpoint = <&admaif14_ep>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15_ep: endpoint {
+ remote-endpoint = <&admaif15_ep>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16_ep: endpoint {
+ remote-endpoint = <&admaif16_ep>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17_ep: endpoint {
+ remote-endpoint = <&admaif17_ep>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18_ep: endpoint {
+ remote-endpoint = <&admaif18_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19_ep: endpoint {
+ remote-endpoint = <&admaif19_ep>;
+ };
+ };
+
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+
+ xbar_i2s5_port: port@18 {
+ reg = <0x18>;
+
+ xbar_i2s5_ep: endpoint {
+ remote-endpoint = <&i2s5_cif_ep>;
+ };
+ };
+
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+
+ xbar_dmic4_port: port@1d {
+ reg = <0x1d>;
+
+ xbar_dmic4_ep: endpoint {
+ remote-endpoint = <&dmic4_cif_ep>;
+ };
+ };
+
+ xbar_dspk1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_dspk1_ep: endpoint {
+ remote-endpoint = <&dspk1_cif_ep>;
+ };
+ };
+
+ xbar_dspk2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_dspk2_ep: endpoint {
+ remote-endpoint = <&dspk2_cif_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap_ep: endpoint@0 {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic4_ep>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk1_ep>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk2_ep>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+ };
};
ddc: i2c@3190000 {
@@ -36,7 +607,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-nx-hda";
+ nvidia,model = "NVIDIA Jetson Xavier NX HDA";
status = "okay";
};
@@ -265,6 +836,28 @@
regulator-boot-on;
};
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s3_port>, <&xbar_i2s5_port>,
+ <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,
+ <&xbar_dspk1_port>, <&xbar_dspk2_port>,
+ /* BE I/O Ports */
+ <&i2s3_port>, <&i2s5_port>,
+ <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
+ <&dspk1_port>, <&dspk2_port>;
+
+ label = "NVIDIA Jetson Xavier NX APE";
+ };
+
thermal-zones {
cpu {
polling-delay = <0>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9449156..b7d5328 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
@@ -733,6 +734,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC1>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC3>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_HDA>;
status = "disabled";
};
@@ -1300,6 +1305,84 @@
interrupt-controller;
};
+ smmu: iommu@12000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x12000000 0x800000>,
+ <0x11000000 0x800000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@
ranges = <0x15000000 0x15000000 0x01000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
+ iommus = <&smmu TEGRA194_SID_HOST1X>;
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_VIC>;
};
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA194_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@@ -2345,6 +2431,20 @@
};
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
+ &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 497635a..7d3e363 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -424,6 +424,6 @@
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
- label = "jetson-tx1-ape";
+ label = "NVIDIA Jetson TX1 APE";
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index a9caaf7c..d8409c1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1345,7 +1345,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-tx1-hda";
+ nvidia,model = "NVIDIA Jetson TX1 HDA";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 14c128a..7dbb13f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -441,7 +441,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-nano-hda";
+ nvidia,model = "NVIDIA Jetson Nano HDA";
status = "okay";
};
@@ -1043,6 +1043,6 @@
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
- label = "jetson-nano-ape";
+ label = "NVIDIA Jetson Nano APE";
};
};
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 456502a..4f05970 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -5,8 +5,11 @@
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
@@ -32,11 +35,12 @@
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2.dtb
-dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
@@ -51,6 +55,8 @@
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
@@ -70,8 +76,13 @@
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index defcbd1..06869235 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -41,14 +41,14 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
- serial1 = &blsp2_uart2;
- serial2 = &blsp1_uart1;
- i2c0 = &blsp1_i2c2;
+ serial0 = &blsp2_uart2;
+ serial1 = &blsp2_uart3;
+ serial2 = &blsp1_uart2;
+ i2c0 = &blsp1_i2c3;
i2c1 = &blsp2_i2c1;
- i2c2 = &blsp2_i2c0;
- spi0 = &blsp1_spi0;
- spi1 = &blsp2_spi5;
+ i2c2 = &blsp2_i2c1;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp2_spi6;
};
chosen {
@@ -133,24 +133,24 @@
};
};
-&blsp1_i2c2 {
+&blsp1_i2c3 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
-&blsp1_spi0 {
+&blsp1_spi1 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
-&blsp1_uart1 {
+&blsp1_uart2 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
@@ -162,7 +162,11 @@
};
};
-&blsp2_i2c0 {
+&adsp_pil {
+ status = "okay";
+};
+
+&blsp2_i2c1 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
@@ -174,32 +178,36 @@
status = "okay";
};
-&blsp2_spi5 {
+&blsp2_spi6 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
-&blsp2_uart1 {
+&blsp2_uart2 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&blsp2_uart2 {
+&blsp2_uart3 {
label = "LS-UART0";
status = "disabled";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart2_4pins_default>;
- pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+ pinctrl-0 = <&blsp2_uart3_4pins_default>;
+ pinctrl-1 = <&blsp2_uart3_4pins_sleep>;
};
&camss {
vdda-supply = <&vreg_l2a_1p25>;
};
+&gpu {
+ status = "okay";
+};
+
&hdmi {
status = "okay";
@@ -245,7 +253,12 @@
vdd-gfx-supply = <&vdd_gfx>;
};
-&msmgpio {
+&pm8994_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&tlmm {
gpio-line-names =
"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
@@ -424,7 +437,7 @@
};
};
- blsp1_uart1_default: blsp1_uart1_default {
+ blsp1_uart2_default: blsp1_uart2_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
@@ -437,7 +450,7 @@
};
};
- blsp1_uart1_sleep: blsp1_uart1_sleep {
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
@@ -505,20 +518,20 @@
&pcie0 {
status = "okay";
- perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie2 {
status = "okay";
- perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
@@ -929,9 +942,9 @@
&sdhc2 {
/* External SD card */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- cd-gpios = <&msmgpio 38 0x1>;
+ pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
status = "okay";
@@ -1026,20 +1039,6 @@
};
};
-&spmi_bus {
- pmic@0 {
- pon@800 {
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
- };
- };
-};
-
&ufsphy {
status = "okay";
@@ -1064,7 +1063,7 @@
status = "okay";
extcon = <&usb2_id>;
- dwc3@7600000 {
+ usb@7600000 {
extcon = <&usb2_id>;
dr_mode = "otg";
maximum-speed = "high-speed";
@@ -1075,7 +1074,7 @@
status = "okay";
extcon = <&usb3_id>;
- dwc3@6a00000 {
+ usb@6a00000 {
extcon = <&usb3_id>;
dr_mode = "otg";
};
@@ -1089,6 +1088,10 @@
};
+&venus {
+ status = "okay";
+};
+
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
index f6ddf17a..8c7a27e 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
@@ -17,7 +17,7 @@
qcom,board-id = <0x00010018 0>;
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
@@ -81,14 +81,22 @@
};
};
-&blsp2_uart1 {
+&blsp2_uart2 {
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&msmgpio {
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&tlmm {
sdc2_pins_default: sdc2-pins-default {
clk {
pins = "sdc2_clk";
@@ -352,7 +360,7 @@
bus-width = <4>;
- cd-gpios = <&msmgpio 38 0x1>;
+ cd-gpios = <&tlmm 38 0x1>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
@@ -383,3 +391,7 @@
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
new file mode 100644
index 0000000..2bfcf42
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1";
+ compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
new file mode 100644
index 0000000..7da39f1d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2";
+ compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
new file mode 100644
index 0000000..07e6708
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+};
+
+&blsp1_spi1 {
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart5 {
+ status = "ok";
+};
+
+&pcie0 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+};
+
+&pcie1 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+};
+
+&pcie_phy0 {
+ status = "ok";
+};
+
+&pcie_phy1 {
+ status = "ok";
+};
+
+&qpic_bam {
+ status = "ok";
+};
+
+&qpic_nand {
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a32e5e7..95d6cb8 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -165,6 +165,7 @@
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
};
pcie_phy0: phy@86000 {
@@ -372,6 +373,21 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x078ba000 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 23>, <&blsp_dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07984000 0x1a000>;
@@ -427,7 +443,7 @@
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
- dwc_0: dwc3@8a00000 {
+ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +484,7 @@
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
- dwc_1: dwc3@8c00000 {
+ dwc_1: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
index 540b1fa..670bd1b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
@@ -45,6 +45,24 @@
status = "okay";
};
+&blsp_i2c4 {
+ status = "okay";
+
+ touchscreen@26 {
+ compatible = "mstar,msg2638";
+ reg = <0x26>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_reset_default>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+ touchscreen-size-x = <2048>;
+ touchscreen-size-y = <2048>;
+ };
+};
+
&blsp_i2c5 {
status = "okay";
@@ -281,6 +299,14 @@
bias-pull-up;
};
+ ts_int_reset_default: ts-int-reset-default {
+ pins = "gpio13", "gpio100";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
usb_id_default: usb-id-default {
pins = "gpio69";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
new file mode 100644
index 0000000..e0075b5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2021 Stephan Gerhold
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+
+/*
+ * Note: The original firmware from Huawei can only boot 32-bit kernels.
+ * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
+ * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
+ * forgot to set up (firmware) secure boot for some reason.
+ *
+ * Also note that Huawei no longer provides bootloader unlock codes.
+ * This can be bypassed by patching the bootloader from a custom HYP firmware,
+ * making it think the bootloader is unlocked.
+ *
+ * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)
+ */
+
+/ {
+ model = "Huawei Ascend G7";
+ compatible = "huawei,g7", "qcom,msm8916";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ label = "GPIO Buttons";
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds_default>;
+
+ led-0 {
+ gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-1 {
+ gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-2 {
+ gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_default>;
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak09911";
+ reg = <0x0c>;
+
+ vdd-supply = <&pm8916_l17>;
+ vid-supply = <&pm8916_l6>;
+
+ reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mag_reset_default>;
+ };
+
+ accelerometer@1e {
+ compatible = "kionix,kx023-1025";
+ reg = <0x1e>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <115 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_irq_default>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+
+ proximity@39 {
+ compatible = "avago,apds9930";
+ reg = <0x39>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <113 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ led-max-microamp = <100000>;
+ amstaos,proximity-diodes = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&prox_irq_default>;
+ };
+
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <®_lcd_en_default>;
+
+ reg_lcd_pos: outp {
+ regulator-name = "outp";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+
+ reg_lcd_neg: outn {
+ regulator-name = "outn";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ rmi4@70 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l16>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_irq_default>;
+
+ syna,startup-delay-ms = <100>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>; /* Allow sleeping */
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>; /* Touchscreen */
+ };
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&pm8916_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&pronto {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>;
+
+ /*
+ * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>.
+ * However, gpio38 does not change its state when inserting/removing the
+ * SD card, it's just low all the time. The Huawei kernel seems to use
+ * polling for SD card detection instead.
+ *
+ * However, looking closer at the GPIO debug output it turns out that
+ * gpio56 switches its state when inserting/removing the SD card.
+ * It behaves just like gpio38 normally does. Usually GPIO56 is used as
+ * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted.
+ * Maybe Huawei decided to replace the second SIM card slot with the
+ * SD card slot and forgot to re-route to gpio38.
+ */
+ cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>;
+};
+
+&usb {
+ status = "okay";
+ extcon = <&usb_id>, <&usb_id>;
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&smd_rpm_regulators {
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ l4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l8 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l10 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ l11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+
+ l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+};
+
+&msmgpio {
+ accel_irq_default: accel-irq-default {
+ pins = "gpio115";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default {
+ pins = "gpio107";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ gpio_leds_default: gpio-leds-default {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ nfc_default: nfc-default {
+ pins = "gpio2", "gpio20", "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mag_reset_default: mag-reset-default {
+ pins = "gpio36";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ prox_irq_default: prox-irq-default {
+ pins = "gpio113";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ reg_lcd_en_default: reg-lcd-en-default {
+ pins = "gpio32", "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdhc2_cd_default: sdhc2-cd-default {
+ pins = "gpio56";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_irq_default: ts-irq-default {
+ pins = "gpio13";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ usb_id_default: usb-id-default {
+ pins = "gpio117";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
index 230ba3c..9b4b7de 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
@@ -95,6 +96,63 @@
pinctrl-0 = <&muic_int_default>;
};
};
+
+ i2c-tkey {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey: touchkey@20 {
+ /* Note: Actually an ABOV MCU that implements same interface */
+ compatible = "coreriver,tc360-touchkey";
+ reg = <0x20>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <98 IRQ_TYPE_EDGE_FALLING>;
+
+ /* vcc/vdd-supply are board-specific */
+ vddio-supply = <&pm8916_l6>;
+
+ linux,keycodes = <KEY_APPSELECT KEY_BACK>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_default>;
+ };
+ };
+
+ i2c-nfc {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+ reg = <0x27>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default &nfc_clk_req>;
+ };
+ };
};
&blsp_i2c2 {
@@ -122,6 +180,20 @@
};
};
+&blsp_i2c4 {
+ status = "okay";
+
+ battery@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <121 IRQ_TYPE_EDGE_BOTH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fg_alert_default>;
+ };
+};
+
&blsp1_uart2 {
status = "okay";
};
@@ -284,6 +356,14 @@
bias-disable;
};
+ fg_alert_default: fg-alert-default {
+ pins = "gpio121";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
gpio_keys_default: gpio-keys-default {
pins = "gpio107", "gpio109";
function = "gpio";
@@ -333,6 +413,46 @@
bias-disable;
};
+ nfc_default: nfc-default {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+
+ irq {
+ pins = "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ nfc_i2c_default: nfc-i2c-default {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_default: tkey-default {
+ pins = "gpio98";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_i2c_default: tkey-i2c-default {
+ pins = "gpio16", "gpio17";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
tsp_en_default: tsp-en-default {
pins = "gpio73";
function = "gpio";
@@ -341,3 +461,14 @@
bias-disable;
};
};
+
+&pm8916_gpios {
+ nfc_clk_req: nfc-clk-req {
+ pins = "gpio2";
+ function = "func1";
+
+ input-enable;
+ bias-disable;
+ power-source = <PM8916_GPIO_L2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
index 661f41a..6cc2eae 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
@@ -20,6 +20,37 @@
pinctrl-names = "default";
pinctrl-0 = <&panel_vdd3_default>;
};
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
+
+ reg_key_led: regulator-key-led {
+ compatible = "regulator-fixed";
+ regulator-name = "key_led";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_led_en_default>;
+ };
+};
+
+&touchkey {
+ vcc-supply = <®_touch_key>;
+ vdd-supply = <®_key_led>;
};
&accelerometer {
@@ -81,6 +112,22 @@
bias-disable;
};
+ tkey_en_default: tkey-en-default {
+ pins = "gpio86";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_led_en_default: tkey-led-en-default {
+ pins = "gpio60";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
index dd35c33..c2eff5a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
@@ -7,6 +7,19 @@
/ {
model = "Samsung Galaxy A5U (EUR)";
compatible = "samsung,a5u-eur", "qcom,msm8916";
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
};
&accelerometer {
@@ -42,7 +55,20 @@
};
};
+&touchkey {
+ vcc-supply = <®_touch_key>;
+ vdd-supply = <®_touch_key>;
+};
+
&msmgpio {
+ tkey_en_default: tkey-en-default {
+ pins = "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
index baa5564..ffe1a9b 100644
--- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
@@ -32,3 +32,7 @@
};
};
};
+
+&tlmm {
+ gpio-reserved-ranges = <85 4>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
index 5f46a14..1e1514e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
@@ -7,7 +7,7 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
deleted file mode 100644
index ac1ede5..0000000
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ /dev/null
@@ -1,653 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
-
- wcd9xxx_intr {
- wcd_intr_default: wcd_intr_default{
- mux {
- pins = "gpio54";
- function = "gpio";
- };
-
- config {
- pins = "gpio54";
- drive-strength = <2>; /* 2 mA */
- bias-pull-down; /* pull down */
- input-enable;
- };
- };
- };
-
- cdc_reset_ctrl {
- cdc_reset_sleep: cdc_reset_sleep {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
- };
- cdc_reset_active:cdc_reset_active {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-pull-down;
- output-high;
- };
- };
- };
-
- blsp1_spi0_default: blsp1_spi0_default {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio0", "gpio1", "gpio3";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio2";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio3";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio2";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp1_spi0_sleep: blsp1_spi0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- blsp1_i2c2_default: blsp1_i2c2_default {
- pinmux {
- function = "blsp_i2c3";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <16>;
- bias-disable = <0>;
- };
- };
-
- blsp1_i2c2_sleep: blsp1_i2c2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <2>;
- bias-disable = <0>;
- };
- };
-
- blsp2_i2c0_default: blsp2_i2c0 {
- pinmux {
- function = "blsp_i2c7";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c0_sleep: blsp2_i2c0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_default: blsp2_uart1_2pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_default: blsp2_uart1_4pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_default: blsp2_i2c1 {
- pinmux {
- function = "blsp_i2c8";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_sleep: blsp2_i2c1_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_default: blsp2_uart2_2pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_default: blsp2_uart2_4pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_spi5_default: blsp2_spi5_default {
- pinmux {
- function = "blsp_spi12";
- pins = "gpio85", "gpio86", "gpio88";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio87";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio88";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio87";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp2_spi5_sleep: blsp2_spi5_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- sdc2_clk_on: sdc2_clk_on {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <16>; /* 16 MA */
- };
- };
-
- sdc2_clk_off: sdc2_clk_off {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_cmd_on: sdc2_cmd_on {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_cmd_off: sdc2_cmd_off {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_data_on: sdc2_data_on {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_data_off: sdc2_data_off {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- pcie0_clkreq_default: pcie0_clkreq_default {
- mux {
- pins = "gpio36";
- function = "pci_e0";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_perst_default: pcie0_perst_default {
- mux {
- pins = "gpio35";
- function = "gpio";
- };
-
- config {
- pins = "gpio35";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie0_wake_default: pcie0_wake_default {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_clkreq_sleep: pcie0_clkreq_sleep {
- mux {
- pins = "gpio36";
- function = "gpio";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie0_wake_sleep: pcie0_wake_sleep {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_clkreq_default: pcie1_clkreq_default {
- mux {
- pins = "gpio131";
- function = "pci_e1";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_perst_default: pcie1_perst_default {
- mux {
- pins = "gpio130";
- function = "gpio";
- };
-
- config {
- pins = "gpio130";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_wake_default: pcie1_wake_default {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_clkreq_sleep: pcie1_clkreq_sleep {
- mux {
- pins = "gpio131";
- function = "gpio";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_wake_sleep: pcie1_wake_sleep {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_clkreq_default: pcie2_clkreq_default {
- mux {
- pins = "gpio115";
- function = "pci_e2";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_perst_default: pcie2_perst_default {
- mux {
- pins = "gpio114";
- function = "gpio";
- };
-
- config {
- pins = "gpio114";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_wake_default: pcie2_wake_default {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_clkreq_sleep: pcie2_clkreq_sleep {
- mux {
- pins = "gpio115";
- function = "gpio";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_wake_sleep: pcie2_wake_sleep {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- cci0_default: cci0_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio17", "gpio18";
- };
- pinconf {
- pins = "gpio17", "gpio18";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- cci1_default: cci1_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio19", "gpio20";
- };
- pinconf {
- pins = "gpio19", "gpio20";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_board_default: camera_board_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio98";
- };
- config_pwdn {
- pins = "gpio98";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio104";
- };
- config_rst {
- pins = "gpio104";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk1 {
- function = "cam_mclk";
- pins = "gpio14";
- };
- config_mclk1 {
- pins = "gpio14";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_front_default: camera_front_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio133";
- };
- config_pwdn {
- pins = "gpio133";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio23";
- };
- config_rst {
- pins = "gpio23";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk2 {
- function = "cam_mclk";
- pins = "gpio15";
- };
- config_mclk2 {
- pins = "gpio15";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_rear_default: camera_rear_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio26";
- };
- config_pwdn {
- pins = "gpio26";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio25";
- };
- config_rst {
- pins = "gpio25";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk0 {
- function = "cam_mclk";
- pins = "gpio13";
- };
- config_mclk0 {
- pins = "gpio13";
- drive-strength = <16>;
- bias-disable;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 5d06216..0e1bc46 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -43,6 +45,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -57,6 +62,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -67,6 +75,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -81,6 +92,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -120,6 +134,227 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-msm8996";
@@ -424,7 +659,7 @@
bits = <1 4>;
};
- gpu_speed_bin: gpu_speed_bin@133 {
+ speedbin_efuse: speedbin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
@@ -472,7 +707,7 @@
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
- reg = <0x00740000 0x20000>;
+ reg = <0x00740000 0x40000>;
};
tcsr: syscon@7a0000 {
@@ -521,6 +756,8 @@
#size-cells = <1>;
ranges;
+ status = "disabled";
+
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x00901000 0x90000>;
@@ -542,6 +779,11 @@
iommus = <&mdp_smmu 0>;
+ assigned-clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -552,9 +794,82 @@
remote-endpoint = <&hdmi_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
};
};
+ dsi0: dsi@994000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x00994000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "byte",
+ "iface",
+ "bus",
+ "core_mmss",
+ "pixel",
+ "core";
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: dsi-phy@994400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0x00994400 0x100>,
+ <0x00994500 0x300>,
+ <0x00994800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+ status = "disabled";
+ };
+
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
@@ -618,7 +933,8 @@
"ref";
};
};
- gpu@b00000 {
+
+ gpu: gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
@@ -642,7 +958,7 @@
power-domains = <&mmcc GPU_GX_GDSC>;
iommus = <&adreno_smmu 0>;
- nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cells = <&speedbin_efuse>;
nvmem-cell-names = "speed_bin";
qcom,gpu-quirk-two-pass-use-wfi;
@@ -650,6 +966,8 @@
operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
@@ -693,15 +1011,482 @@
};
};
- msmgpio: pinctrl@1010000 {
+ tlmm: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&msmgpio 0 0 150>;
+ gpio-ranges = <&tlmm 0 0 150>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ blsp1_spi1_default: blsp1-spi1-default {
+ spi {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp1_spi1_sleep: blsp1-spi1-sleep {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_default: blsp2-i2c2 {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci0_default: cci0-default {
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera0_state_on:
+ camera_rear_default: camera-rear-default {
+ mclk0 {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci1_default: cci1-default {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera1_state_on:
+ camera_board_default: camera-board-default {
+ mclk1 {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio98";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera2_state_on:
+ camera_front_default: camera-front-default {
+ mclk2 {
+ pins = "gpio15";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ pcie0_state_on: pcie0-state-on {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_state_off: pcie0-state-off {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_i2c3_default: blsp1-i2c2-default {
+ pins = "gpio47", "gpio48";
+ function = "blsp_i2c3";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+
+ blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ pins = "gpio47", "gpio48";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+
+ blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcd_intr_default: wcd-intr-default{
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ blsp2_i2c1_default: blsp2-i2c1 {
+ pins = "gpio55", "gpio56";
+ function = "blsp_i2c7";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c5_default: blsp2-i2c5 {
+ pins = "gpio60", "gpio61";
+ function = "blsp_i2c11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /* Sleep state for BLSP2_I2C5 is missing.. */
+
+ cdc_reset_active: cdc-reset-active {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ output-high;
+ };
+
+ cdc_reset_sleep: cdc-reset-sleep {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ blsp2_spi6_default: blsp2-spi5-default {
+ spi {
+ pins = "gpio85", "gpio86", "gpio88";
+ function = "blsp_spi12";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp2_spi6_sleep: blsp2-spi5-sleep {
+ pins = "gpio85", "gpio86", "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_i2c6_default: blsp2-i2c6 {
+ pins = "gpio87", "gpio88";
+ function = "blsp_i2c12";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ pins = "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_state_on: pcie1-state-on {
+ perst {
+ pins = "gpio130";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio131";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_state_off: pcie1-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio131";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie2_state_on: pcie2-state-on {
+ perst {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio115";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_state_off: pcie2-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sdc1_state_on: sdc1-state-on {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-state-off {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-clk-on {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-clk-off {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
spmi_bus: qcom,spmi@400f000 {
@@ -762,8 +1547,8 @@
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
- pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
+ pinctrl-0 = <&pcie0_state_on>;
+ pinctrl-1 = <&pcie0_state_off>;
linux,pci-domain = <0>;
@@ -816,8 +1601,8 @@
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
- pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+ pinctrl-0 = <&pcie1_state_on>;
+ pinctrl-1 = <&pcie1_state_off>;
linux,pci-domain = <1>;
@@ -867,8 +1652,8 @@
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+ pinctrl-0 = <&pcie2_state_on>;
+ pinctrl-1 = <&pcie2_state_off>;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
@@ -1152,7 +1937,7 @@
power-domains = <&mmcc GPU_GDSC>;
};
- video-codec@c00000 {
+ venus: video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
@@ -1183,7 +1968,7 @@
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
- status = "okay";
+ status = "disabled";
video-decoder {
compatible = "venus-decoder";
@@ -1745,9 +2530,14 @@
};
};
};
+
kryocc: clock-controller@6400000 {
- compatible = "qcom,apcc-msm8996";
+ compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
+
+ clock-names = "xo";
+ clocks = <&xo_board>;
+
#clock-cells = <1>;
};
@@ -1758,6 +2548,10 @@
#size-cells = <1>;
ranges;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
@@ -1772,7 +2566,7 @@
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
- dwc3@6a00000 {
+ usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
@@ -1841,34 +2635,75 @@
status = "disabled";
};
+ sdhc1: sdhci@7464900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x07464900 0x11c>, <0x07464000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+ };
+
sdhc2: sdhci@74a4900 {
- status = "disabled";
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
- clock-names = "iface", "core", "xo";
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
- bus-width = <4>;
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+
+ bus-width = <4>;
+ status = "disabled";
};
- blsp1_uart1: serial@7570000 {
+ blsp1_dma: dma@7544000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07544000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart2: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
- blsp1_spi0: spi@7575000 {
+ blsp1_spi1: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -1876,14 +2711,16 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_spi0_default>;
- pinctrl-1 = <&blsp1_spi0_sleep>;
+ pinctrl-0 = <&blsp1_spi1_default>;
+ pinctrl-1 = <&blsp1_spi1_sleep>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp1_i2c2: i2c@7577000 {
+ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -1891,14 +2728,27 @@
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_i2c2_default>;
- pinctrl-1 = <&blsp1_i2c2_sleep>;
+ pinctrl-0 = <&blsp1_i2c3_default>;
+ pinctrl-1 = <&blsp1_i2c3_sleep>;
+ dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_uart1: serial@75b0000 {
+ blsp2_dma: dma@7584000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07584000 0x2b000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -1908,7 +2758,7 @@
status = "disabled";
};
- blsp2_uart2: serial@75b1000 {
+ blsp2_uart3: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
@@ -1918,7 +2768,7 @@
status = "disabled";
};
- blsp2_i2c0: i2c@75b5000 {
+ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -1926,14 +2776,16 @@
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c0_default>;
- pinctrl-1 = <&blsp2_i2c0_sleep>;
+ pinctrl-0 = <&blsp2_i2c1_default>;
+ pinctrl-1 = <&blsp2_i2c1_sleep>;
+ dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_i2c1: i2c@75b6000 {
+ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@@ -1941,14 +2793,49 @@
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c1_default>;
- pinctrl-1 = <&blsp2_i2c1_sleep>;
+ pinctrl-0 = <&blsp2_i2c2_default>;
+ pinctrl-1 = <&blsp2_i2c2_sleep>;
+ dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_spi5: spi@75ba000{
+ blsp2_i2c5: i2c@75b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75b9000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp2_i2c5_default>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_i2c6: i2c@75ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75ba000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c6_default>;
+ pinctrl-1 = <&blsp2_i2c6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_spi6: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -1956,8 +2843,10 @@
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_spi5_default>;
- pinctrl-1 = <&blsp2_spi5_sleep>;
+ pinctrl-0 = <&blsp2_spi6_default>;
+ pinctrl-1 = <&blsp2_spi6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1981,14 +2870,16 @@
assigned-clock-rates = <19200000>, <60000000>;
power-domains = <&gcc USB30_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
status = "disabled";
- dwc3@7600000 {
+ usb@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
@@ -2032,13 +2923,13 @@
compatible = "slim217,1a0";
reg = <1 0>;
- interrupt-parent = <&msmgpio>;
+ interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
- reset-gpios = <&msmgpio 64 0>;
+ reset-gpios = <&tlmm 64 0>;
slim-ifc-dev = <&tasha_ifd>;
@@ -2067,6 +2958,11 @@
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
+ power-domains = <&rpmpd MSM8996_VDDCX>;
+ power-domain-names = "cx";
+
+ status = "disabled";
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
@@ -2458,4 +3354,3 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
-#include "msm8996-pins.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index e9d3ce2..6f294f9 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -1964,7 +1964,7 @@
resets = <&gcc GCC_USB_30_BCR>;
- usb3_dwc3: dwc3@a800000 {
+ usb3_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 8ab4f1f..8a4972e 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -7,6 +7,30 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
+/ {
+ thermal-zones {
+ pm6150_thermal: pm6150-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6150_temp>;
+
+ trips {
+ pm6150_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6150_crit: crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pm6150_lsid0: pmic@0 {
compatible = "qcom,pm6150", "qcom,spmi-pmic";
diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi
new file mode 100644
index 0000000..e7f64a9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2021, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm7325: pmic@1 {
+ compatible = "qcom,pm7325", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm7325_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm7325_gpios: gpios@8800 {
+ compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm7325_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm7325_thermal: pm7325-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7325_temp_alarm>;
+
+ trips {
+ pm7325_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm7325_crit: pm7325-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index fa4ea7d..c566a64 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -50,7 +50,8 @@
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
- pwrkey {
+
+ pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
@@ -59,6 +60,15 @@
status = "disabled";
};
+
+ pon_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+
+ status = "disabled";
+ };
};
pm8150_temp: temp-alarm@2400 {
diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi
index 2b9b75e..e1b75ae 100644
--- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8350c_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pm8350c_gpios: gpio@8800 {
- compatible = "qcom,pm8350c-gpio";
+ compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pm8350c_gpios 0 0 9>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pm8350c_thermal: pm8350c-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8350c_temp_alarm>;
+
+ trips {
+ pm8350c_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8350c_crit: pm8350c-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index c3876c8..ad19016 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -45,7 +45,6 @@
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
-
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
@@ -58,6 +57,13 @@
linux,code = <KEY_POWER>;
};
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm8994_temp: temp-alarm@2400 {
diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
index e5ed28a..b4ac900 100644
--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -32,5 +32,18 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ pmi8994_wled: wled@d800 {
+ compatible = "qcom,pmi8994-wled";
+ reg = <0xd800 0xd900>;
+ interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "short";
+ qcom,num-strings = <3>;
+ /* Yes, all four strings *have to* be defined or things won't work. */
+ qcom,enabled-strings = <0 1 2 3>;
+ qcom,cabc;
+ qcom,eternal-pfet;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
index 1530b8f..04fc263 100644
--- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2021, Linaro Limited
*/
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@@ -13,10 +15,57 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmk8350_pon: pon@1300 {
+ compatible = "qcom,pm8998-pon";
+ reg = <0x1300>;
+
+ pwrkey {
+ compatible = "qcom,pmk8350-pwrkey";
+ interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ };
+
+ resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pmk8350_vadc: adc@3100 {
+ compatible = "qcom,spmi-adc7";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ };
+
+ pmk8350_adc_tm: adc-tm@3400 {
+ compatible = "qcom,adc-tm7";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "threshold";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ pmk8350_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
pmk8350_gpios: gpio@b000 {
- compatible = "qcom,pmk8350-gpio";
+ compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
reg = <0xb000>;
gpio-controller;
+ gpio-ranges = <&pmk8350_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
new file mode 100644
index 0000000..7072e5a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-1-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_1_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon: power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+
+ status = "disabled";
+ };
+ };
+
+ pmm8155au_1_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_1_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_1_adc_tm: adc-tm@3500 {
+ compatible = "qcom,spmi-adc-tm5";
+ reg = <0x3500>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pmm8155au_1_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_1_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_1_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
new file mode 100644
index 0000000..7207596
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_2_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@4 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_2_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_2_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_2_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_2_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@5 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi
index 1c675af1..b4b6ba24 100644
--- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmr735a_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pmr735a_gpios: gpio@8800 {
- compatible = "qcom,pmr735a-gpio";
+ compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pmr735a_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pmr735a_thermal: pmr735a-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmr735a_temp_alarm>;
+
+ trips {
+ pmr735a_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmr735a_crit: pmr735a-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index a80c578..f8a5530 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -337,7 +337,7 @@
&usb3 {
status = "okay";
- dwc3@7580000 {
+ usb@7580000 {
dr_mode = "host";
};
};
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 339790b..9c4be020d 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -544,7 +544,7 @@
assigned-clock-rates = <19200000>, <200000000>;
status = "disabled";
- dwc3@7580000 {
+ usb@7580000 {
compatible = "snps,dwc3";
reg = <0x07580000 0xcd00>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -573,7 +573,7 @@
assigned-clock-rates = <19200000>, <133333333>;
status = "disabled";
- dwc3@78c0000 {
+ usb@78c0000 {
compatible = "snps,dwc3";
reg = <0x078c0000 0xcc00>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 5f41de2..8ac96f8 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -5,7 +5,6 @@
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -552,7 +551,13 @@
vdds-supply = <&vreg_l5a_0p88>;
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -664,10 +669,6 @@
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_default_state>;
};
&pcie0_phy {
@@ -678,10 +679,6 @@
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_default_state>;
};
&pcie1_phy {
@@ -692,10 +689,6 @@
&pcie2 {
status = "okay";
- perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_default_state>;
};
&pcie2_phy {
@@ -1173,81 +1166,6 @@
bias-disable;
};
- pcie0_default_state: pcie0-default {
- clkreq {
- pins = "gpio80";
- function = "pci_e0";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio79";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio81";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_default_state: pcie1-default {
- clkreq {
- pins = "gpio83";
- function = "pci_e1";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio82";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio84";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_default_state: pcie2-default {
- clkreq {
- pins = "gpio86";
- function = "pci_e2";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio85";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio87";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
@@ -1352,6 +1270,10 @@
qcom,dmic-sample-rate = <600000>;
};
+&venus {
+ status = "okay";
+};
+
/* PINCTRL - additions to nodes defined in sm8250.dtsi */
&qup_spi0_cs_gpio {
drive-strength = <6>;
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
new file mode 100644
index 0000000..0da7a3b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pmm8155au_1.dtsi"
+#include "pmm8155au_2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA8155P ADP";
+ compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vreg_3p3: vreg_3p3_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /*
+ * S4A is always on and not controllable through RPMh.
+ * So model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: smps4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+
+ vin-supply = <&vreg_3p3>;
+ };
+};
+
+&apps_rsc {
+ pmm8155au-1-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p92>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s5a_2p04: smps5 {
+ regulator-name = "vreg_s5a_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p92: smps6 {
+ regulator-name = "vreg_s6a_0p92";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1a_0p752: ldo1 {
+ regulator-name = "vreg_l1a_0p752";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p072: ldo2 {
+ regulator-name = "vreg_l2a_3p072";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-name = "vreg_l3a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_usb_ss_dp_core_1:
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p96: ldo10 {
+ regulator-name = "vreg_l10a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-name = "vreg_l11a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_1p8:
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-name = "vreg_l13a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-name = "vreg_l15a_1p7";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_2p96: ldo17 {
+ regulator-name = "vreg_l17a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pmm8155au-2-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>;
+ vdd-l6-l9-supply = <&vreg_s6c_1p128>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s4c_1p352: smps4 {
+ regulator-name = "vreg_s4c_1p352";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5c_2p04: smps5 {
+ regulator-name = "vreg_s5c_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6c_1p128: smps6 {
+ regulator-name = "vreg_s6c_1p128";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1c_1p304: ldo1 {
+ regulator-name = "vreg_l1c_1p304";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p808: ldo2 {
+ regulator-name = "vreg_l2c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p2: ldo5 {
+ regulator-name = "vreg_l5c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_1p8: ldo7 {
+ regulator-name = "vreg_l7c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p2: ldo8 {
+ regulator-name = "vreg_l8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_0p8: ldo11 {
+ regulator-name = "vreg_l11c_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p808: ldo12 {
+ regulator-name = "vreg_l12c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p96: ldo13 {
+ regulator-name = "vreg_l13c_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15c_1p9: ldo15 {
+ regulator-name = "vreg_l15c_1p9";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16c_3p008: ldo16 {
+ regulator-name = "vreg_l16c_3p008";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18c_0p88: ldo18 {
+ regulator-name = "vreg_l18c_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p96>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l5c_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-max-microamp = <87100>;
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda-pll-max-microamp = <18300>;
+};
+
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index e77a792..acdb36f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sc7180.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
@@ -45,7 +46,7 @@
/* Increase the size from 2MB to 8MB */
&rmtfs_mem {
- reg = <0x0 0x84400000 0x0 0x800000>;
+ reg = <0x0 0x94600000 0x0 0x800000>;
};
/ {
@@ -288,6 +289,57 @@
};
};
+&dsi0 {
+ status = "okay";
+
+ vdda-supply = <&vreg_l3c_1p2>;
+
+ panel@0 {
+ compatible = "visionox,rm69299-1080p-display";
+ reg = <0>;
+
+ vdda-supply = <&vreg_l8c_1p8>;
+ vdd3p3-supply = <&vreg_l18a_2p8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pins>;
+
+ reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dsi_phy {
+ status = "okay";
+};
+
+&mdp {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
&qfprom {
vcc-supply = <&vreg_l11a_1p8>;
};
@@ -414,6 +466,19 @@
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+&pm6150l_gpio {
+ disp_pins: disp-pins {
+ pinconf {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_FUNC1;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
&qspi_clk {
pinconf {
pins = "gpio63";
@@ -598,4 +663,106 @@
bias-pull-up;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts
index 533c048..82dc00c 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts
@@ -9,8 +9,8 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev1) with LTE";
- compatible = "google,coachz-rev1-sku0", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2) with LTE";
+ compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180";
};
&cros_ec_proximity {
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
index 1b1dbdb..21b516e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
@@ -10,8 +10,26 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev1)";
- compatible = "google,coachz-rev1", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2)";
+ compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature,
+ * which currently is not supported by the PM6150 ADC driver. Disable the
+ * skin temperature thermal zone to avoid using bogus temperature values.
+ */
+&skin_temp_thermal {
+ status = "disabled";
};
&tlmm {
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts
similarity index 69%
rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts
rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts
index 6e77458..d2340903 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts
@@ -2,14 +2,14 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
-#include "sc7180-trogdor-coachz-r2.dts"
+#include "sc7180-trogdor-coachz-r3.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev2+) with LTE";
+ model = "Google CoachZ (rev3+) with LTE";
compatible = "google,coachz-sku0", "qcom,sc7180";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts
similarity index 75%
rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts
rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts
index 4f69b6b..a02d2d57 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts
@@ -2,7 +2,7 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
/dts-v1/;
@@ -10,6 +10,6 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev2+)";
+ model = "Google CoachZ (rev3+)";
compatible = "google,coachz", "qcom,sc7180";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
index 4c6e433..6f9c071 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
@@ -23,8 +23,53 @@
adau7002: audio-codec-1 {
compatible = "adi,adau7002";
IOVDD-supply = <&pp1800_l15a>;
+ wakeup-delay-ms = <15>;
#sound-dai-cells = <0>;
};
+
+ thermal-zones {
+ skin_temp_thermal: skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150_adc_tm 1>;
+ sustainable-power = <814>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <42000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <45000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <60000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
&ap_spi_fp {
@@ -77,6 +122,25 @@
compatible = "boe,nv110wtm-n61";
};
+&pm6150_adc {
+ skin-temp-thermistor@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ skin-temp-thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
index 5c997cd..30e3e769 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev0", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
index d9fbcc7..c2ef063 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts
index ea8c2ee..b474df4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts
@@ -14,12 +14,3 @@
model = "Google Lazor (rev3+)";
compatible = "google,lazor", "qcom,sc7180";
};
-
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
index 6b10b96..00535aa 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
@@ -21,6 +21,15 @@
semtech,avg-pos-strength = <64>;
};
+/*
+ * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
+ * not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
index e720e7b..e122a6b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
@@ -9,11 +9,23 @@
#include "sc7180-trogdor-pompom.dtsi"
+/delete-node/ &keyboard_controller;
+#include <arm/cros-ec-keyboard.dtsi>
+
/ {
model = "Google Pompom (rev1)";
compatible = "google,pompom-rev1", "qcom,sc7180";
};
+/*
+ * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts
index 791d496..00e187c 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts
@@ -9,6 +9,6 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google Pompom (rev2+) with LTE";
- compatible = "google,pompom-sku0", "qcom,sc7180";
+ model = "Google Pompom (rev2) with LTE";
+ compatible = "google,pompom-rev2-sku0", "qcom,sc7180";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
index 984d733..4f32e67 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
@@ -10,35 +10,15 @@
#include "sc7180-trogdor-pompom.dtsi"
/ {
- model = "Google Pompom (rev2+)";
- compatible = "google,pompom", "qcom,sc7180";
+ model = "Google Pompom (rev2)";
+ compatible = "google,pompom-rev2", "qcom,sc7180";
};
-&keyboard_controller {
- function-row-physmap = <
- MATRIX_KEY(0x00, 0x02, 0) /* T1 */
- MATRIX_KEY(0x03, 0x02, 0) /* T2 */
- MATRIX_KEY(0x02, 0x02, 0) /* T3 */
- MATRIX_KEY(0x01, 0x02, 0) /* T4 */
- MATRIX_KEY(0x03, 0x04, 0) /* T5 */
- MATRIX_KEY(0x02, 0x04, 0) /* T6 */
- MATRIX_KEY(0x01, 0x04, 0) /* T7 */
- MATRIX_KEY(0x02, 0x09, 0) /* T8 */
- MATRIX_KEY(0x01, 0x09, 0) /* T9 */
- MATRIX_KEY(0x00, 0x04, 0) /* T10 */
- >;
- linux,keymap = <
- MATRIX_KEY(0x00, 0x02, KEY_BACK)
- MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
- MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
- MATRIX_KEY(0x01, 0x02, KEY_SCALE)
- MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
- MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
- MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
- MATRIX_KEY(0x02, 0x09, KEY_MUTE)
- MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
- MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
- CROS_STD_MAIN_KEYMAP
- >;
+/*
+ * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts
new file mode 100644
index 0000000..e90b73c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "sc7180-trogdor-pompom-r3.dts"
+#include "sc7180-trogdor-lte-sku.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+) with LTE";
+ compatible = "google,pompom-sku0", "qcom,sc7180";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts
new file mode 100644
index 0000000..f8aac63
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-pompom.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+)";
+ compatible = "google,pompom", "qcom,sc7180";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
index 622b5f1..a246dbd 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
@@ -107,6 +107,35 @@
};
};
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
&panel {
compatible = "kingdisplay,kd116n21-30nv-a010";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 24d293e..77ae756 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -64,11 +64,6 @@
no-map;
};
- camera_mem: memory@8ec00000 {
- reg = <0x0 0x8ec00000 0x0 0x500000>;
- no-map;
- };
-
venus_mem: memory@8f600000 {
reg = <0 0x8f600000 0 0x500000>;
no-map;
@@ -335,8 +330,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
- /* TODO: Increase frequency after testing */
- spi-max-frequency = <25000000>;
+ spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
@@ -564,10 +558,6 @@
#size-cells = <0>;
};
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
-
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
@@ -655,6 +645,8 @@
clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -772,7 +764,7 @@
qcom,capture-sd-lines = <0>;
};
- mi2s@1 {
+ secondary_mi2s: mi2s@1 {
reg = <MI2S_SECONDARY>;
qcom,playback-sd-lines = <0>;
};
@@ -805,7 +797,7 @@
};
};
-&pm6150_pwrkey {
+&pm6150_pon {
status = "disabled";
};
@@ -981,6 +973,7 @@
&qspi_clk {
pinconf {
pins = "gpio63";
+ drive-strength = <8>;
bias-disable;
};
};
@@ -1494,4 +1487,106 @@
drive-strength = <2>;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6228ba2..a5d58eb 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -701,8 +701,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -726,15 +727,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <100000 100000>;
- opp-avg-kBps = <100000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <600000 900000>;
- opp-avg-kBps = <261438 300000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <390000 0>;
};
};
};
@@ -768,8 +769,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -1059,8 +1058,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -1871,108 +1868,6 @@
function = "lpass_ext";
};
};
-
- sdc1_on: sdc1-on {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc1_off: sdc1-off {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc2_on: sdc2-on {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- sdc2_off: sdc2-off {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-disable;
- drive-strength = <2>;
- };
- };
};
remoteproc_mpss: remoteproc@4080000 {
@@ -2670,8 +2565,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
@@ -2689,15 +2585,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <160000 100000>;
- opp-avg-kBps = <80000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <200000 120000>;
- opp-avg-kBps = <100000 60000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <200000 0>;
};
};
};
@@ -2754,8 +2650,8 @@
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
+ <0 0x088e8000 0 0x3c>,
+ <0 0x088ea000 0 0x18c>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -2860,7 +2756,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 54d2cb3..3900cfc 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -7,11 +7,19 @@
/dts-v1/;
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include "sc7280.dtsi"
+#include "pm7325.dtsi"
+#include "pmr735a.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
- compatible = "qcom,sc7280-idp", "qcom,sc7280";
+ compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280";
aliases {
serial0 = &uart5;
@@ -234,6 +242,32 @@
};
};
+&pmk8350_vadc {
+ pm8350_die_temp {
+ reg = <PM8350_ADC7_DIE_TEMP>;
+ label = "pm8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmk8350_die_temp {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735a_die_temp {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ label = "pmr735a_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735b_die_temp {
+ reg = <PMR735B_ADC7_DIE_TEMP>;
+ label = "pmr735b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2cc4785..a8c274a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -11,7 +11,10 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -51,6 +54,11 @@
no-map;
};
+ smem_mem: memory@80900000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ no-map;
+ };
+
cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -70,6 +78,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -88,6 +98,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -103,6 +115,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +132,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +149,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -148,6 +166,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -163,6 +183,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -178,6 +200,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -251,6 +275,125 @@
};
};
+ clk_virt: interconnect {
+ compatible = "qcom,sc7280-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ wpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -316,6 +459,93 @@
};
};
+ cnoc2: interconnect@1500000 {
+ reg = <0 0x01500000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc2";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc3: interconnect@1502000 {
+ reg = <0 0x01502000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc3";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@1580000 {
+ reg = <0 0x01580000 0 0x4>;
+ compatible = "qcom,sc7280-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ reg = <0 0x01680000 0 0x15480>;
+ compatible = "qcom,sc7280-system-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sc7280-aggre1-noc";
+ reg = <0 0x016e0000 0 0x1c080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ reg = <0 0x01700000 0 0x2b080>;
+ compatible = "qcom,sc7280-aggre2-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1740000 {
+ reg = <0 0x01740000 0 0x1e080>;
+ compatible = "qcom,sc7280-mmss-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex", "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+ <0 0x03c04000 0 0x4>,
+ <0 0x03389000 0 0x24>;
+ reg-names = "qdsp6ss", "top_cc", "cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ reg = <0 0x03c40000 0 0xf080>;
+ compatible = "qcom,sc7280-lpass-ag-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc7280-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
@@ -805,6 +1035,20 @@
};
};
+ dc_noc: interconnect@90e0000 {
+ reg = <0 0x090e0000 0 0x5080>;
+ compatible = "qcom,sc7280-dc-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ reg = <0 0x9100000 0 0xe2200>;
+ compatible = "qcom,sc7280-gem-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
@@ -812,6 +1056,42 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ nsp_noc: interconnect@a0c0000 {
+ reg = <0 0x0a0c0000 0 0x10000>;
+ compatible = "qcom,sc7280-nsp-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sc7280-videocc";
+ reg = <0 0xaaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sc7280-dispcc";
+ reg = <0 0xaf00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
@@ -825,6 +1105,40 @@
interrupt-controller;
};
+ pdc_reset: reset-controller@b5e0000 {
+ compatible = "qcom,sc7280-pdc-global";
+ reg = <0 0x0b5e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <12>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
@@ -1063,6 +1377,10 @@
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
rpmhpd: power-controller {
compatible = "qcom,sc7280-rpmhpd";
#power-domain-cells = <1>;
@@ -1116,6 +1434,859 @@
#clock-cells = <1>;
};
};
+
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu0_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu1_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu2_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu3_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu4_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu5_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu6_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu7_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu8-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu8_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu8_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu8_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu9-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu9_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu9_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu9_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu10-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu10_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu10_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu10_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu11-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu11_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu11_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu11_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0_crit: aoss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss1_crit: aoss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss0_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss1_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss0_crit: gpuss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss1_crit: gpuss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ nspss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss0_crit: nspss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ nspss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss1_crit: nspss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ video_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video_crit: video-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ ddr_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ ddr_crit: ddr-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ mdmss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss0_crit: mdmss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ mdmss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss1_crit: mdmss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ mdmss2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss2_crit: mdmss2-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ mdmss3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss3_crit: mdmss3-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ camera0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0_crit: camera0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
};
timer {
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
index 216a74f..dfd1b42 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
@@ -714,10 +714,6 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 1372fe8..91ede92 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -448,6 +448,11 @@
clock-frequency = <400000>;
};
+&ipa {
+ status = "okay";
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
index 8f617f7..4d052e3 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
@@ -46,6 +46,14 @@
};
reserved-memory {
+ /* The rmtfs_mem needs to be guarded due to "XPU limitations"
+ * it is otherwise possible for an allocation adjacent to the
+ * rmtfs_mem region to trigger an XPU violation, causing a crash.
+ */
+ rmtfs_lower_guard: memory@f5b00000 {
+ no-map;
+ reg = <0 0xf5b00000 0 0x1000>;
+ };
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
* but given the same address every time. Hard code it as this address is
@@ -59,6 +67,10 @@
qcom,client-id = <1>;
qcom,vmid = <15>;
};
+ rmtfs_upper_guard: memory@f5d01000 {
+ no-map;
+ reg = <0 0xf5d01000 0 0x2000>;
+ };
/*
* It seems like reserving the old rmtfs_mem region is also needed to prevent
@@ -387,6 +399,12 @@
};
};
+&ipa {
+ status = "okay";
+
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
index 7d02942..c60c8c6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
@@ -5,6 +5,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
@@ -311,6 +313,28 @@
};
};
+/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */
+&q6afedai {
+ qi2s@22 {
+ reg = <22>;
+ qcom,sd-lines = <0>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -328,6 +352,70 @@
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
};
+&sound {
+ compatible = "qcom,db845c-sndcard";
+ pinctrl-0 = <&quat_mi2s_active
+ &quat_mi2s_sd0_active>;
+ pinctrl-names = "default";
+ model = "Xiaomi Poco F1";
+ audio-routing =
+ "RX_BIAS", "MCLK",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 0>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 1>;
+ };
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
@@ -356,6 +444,15 @@
function = "gpio";
bias-pull-up;
};
+
+ wcd_intr_default: wcd_intr_default {
+ pins = <54>;
+ function = "gpio";
+
+ input-enable;
+ bias-pull-down;
+ drive-strength = <2>;
+ };
};
&uart6 {
@@ -416,6 +513,23 @@
vdda-pll-supply = <&vreg_l1a_0p875>;
};
+&wcd9340{
+ pinctrl-0 = <&wcd_intr_default>;
+ pinctrl-names = "default";
+ clock-names = "extclk";
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ reset-gpios = <&tlmm 64 0>;
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
+ qcom,micbias1-microvolt = <2700000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <2700000>;
+ qcom,micbias4-microvolt = <2700000>;
+};
+
&wifi {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe7..1796ae8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3781,7 +3781,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -3829,7 +3829,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_2_dwc3: dwc3@a800000 {
+ usb_2_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
index 140db2d..c2a709a 100644
--- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
@@ -376,6 +376,8 @@
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
index fb2cf3d..335aa07 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
@@ -354,22 +354,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
new file mode 100644
index 0000000..736da9a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (C) 2021, Microsoft Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/ {
+ model = "Microsoft Surface Duo";
+ compatible = "microsoft,surface-duo", "qcom,sm8150";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ vol_up {
+ label = "Volume Up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s5a_2p0: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vdda_wcss_pll:
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_pdphy:
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_csi_0_0p9:
+ vdda_csi_1_0p9:
+ vdda_csi_2_0p9:
+ vdda_csi_3_0p9:
+ vdda_dsi_0_0p9:
+ vdda_dsi_1_0p9:
+ vdda_dsi_0_pll_0p9:
+ vdda_dsi_1_pll_0p9:
+ vdda_pcie_1ln_core:
+ vdda_pcie_2ln_core:
+ vdda_pll_hv_cc_ebi01:
+ vdda_pll_hv_cc_ebi23:
+ vdda_qrefs_0p875_5:
+ vdda_sp_sensor:
+ vdda_ufs_2ln_core_1:
+ vdda_ufs_2ln_core_2:
+ vdda_usb_ss_dp_core_1:
+ vdda_usb_ss_dp_core_2:
+ vdda_qlink_lv:
+ vdda_qlink_lv_ck:
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_10:
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_qfprom:
+ vdd_qfprom_sp:
+ vdda_apc_cs_1p8:
+ vdda_gfx_cs_1p8:
+ vdda_usb_hs_1p8:
+ vdda_qrefs_vref_1p8:
+ vddpx_10_a:
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_wcss_adcdac_1:
+ vdda_wcss_adcdac_22:
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_hv_ebi0:
+ vdda_hv_ebi1:
+ vdda_hv_ebi2:
+ vdda_hv_ebi3:
+ vdda_hv_refgen0:
+ vdda_qlink_hv_ck:
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_5:
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_6:
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_2:
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+
+ vdd-l2-supply = <&vreg_s8c_1p3>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f_2p85: ldo5 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p85: ldo6 {
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <2856000>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+
+ da7280@4a {
+ compatible = "dlg,da7280";
+ reg = <0x4a>;
+ interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "da7280_default";
+ pinctrl-0 = <&da7280_intr_default>;
+
+ dlg,actuator-type = "LRA";
+ dlg,dlg,const-op-mode = <1>;
+ dlg,dlg,periodic-op-mode = <1>;
+ dlg,nom-microvolt = <2000000>;
+ dlg,abs-max-microvolt = <2000000>;
+ dlg,imax-microamp = <129000>;
+ dlg,resonant-freq-hz = <180>;
+ dlg,impd-micro-ohms = <14300000>;
+ dlg,freq-track-enable;
+ dlg,bemf-sens-enable;
+ dlg,mem-array = <
+ 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a
+ 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29
+ 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01
+ 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06
+ 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08
+ 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84
+ 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e
+ 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ >;
+ };
+
+ /* SMB1381 @ 0x44 */
+ /* MAX34417 @ 0x1c */
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* SMB1355 @ 0x0c */
+ /* SMB1390 @ 0x10 */
+};
+
+&i2c17 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+};
+
+&i2c19 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* MAX34417 @ 0x12 */
+ /* MAX34417 @ 0x1a */
+ /* MAX34417 @ 0x1e */
+};
+
+&pon {
+ pwrkey {
+ status = "okay";
+ };
+
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/adsp.mdt";
+};
+
+&remoteproc_cdsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/cdsp.mdt";
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/modem.mdt";
+};
+
+&remoteproc_slpi {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/slpi.mdt";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+
+ da7280_intr_default: da7280-intr-default {
+ pins = "gpio42";
+ function = "gpio";
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p5>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l9a_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
+ vdda-max-microamp = <90200>;
+ vdda-pll-supply = <&vreg_l3c_1p2>;
+ vdda-pll-max-microamp = <19000>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&wifi {
+ status = "okay";
+
+ vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>;
+ vdd-3.3-ch0-supply = <&vreg_l11c_3p3>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
index 3774f8e..53edf754 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -349,22 +349,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts
new file mode 100644
index 0000000..3b55fdd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 5";
+ compatible = "sony,bahamut-generic", "qcom,sm8150";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts
new file mode 100644
index 0000000..6f490ec2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 1";
+ compatible = "sony,griffin-generic", "qcom,sm8150";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
new file mode 100644
index 0000000..014fe3a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &venus_mem;
+
+/ {
+ qcom,msm-id = <339 0x20000>; /* SM8150 v2 */
+ qcom,board-id = <8 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's (going to be) a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet (& no dispcc either)..
+ */
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ mpss_mem: memory@8dc00000 {
+ reg = <0x0 0x8dc00000 0x0 0x9600000>;
+ no-map;
+ };
+
+ venus_mem: memory@97200000 {
+ reg = <0x0 0x97200000 0x0 0x500000>;
+ no-map;
+ };
+
+ slpi_mem: memory@97700000 {
+ reg = <0x0 0x97700000 0x0 0x1400000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@98b00000 {
+ reg = <0x0 0x98b00000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@98b10000 {
+ reg = <0x0 0x98b10000 0x0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: memory@98b15000 {
+ reg = <0x0 0x98b15000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: memory@98c00000 {
+ reg = <0x0 0x98c00000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: memory@98d00000 {
+ reg = <0x0 0x98d00000 0x0 0x1400000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2400000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@a4c00000 {
+ reg = <0x0 0xa4c00000 0x0 0x3c00000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp_mem {
+ reg = <0x0 0x8be00000 0x0 0x1e00000>;
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s2a_0p6: smps2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p8: ldo18 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s1c_1p1: smps1 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /* PM8009 is not present on these boards, even if downstream sources suggest so. */
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Qcom SMB1355 @ c */
+ /* Qcom SMB1390 @ 10 */
+ /* NXP PN553 NFC @ 28 */
+ /* Qcom FSA4480 USB-C audio switch @ 43 */
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c10 {
+ status = "okay";
+
+ /* Samsung touchscreen @ 48 */
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l5a_0p875>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p8>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 51235a9..612dda0 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -577,6 +578,29 @@
<&sleep_clk>;
};
+ gpi_dma0: dma-controller@800000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0x800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x00d6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -695,6 +719,29 @@
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xa00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x0616 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -795,6 +842,29 @@
};
};
+ gpi_dma2: dma-controller@c00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xc00000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x07b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@cc0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00cc0000 0x0 0x6000>;
@@ -1082,6 +1152,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1149,6 +1221,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1496,6 +1570,8 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ status = "disabled";
+
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
@@ -2268,7 +2344,7 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index c3a2c5a..4774281 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include <dt-bindings/gpio/gpio.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -365,22 +364,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&tlmm {
@@ -452,3 +455,7 @@
&usb_2_dwc3 {
dr_mode = "host";
};
+
+&venus {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
index cfc4d1f..062b944 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
@@ -465,7 +465,13 @@
firmware-name = "qcom/sm8250/cdsp.mbn";
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -691,3 +697,7 @@
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p9>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts
new file mode 100644
index 0000000..79afeb0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 1 II";
+ compatible = "sony,pdx203-generic", "qcom,sm8250";
+};
+
+/delete-node/ &vreg_l7f_1p8;
diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
new file mode 100644
index 0000000..16c96e8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 5 II";
+ compatible = "sony,pdx206-generic", "qcom,sm8250";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
+
+&gpio_keys {
+ g-assist-key {
+ label = "Google Assistant Key";
+ linux,code = <KEY_LEFTMETA>;
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+};
+
+&vreg_l2f_1p3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
new file mode 100644
index 0000000..d63f7a9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8250.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+/delete-node/ &adsp_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &cdsp_secure_heap;
+
+/ {
+ qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */
+ qcom,board-id = <0x10008 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet..
+ */
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ power-domains = <&dispcc MDSS_GDSC>;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ /*
+ * Camera focus (light press) and camera snapshot (full press)
+ * seem not to work properly.. Adding the former one stalls the CPU
+ * and the latter kills the volume down key for whatever reason. In any
+ * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1).
+ */
+
+ vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S6c is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s6c_0p88: smpc6-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s6c_0p88";
+
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ adsp_mem: memory@8a100000 {
+ reg = <0x0 0x8a100000 0x0 0x2500000>;
+ no-map;
+ };
+
+ spss_mem: memory@8c600000 {
+ reg = <0x0 0x8c600000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap: memory@8c700000 {
+ reg = <0x0 0x8c700000 0x0 0x4600000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2300000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p2>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ /* (S1+S2+S3) - cx.lvl (ARC) */
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-name = "vreg_s5a_1p9";
+ regulator-min-microvolt = <1824000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p6: smps6 {
+ regulator-name = "vreg_s6a_0p6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-name = "vreg_l2a_3p1";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p9: ldo3 {
+ regulator-name = "vreg_l3a_0p9";
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L4 - lmx.lvl (ARC) */
+
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L7 is unused. */
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-name = "vreg_l9a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L10 is unused, L11 - lcx.lvl (ARC) */
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L15 & L16 are unused. */
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-name = "vreg_l17a_3p0";
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p9: ldo18 {
+ regulator-name = "vreg_l18a_0p9";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /*
+ * Remaining regulators that are not yet supported:
+ * OLEDB: 4925000-8100000
+ * ab: 4600000-6100000
+ * ibb: 800000-5400000
+ */
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p2>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ /*
+ * S1-S6 are ARCs:
+ * (S1+S2) - gfx.lvl,
+ * S3 - mx.lvl,
+ * (S4+S5) - mmcx.lvl,
+ * S6 - ebi.lvl
+ */
+
+ vreg_s7c_0p35: smps7 {
+ regulator-name = "vreg_s7c_0p35";
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p2: smps8 {
+ regulator-name = "vreg_s8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L2-4 are unused. */
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-name = "vreg_l5c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-name = "vreg_l6c_2p9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_2p85: ldo7 {
+ regulator-name = "vreg_l7c_2p85";
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-name = "vreg_l9c_2p9";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3296000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p0: ldo11 {
+ regulator-name = "vreg_l11c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+ vdd-l2-supply = <&vreg_s8c_1p2>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_s4a_1p8>;
+
+ vreg_s1f_1p2: smps1 {
+ regulator-name = "vreg_s1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2f_0p5: smps2 {
+ regulator-name = "vreg_s2f_0p5";
+ regulator-min-microvolt = <512000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L1 is unused. */
+
+ vreg_l2f_1p3: ldo2 {
+ regulator-name = "vreg_l2f_1p3";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L3 & L4 are unused. */
+
+ vreg_l5f_2p8: ldo5 {
+ regulator-name = "vreg_l5f_2p85";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p8: ldo6 {
+ regulator-name = "vreg_l6f_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f_1p8: ldo7 {
+ regulator-name = "vreg_l7f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&cdsp {
+ status = "okay";
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* NXP PN553 NFC @ 28 */
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Dialog SLG51000 CMIC @ 75 */
+};
+
+&i2c9 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c13 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ /* It's "vddio" downstream but it works anyway! */
+ vdd-supply = <&vreg_l1c_1p8>;
+ avdd-supply = <&vreg_l10c_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_default>;
+ };
+};
+
+&i2c15 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Qcom SMB1390 @ 10 */
+ /* Silicon Labs SI4704 FM Radio Receiver @ 11 */
+ /* Qcom SMB1390_slave @ 18 */
+ /* HALO HL6111R Qi charger @ 25 */
+ /* Richwave RTC6226 FM Radio Receiver @ 64 */
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pcie2 {
+ status = "okay";
+
+ pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>;
+};
+
+&pcie2_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEUP>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9c_2p9>;
+ vqmmc-supply = <&vreg_l6c_2p9>;
+ bus-width = <4>;
+ no-sdio;
+ no-emmc;
+};
+
+&slpi {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <40 4>, <52 4>;
+
+ sdc2_default_state: sdc2-default {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ mdm2ap_default: mdm2ap-default {
+ pins = "gpio1", "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default {
+ pins = "gpio39";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disabled;
+ input-enable;
+ };
+
+ ap2mdm_default: ap2mdm-default {
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sdc2_card_det_n: sd-card-det-n {
+ pins = "gpio77";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&uart12 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l9a_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p9>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4c0de12..4798368 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -519,6 +521,26 @@
};
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00800000 0 0x70000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x76 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -714,6 +736,29 @@
};
};
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00900000 0 0x70000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <15>;
+ dma-channel-mask = <0x7ff>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -961,6 +1006,26 @@
};
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00a00000 0 0x70000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -1249,6 +1314,12 @@
phys = <&pcie0_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
status = "disabled";
};
@@ -1347,6 +1418,12 @@
phys = <&pcie1_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
status = "disabled";
};
@@ -1447,6 +1524,12 @@
phys = <&pcie2_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_default_state>;
+
status = "disabled";
};
@@ -1470,7 +1553,7 @@
status = "disabled";
- pcie2_lane: lanes@1c0e200 {
+ pcie2_lane: lanes@1c16200 {
reg = <0 0x1c16200 0 0x170>, /* tx0 */
<0 0x1c16400 0 0x200>, /* rx0 */
<0 0x1c16a00 0 0x1f0>, /* pcs */
@@ -1746,6 +1829,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1819,6 +1904,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2323,6 +2410,8 @@
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "bus", "core";
+ status = "disabled";
+
video-decoder {
compatible = "venus-decoder";
};
@@ -2370,7 +2459,7 @@
};
mdss: mdss@ae00000 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
@@ -2402,7 +2491,7 @@
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2424,8 +2513,6 @@
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2499,6 +2586,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2566,6 +2656,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -3395,6 +3488,95 @@
output-high;
};
};
+
+ sdc2_sleep_state: sdc2-sleep {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_default_state: pcie0-default {
+ perst {
+ pins = "gpio79";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio80";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default {
+ perst {
+ pins = "gpio82";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio83";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio84";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_default_state: pcie2-default {
+ perst {
+ pins = "gpio85";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio86";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
apps_smmu: iommu@15000000 {
diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
index 6ca638b..9374044 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
@@ -364,3 +364,9 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l5b_0p88>;
};
+
+&ipa {
+ status = "okay";
+
+ memory-region = <&pil_ipa_fw_mem>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index ed0b51b..0d16392 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -6,11 +6,13 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
/ {
interrupt-parent = <&intc>;
@@ -391,6 +393,17 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
smp2p-slpi {
@@ -629,6 +642,45 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ipa: ipa@1e40000 {
+ compatible = "qcom,sm8350-ipa";
+
+ iommus = <&apps_smmu 0x5c0 0x0>,
+ <&apps_smmu 0x5c2 0x0>;
+ reg = <0 0x1e40000 0 0x8000>,
+ <0 0x1e50000 0 0x4b20>,
+ <0 0x1e04000 0 0x23000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
+ <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+ interconnect-names = "ipa_to_llcc",
+ "llcc_to_ebi1",
+ "appss_to_ipa";
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -656,7 +708,7 @@
<&rpmhpd 12>;
power-domain-names = "load_state", "cx", "mss";
- interconnects = <&mc_virt 0 &mc_virt 1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
@@ -689,7 +741,7 @@
interrupt-controller;
};
- tsens0: thermal-sensor@c222000 {
+ tsens0: thermal-sensor@c263000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
@@ -700,7 +752,7 @@
#thermal-sensor-cells = <1>;
};
- tsens1: thermal-sensor@c223000 {
+ tsens1: thermal-sensor@c265000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
@@ -1063,7 +1115,7 @@
<&rpmhpd 10>;
power-domain-names = "load_state", "cx", "mxc";
- interconnects = <&compute_noc 1 &mc_virt 1>;
+ interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
@@ -1176,7 +1228,7 @@
};
};
- dc_noc: interconnect@90e0000 {
+ dc_noc: interconnect@90c0000 {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c0000 0 0x4200>;
#interconnect-cells = <1>;
@@ -1317,7 +1369,7 @@
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index f2de2fa..68e30e2 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -62,3 +62,5 @@
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
+
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index d8046fe..e3c8b2f 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
@@ -271,12 +271,12 @@
&ehci0 {
dr_mode = "otg";
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&hdmi0 {
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index 8d3a4d6..090dc9c4 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
@@ -53,6 +53,8 @@
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
+ clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+ clock-names = "fck", "refclk";
status = "okay";
phy0: ethernet-phy@0 {
@@ -319,8 +321,10 @@
status = "okay";
};
-&usb_extal_clk {
- clock-frequency = <50000000>;
+&usb2_clksel {
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&versaclock5 3>, <&usb3s0_clk>;
+ status = "okay";
};
&usb3s0_clk {
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 46f8dbf..78c121a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -76,6 +76,7 @@
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
};
@@ -1127,6 +1128,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index d16a4be..28c612c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1001,6 +1001,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 1aef344..a5d4dce 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -957,6 +957,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 1f51237..379a130 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1230,6 +1230,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 85d66d1..2e4c18b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -1312,6 +1312,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index 12476e3..2bd8169 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -63,18 +63,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -1188,6 +1189,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index d980476..91b501e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -52,18 +52,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -559,10 +560,19 @@
};
intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77961", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
- /* placeholder */
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
@@ -1144,6 +1154,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index dcb9df8..ad69da3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1050,6 +1050,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 874a7fc..5c84681 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -73,6 +73,12 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ x1_clk: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
};
&avb {
@@ -104,6 +110,8 @@
};
&du {
+ clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
+ clock-names = "du.0", "dclkin.0";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 7417cf5..2426e53 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -59,7 +59,7 @@
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
+ reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc5_clk: osc5-clock {
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index e8f6352..517892c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -612,6 +612,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 04d47c0..7bde0a5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -210,7 +210,7 @@
&mmc0 {
pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins_uhs>;
+ pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
@@ -255,12 +255,6 @@
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
- power-source = <3300>;
- };
-
- mmc_pins_uhs: mmc_uhs {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
power-source = <1800>;
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 7b51d46..6347d15 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -664,6 +664,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 0eaea58..4d0304bc 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1000,6 +1000,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 2319271..84dba37 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -760,6 +760,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
index 14d3db5d..f791c76 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
@@ -6,6 +6,27 @@
*/
&i2c0 {
+ pca9654_a: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_b: gpio@22 {
+ compatible = "onnn,pca9654";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_c: gpio@23 {
+ compatible = "onnn,pca9654";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 70b3604..78ca75f 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -618,6 +618,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 211>;
phy-mode = "rgmii";
@@ -665,6 +666,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 212>;
phy-mode = "rgmii";
@@ -712,6 +714,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 213>;
phy-mode = "rgmii";
@@ -759,6 +762,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 214>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 214>;
phy-mode = "rgmii";
@@ -806,6 +810,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 215>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 215>;
phy-mode = "rgmii";
@@ -853,6 +858,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 216>;
phy-mode = "rgmii";
@@ -1096,7 +1102,6 @@
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
fcpvd0: fcp@fea10000 {
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
new file mode 100644
index 0000000..734c8ad
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g044-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g044";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_CLK_SCIF0>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g044-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
new file mode 100644
index 0000000..9d89d45
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
new file mode 100644
index 0000000..d3f72ec
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
new file mode 100644
index 0000000..91dc10b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
new file mode 100644
index 0000000..adcd4f5
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index c3e00c0e..7fdb41d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -51,3 +51,4 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 09baa8a..248ebb6 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -244,28 +244,31 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -277,15 +280,17 @@
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -300,8 +305,9 @@
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -311,11 +317,13 @@
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -814,7 +822,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -1087,7 +1095,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1128,7 +1135,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
index 3dddd47..665b2e6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
@@ -84,8 +84,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
vin-supply = <&vcc5v0_sys>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index b815ce7..a185901 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -164,7 +164,7 @@
grf: grf@ff000000 {
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x10000>;
+ reg = <0x0 0xff000000 0x0 0x08000>;
reboot-mode {
compatible = "syscon-reboot-mode";
@@ -177,6 +177,42 @@
};
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
detect_grf: syscon@ff00b000 {
compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
@@ -579,6 +615,42 @@
status = "disabled";
};
+ usb20_otg: usb@ff400000 {
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index 49c97f7..7fc674a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -165,6 +165,31 @@
};
};
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+ };
+
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
@@ -239,6 +264,7 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
port {
@@ -269,11 +295,14 @@
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "xin32k";
+ #sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
@@ -432,6 +461,10 @@
};
};
};
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
index f807bc0..3857d48 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
@@ -76,8 +77,8 @@
regulator-settling-time-us = <5000>;
regulator-type = "voltage";
startup-delay-us = <2000>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
vin-supply = <&vcc_io_33>;
};
@@ -101,6 +102,18 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vdd_5v_lan: vdd-5v-lan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&lan_vdd_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_5v_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
};
&cpu0 {
@@ -309,6 +322,12 @@
};
};
+ lan {
+ lan_vdd_pin: lan-vdd-pin {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -368,6 +387,19 @@
dr_mode = "host";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Second port is for USB 3.0 */
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
+ };
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index a05732b..aa22a0c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -50,8 +50,8 @@
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
@@ -363,6 +363,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
index c7e31ef..018a3a5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
@@ -177,8 +177,6 @@
};
&gmac2phy {
- pinctrl-names = "default";
- pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>;
status = "okay";
};
@@ -382,6 +380,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 3bef1f3..1b0f7e4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -381,6 +381,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 3ed69ec..8c821ac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -288,7 +288,7 @@
status = "disabled";
};
- grf_gpio: grf-gpio {
+ grf_gpio: gpio {
compatible = "rockchip,rk3328-grf-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -300,15 +300,18 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_hevc@RK3328_PD_HEVC {
+ power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3328_PD_VIDEO {
+ power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ #power-domain-cells = <0>;
};
- pd_vpu@RK3328_PD_VPU {
+ power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ #power-domain-cells = <0>;
};
};
@@ -816,7 +819,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,rk3328-usb2phy";
reg = <0x100 0x10>;
clocks = <&xin24m>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index dfc6376..4c64fbe 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -664,6 +664,8 @@
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
+ clock-names = "pclk", "timer";
};
spdif: spdif@ff880000 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 45254be1..c4dd2a6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -94,6 +95,13 @@
};
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -151,6 +159,23 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+ sound-dit {
+ compatible = "audio-graph-card";
+ label = "SPDIF";
+ dais = <&spdif_p0>;
+ };
+
+ spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port {
+ dit_p0_0: endpoint {
+ remote-endpoint = <&spdif_p0_0>;
+ };
+ };
+ };
+
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@@ -196,6 +221,17 @@
vin-supply = <&vcc_sys>;
};
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -521,6 +557,53 @@
i2c-scl-falling-time-ns = <20>;
status = "okay";
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vcc5v0_typec>;
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "host";
+ label = "USB-C";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos =
+ <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usbc_hs: endpoint {
+ remote-endpoint =
+ <&u2phy0_typec_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usbc_ss: endpoint {
+ remote-endpoint =
+ <&tcphy0_typec_ss>;
+ };
+ };
+ };
+ };
+ };
+
accelerometer@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
@@ -578,12 +661,34 @@
};
};
+ fusb302x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+ leds {
+ work_led_pin: work-led-pin {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_pin: diy-led-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -595,6 +700,10 @@
};
pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
@@ -604,21 +713,21 @@
};
};
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
rt5640 {
rt5640_hpcon: rt5640-hpcon {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0_typec_en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -633,16 +742,6 @@
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- leds {
- work_led_pin: work-led-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_pin: diy-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
};
&pwm0 {
@@ -710,10 +809,29 @@
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdif_bus_1>;
+ status = "okay";
+
+ spdif_p0: port {
+ spdif_p0_0: endpoint {
+ remote-endpoint = <&dit_p0_0>;
+ };
+ };
+};
+
&tcphy0 {
status = "okay";
};
+&tcphy0_usb3 {
+ port {
+ tcphy0_typec_ss: endpoint {
+ remote-endpoint = <&usbc_ss>;
+ };
+ };
+};
+
&tcphy1 {
status = "okay";
};
@@ -737,6 +855,12 @@
phy-supply = <&vcc5v0_host>;
status = "okay";
};
+
+ port {
+ u2phy0_typec_hs: endpoint {
+ remote-endpoint = <&usbc_hs>;
+ };
+ };
};
&u2phy1 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index beee5fb..5d7a9d9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -245,7 +245,7 @@
};
&ppvar_sd_card_io {
- states = <1800000 0x0 3300000 0x1>;
+ states = <1800000 0x0>, <3300000 0x1>;
regulator-max-microvolt = <3300000>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 4002742..c1bcc8c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -252,8 +252,8 @@
enable-active-high;
enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3000000 0x0>;
+ states = <1800000 0x1>,
+ <3000000 0x0>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
index 19485b5..738cfd2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
@@ -23,6 +23,16 @@
mmc1 = &sdhci;
};
+ avdd_0v9_s0: avdd-0v9-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_0v9_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc1v8_sys_s3>;
+ };
+
avdd_1v8_s0: avdd-1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "avdd_1v8_s0";
@@ -40,6 +50,20 @@
#clock-cells = <0>;
};
+ fan1 {
+ /* fan connected to P7 */
+ compatible = "pwm-fan";
+ pwms = <&pwm0 0 40000 0>;
+ cooling-levels = <0 80 170 255>;
+ };
+
+ fan2 {
+ /* fan connected to P6 */
+ compatible = "pwm-fan";
+ pwms = <&pwm1 0 40000 0>;
+ cooling-levels = <0 80 170 255>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -58,6 +82,18 @@
};
};
+ pcie_power: pcie-power {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie_pwr>;
+ pinctrl-names = "default";
+ regulator-boot-on;
+ regulator-name = "pcie_power";
+ startup-delay-us = <10000>;
+ vin-supply = <&vcc5v0_perdev>;
+ };
+
vcc1v8_sys_s0: vcc1v8-sys-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys_s0";
@@ -95,6 +131,16 @@
};
};
+ vcc5v0_perdev: vcc5v0-perdev {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_perdev";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin_bkup>;
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -109,6 +155,20 @@
};
};
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_en>;
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_perdev>;
+ };
+
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -317,6 +377,20 @@
status = "okay";
};
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ num-lanes = <2>;
+ status = "okay";
+
+ vpcie12v-supply = <&vcc12v_dcin>;
+ vpcie3v3-supply = <&pcie_power>;
+ vpcie1v8-supply = <&avdd_1v8_s0>;
+ vpcie0v9-supply = <&avdd_0v9_s0>;
+};
+
&pinctrl {
gmac {
gphy_reset: gphy-reset {
@@ -334,12 +408,25 @@
};
};
+ pcie {
+ pcie_pwr: pcie-pwr {
+ rockchip,pins =
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+ power {
+ vcc5v0_usb_en: vcc5v0-usb-en {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
vcc3v0-sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -352,6 +439,16 @@
status = "okay";
};
+&pwm0 {
+ /* pwm-fan on P7 */
+ status = "okay";
+};
+
+&pwm1 {
+ /* pwm-fan on P6 */
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
@@ -372,6 +469,30 @@
status = "okay";
};
+&tcphy1 {
+ /* phy for &usbdrd_dwc3_1 */
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+
+ otg-port {
+ /* phy for &usbdrd_dwc3_1 */
+ phy-supply = <&vcc5v0_usb>;
+ status = "okay";
+ };
+};
+
&uart2 {
status = "okay";
};
+
+&usbdrd3_1 {
+ status = "okay";
+
+ usb@fe900000 {
+ dr_mode = "host";
+ status = "okay";
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index fa58098..cef4d18 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -33,7 +33,7 @@
sys_led: led-sys {
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- label = "red:sys";
+ label = "red:power";
default-state = "on";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 16fd58c..8c0ff6c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -510,7 +510,6 @@
};
&pcie0 {
- max-link-speed = <2>;
num-lanes = <2>;
vpcie0v9-supply = <&vcca0v9_s3>;
vpcie1v8-supply = <&vcca1v8_s3>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index c172f5a..d1aaf8e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -63,6 +63,13 @@
};
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -389,6 +396,7 @@
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
+ regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
@@ -493,6 +501,8 @@
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
@@ -601,6 +611,12 @@
};
};
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
index 7d0a7c69..b28888e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
@@ -474,7 +474,6 @@
&pcie0 {
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4b854eb..3871c7f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -968,126 +968,146 @@
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
- pd_iep@RK3399_PD_IEP {
+ power-domain@RK3399_PD_IEP {
reg = <RK3399_PD_IEP>;
clocks = <&cru ACLK_IEP>,
<&cru HCLK_IEP>;
pm_qos = <&qos_iep>;
+ #power-domain-cells = <0>;
};
- pd_rga@RK3399_PD_RGA {
+ power-domain@RK3399_PD_RGA {
reg = <RK3399_PD_RGA>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_rga_r>,
<&qos_rga_w>;
+ #power-domain-cells = <0>;
};
- pd_vcodec@RK3399_PD_VCODEC {
+ power-domain@RK3399_PD_VCODEC {
reg = <RK3399_PD_VCODEC>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video_m0>;
+ #power-domain-cells = <0>;
};
- pd_vdu@RK3399_PD_VDU {
+ power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
+ #power-domain-cells = <0>;
};
/* These power domains are grouped by VD_GPU */
- pd_gpu@RK3399_PD_GPU {
+ power-domain@RK3399_PD_GPU {
reg = <RK3399_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
/* These power domains are grouped by VD_LOGIC */
- pd_edp@RK3399_PD_EDP {
+ power-domain@RK3399_PD_EDP {
reg = <RK3399_PD_EDP>;
clocks = <&cru PCLK_EDP_CTRL>;
+ #power-domain-cells = <0>;
};
- pd_emmc@RK3399_PD_EMMC {
+ power-domain@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
pm_qos = <&qos_emmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@RK3399_PD_GMAC {
+ power-domain@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_sd@RK3399_PD_SD {
+ power-domain@RK3399_PD_SD {
reg = <RK3399_PD_SD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
+ #power-domain-cells = <0>;
};
- pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+ power-domain@RK3399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
clocks = <&cru HCLK_SDIO>;
pm_qos = <&qos_sdioaudio>;
+ #power-domain-cells = <0>;
};
- pd_tcpc0@RK3399_PD_TCPD0 {
+ power-domain@RK3399_PD_TCPD0 {
reg = <RK3399_PD_TCPD0>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
+ #power-domain-cells = <0>;
};
- pd_tcpc1@RK3399_PD_TCPD1 {
+ power-domain@RK3399_PD_TCPD1 {
reg = <RK3399_PD_TCPD1>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
+ #power-domain-cells = <0>;
};
- pd_usb3@RK3399_PD_USB3 {
+ power-domain@RK3399_PD_USB3 {
reg = <RK3399_PD_USB3>;
clocks = <&cru ACLK_USB3>;
pm_qos = <&qos_usb_otg0>,
<&qos_usb_otg1>;
+ #power-domain-cells = <0>;
};
- pd_vio@RK3399_PD_VIO {
+ power-domain@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
+ #power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- pd_hdcp@RK3399_PD_HDCP {
+ power-domain@RK3399_PD_HDCP {
reg = <RK3399_PD_HDCP>;
clocks = <&cru ACLK_HDCP>,
<&cru HCLK_HDCP>,
<&cru PCLK_HDCP>;
pm_qos = <&qos_hdcp>;
+ #power-domain-cells = <0>;
};
- pd_isp0@RK3399_PD_ISP0 {
+ power-domain@RK3399_PD_ISP0 {
reg = <RK3399_PD_ISP0>;
clocks = <&cru ACLK_ISP0>,
<&cru HCLK_ISP0>;
pm_qos = <&qos_isp0_m0>,
<&qos_isp0_m1>;
+ #power-domain-cells = <0>;
};
- pd_isp1@RK3399_PD_ISP1 {
+ power-domain@RK3399_PD_ISP1 {
reg = <RK3399_PD_ISP1>;
clocks = <&cru ACLK_ISP1>,
<&cru HCLK_ISP1>;
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
+ #power-domain-cells = <0>;
};
- pd_vo@RK3399_PD_VO {
+ power-domain@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
+ #power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- pd_vopb@RK3399_PD_VOPB {
+ power-domain@RK3399_PD_VOPB {
reg = <RK3399_PD_VOPB>;
clocks = <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>;
pm_qos = <&qos_vop_big_r>,
<&qos_vop_big_w>;
+ #power-domain-cells = <0>;
};
- pd_vopl@RK3399_PD_VOPL {
+ power-domain@RK3399_PD_VOPL {
reg = <RK3399_PD_VOPL>;
clocks = <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
pm_qos = <&qos_vop_little>;
+ #power-domain-cells = <0>;
};
};
};
@@ -1398,7 +1418,7 @@
status = "disabled";
};
- u2phy0: usb2-phy@e450 {
+ u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
@@ -1425,7 +1445,7 @@
};
};
- u2phy1: usb2-phy@e460 {
+ u2phy1: usb2phy@e460 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe460 0x10>;
clocks = <&cru SCLK_USB2PHY1_REF>;
@@ -2354,7 +2374,7 @@
};
};
- sleep {
+ suspend {
ap_pwroff: ap-pwroff {
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index c0074b3..01d1a75 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -329,7 +329,6 @@
&pcie0 {
ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
new file mode 100644
index 0000000..6978655
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+ compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
new file mode 100644
index 0000000..a588ca9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
@@ -0,0 +1,3111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ acodec {
+ /omit-if-no-ref/
+ acodec_pins: acodec-pins {
+ rockchip,pins =
+ /* acodec_adc_sync */
+ <1 RK_PB1 5 &pcfg_pull_none>,
+ /* acodec_adcclk */
+ <1 RK_PA1 5 &pcfg_pull_none>,
+ /* acodec_adcdata */
+ <1 RK_PA0 5 &pcfg_pull_none>,
+ /* acodec_dac_datal */
+ <1 RK_PA7 5 &pcfg_pull_none>,
+ /* acodec_dac_datar */
+ <1 RK_PB0 5 &pcfg_pull_none>,
+ /* acodec_dacclk */
+ <1 RK_PA3 5 &pcfg_pull_none>,
+ /* acodec_dacsync */
+ <1 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ audiopwm {
+ /omit-if-no-ref/
+ audiopwm_lout: audiopwm-lout {
+ rockchip,pins =
+ /* audiopwm_lout */
+ <1 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_loutn: audiopwm-loutn {
+ rockchip,pins =
+ /* audiopwm_loutn */
+ <1 RK_PA1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_loutp: audiopwm-loutp {
+ rockchip,pins =
+ /* audiopwm_loutp */
+ <1 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_rout: audiopwm-rout {
+ rockchip,pins =
+ /* audiopwm_rout */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_routn: audiopwm-routn {
+ rockchip,pins =
+ /* audiopwm_routn */
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_routp: audiopwm-routp {
+ rockchip,pins =
+ /* audiopwm_routp */
+ <1 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ bt656 {
+ /omit-if-no-ref/
+ bt656m0_pins: bt656m0-pins {
+ rockchip,pins =
+ /* bt656_clkm0 */
+ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* bt656_d0m0 */
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ /* bt656_d1m0 */
+ <2 RK_PD1 2 &pcfg_pull_none>,
+ /* bt656_d2m0 */
+ <2 RK_PD2 2 &pcfg_pull_none>,
+ /* bt656_d3m0 */
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ /* bt656_d4m0 */
+ <2 RK_PD4 2 &pcfg_pull_none>,
+ /* bt656_d5m0 */
+ <2 RK_PD5 2 &pcfg_pull_none>,
+ /* bt656_d6m0 */
+ <2 RK_PD6 2 &pcfg_pull_none>,
+ /* bt656_d7m0 */
+ <2 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ bt656m1_pins: bt656m1-pins {
+ rockchip,pins =
+ /* bt656_clkm1 */
+ <4 RK_PB4 5 &pcfg_pull_none>,
+ /* bt656_d0m1 */
+ <3 RK_PC6 5 &pcfg_pull_none>,
+ /* bt656_d1m1 */
+ <3 RK_PC7 5 &pcfg_pull_none>,
+ /* bt656_d2m1 */
+ <3 RK_PD0 5 &pcfg_pull_none>,
+ /* bt656_d3m1 */
+ <3 RK_PD1 5 &pcfg_pull_none>,
+ /* bt656_d4m1 */
+ <3 RK_PD2 5 &pcfg_pull_none>,
+ /* bt656_d5m1 */
+ <3 RK_PD3 5 &pcfg_pull_none>,
+ /* bt656_d6m1 */
+ <3 RK_PD4 5 &pcfg_pull_none>,
+ /* bt656_d7m1 */
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+ };
+
+ bt1120 {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* bt1120_clk */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* bt1120_d0 */
+ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* bt1120_d1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* bt1120_d2 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* bt1120_d3 */
+ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* bt1120_d4 */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* bt1120_d5 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* bt1120_d6 */
+ <3 RK_PB0 2 &pcfg_pull_none>,
+ /* bt1120_d7 */
+ <3 RK_PB1 2 &pcfg_pull_none>,
+ /* bt1120_d8 */
+ <3 RK_PB2 2 &pcfg_pull_none>,
+ /* bt1120_d9 */
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ /* bt1120_d10 */
+ <3 RK_PB4 2 &pcfg_pull_none>,
+ /* bt1120_d11 */
+ <3 RK_PB5 2 &pcfg_pull_none>,
+ /* bt1120_d12 */
+ <3 RK_PB6 2 &pcfg_pull_none>,
+ /* bt1120_d13 */
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ /* bt1120_d14 */
+ <3 RK_PC2 2 &pcfg_pull_none>,
+ /* bt1120_d15 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ cam {
+ /omit-if-no-ref/
+ cam_clkout0: cam-clkout0 {
+ rockchip,pins =
+ /* cam_clkout0 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clkout1: cam-clkout1 {
+ rockchip,pins =
+ /* cam_clkout1 */
+ <4 RK_PB0 1 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rxm0 */
+ <0 RK_PB4 2 &pcfg_pull_none>,
+ /* can0_txm0 */
+ <0 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rxm1 */
+ <2 RK_PA2 4 &pcfg_pull_none>,
+ /* can0_txm1 */
+ <2 RK_PA1 4 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rxm0 */
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ /* can1_txm0 */
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rxm1 */
+ <4 RK_PC2 3 &pcfg_pull_none>,
+ /* can1_txm1 */
+ <4 RK_PC3 3 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ /omit-if-no-ref/
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ /* can2_rxm0 */
+ <4 RK_PB4 3 &pcfg_pull_none>,
+ /* can2_txm0 */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ /* can2_rxm1 */
+ <2 RK_PB1 4 &pcfg_pull_none>,
+ /* can2_txm1 */
+ <2 RK_PB2 4 &pcfg_pull_none>;
+ };
+ };
+
+ cif {
+ /omit-if-no-ref/
+ cif_clk: cif-clk {
+ rockchip,pins =
+ /* cif_clkout */
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_clk: cif-dvp-clk {
+ rockchip,pins =
+ /* cif_clkin */
+ <4 RK_PC1 1 &pcfg_pull_none>,
+ /* cif_href */
+ <4 RK_PB6 1 &pcfg_pull_none>,
+ /* cif_vsync */
+ <4 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus16: cif-dvp-bus16 {
+ rockchip,pins =
+ /* cif_d8 */
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ /* cif_d9 */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* cif_d10 */
+ <4 RK_PA0 1 &pcfg_pull_none>,
+ /* cif_d11 */
+ <4 RK_PA1 1 &pcfg_pull_none>,
+ /* cif_d12 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* cif_d13 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* cif_d14 */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* cif_d15 */
+ <4 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus8: cif-dvp-bus8 {
+ rockchip,pins =
+ /* cif_d0 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* cif_d1 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* cif_d2 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* cif_d3 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* cif_d4 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* cif_d5 */
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ /* cif_d6 */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* cif_d7 */
+ <3 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_in: clk32k-in {
+ rockchip,pins =
+ /* clk32k_in */
+ <0 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out0: clk32k-out0 {
+ rockchip,pins =
+ /* clk32k_out0 */
+ <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out1: clk32k-out1 {
+ rockchip,pins =
+ /* clk32k_out1 */
+ <2 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_avs */
+ <0 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ ebc {
+ /omit-if-no-ref/
+ ebc_extern: ebc-extern {
+ rockchip,pins =
+ /* ebc_sdce1 */
+ <4 RK_PA7 2 &pcfg_pull_none>,
+ /* ebc_sdce2 */
+ <4 RK_PB0 2 &pcfg_pull_none>,
+ /* ebc_sdce3 */
+ <4 RK_PB1 2 &pcfg_pull_none>,
+ /* ebc_sdshr */
+ <4 RK_PB5 2 &pcfg_pull_none>,
+ /* ebc_vcom */
+ <4 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ebc_pins: ebc-pins {
+ rockchip,pins =
+ /* ebc_gdclk */
+ <4 RK_PC0 2 &pcfg_pull_none>,
+ /* ebc_gdoe */
+ <4 RK_PB3 2 &pcfg_pull_none>,
+ /* ebc_gdsp */
+ <4 RK_PB4 2 &pcfg_pull_none>,
+ /* ebc_sdce0 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* ebc_sdclk */
+ <4 RK_PC1 2 &pcfg_pull_none>,
+ /* ebc_sddo0 */
+ <3 RK_PC6 2 &pcfg_pull_none>,
+ /* ebc_sddo1 */
+ <3 RK_PC7 2 &pcfg_pull_none>,
+ /* ebc_sddo2 */
+ <3 RK_PD0 2 &pcfg_pull_none>,
+ /* ebc_sddo3 */
+ <3 RK_PD1 2 &pcfg_pull_none>,
+ /* ebc_sddo4 */
+ <3 RK_PD2 2 &pcfg_pull_none>,
+ /* ebc_sddo5 */
+ <3 RK_PD3 2 &pcfg_pull_none>,
+ /* ebc_sddo6 */
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ /* ebc_sddo7 */
+ <3 RK_PD5 2 &pcfg_pull_none>,
+ /* ebc_sddo8 */
+ <3 RK_PD6 2 &pcfg_pull_none>,
+ /* ebc_sddo9 */
+ <3 RK_PD7 2 &pcfg_pull_none>,
+ /* ebc_sddo10 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* ebc_sddo11 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* ebc_sddo12 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* ebc_sddo13 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* ebc_sddo14 */
+ <4 RK_PA4 2 &pcfg_pull_none>,
+ /* ebc_sddo15 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* ebc_sdle */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* ebc_sdoe */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ edpdp {
+ /omit-if-no-ref/
+ edpdpm0_pins: edpdpm0-pins {
+ rockchip,pins =
+ /* edpdp_hpdinm0 */
+ <4 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ edpdpm1_pins: edpdpm1-pins {
+ rockchip,pins =
+ /* edpdp_hpdinm1 */
+ <0 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clkout */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_datastrobe: emmc-datastrobe {
+ rockchip,pins =
+ /* emmc_datastrobe */
+ <1 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0_pins: eth0-pins {
+ rockchip,pins =
+ /* eth0_refclko25m */
+ <2 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1m0_pins: eth1m0-pins {
+ rockchip,pins =
+ /* eth1_refclko25mm0 */
+ <3 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_pins: eth1m1-pins {
+ rockchip,pins =
+ /* eth1_refclko25mm1 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ /omit-if-no-ref/
+ flash_pins: flash-pins {
+ rockchip,pins =
+ /* flash_ale */
+ <1 RK_PD0 2 &pcfg_pull_none>,
+ /* flash_cle */
+ <1 RK_PC6 3 &pcfg_pull_none>,
+ /* flash_cs0n */
+ <1 RK_PD3 2 &pcfg_pull_none>,
+ /* flash_cs1n */
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ /* flash_d0 */
+ <1 RK_PB4 2 &pcfg_pull_none>,
+ /* flash_d1 */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* flash_d2 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* flash_d3 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* flash_d4 */
+ <1 RK_PC0 2 &pcfg_pull_none>,
+ /* flash_d5 */
+ <1 RK_PC1 2 &pcfg_pull_none>,
+ /* flash_d6 */
+ <1 RK_PC2 2 &pcfg_pull_none>,
+ /* flash_d7 */
+ <1 RK_PC3 2 &pcfg_pull_none>,
+ /* flash_dqs */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* flash_rdn */
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ /* flash_rdy */
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ /* flash_volsel */
+ <0 RK_PA7 1 &pcfg_pull_none>,
+ /* flash_wpn */
+ <1 RK_PC7 3 &pcfg_pull_none>,
+ /* flash_wrn */
+ <1 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD0 1 &pcfg_pull_none>,
+ /* fspi_cs0n */
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PC7 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_cs1: fspi-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n */
+ <1 RK_PC6 2 &pcfg_pull_up>;
+ };
+ };
+
+ gmac0 {
+ /omit-if-no-ref/
+ gmac0_miim: gmac0-miim {
+ rockchip,pins =
+ /* gmac0_mdc */
+ <2 RK_PC3 2 &pcfg_pull_none>,
+ /* gmac0_mdio */
+ <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_clkinout: gmac0-clkinout {
+ rockchip,pins =
+ /* gmac0_mclkinout */
+ <2 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_er: gmac0-rx-er {
+ rockchip,pins =
+ /* gmac0_rxer */
+ <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_bus2: gmac0-rx-bus2 {
+ rockchip,pins =
+ /* gmac0_rxd0 */
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ /* gmac0_rxd1 */
+ <2 RK_PB7 2 &pcfg_pull_none>,
+ /* gmac0_rxdvcrs */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_tx_bus2: gmac0-tx-bus2 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txd1 */
+ <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txen */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_clk: gmac0-rgmii-clk {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PA5 2 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus: gmac0-rgmii-bus {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txd3 */
+ <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gmac1 {
+ /omit-if-no-ref/
+ gmac1m0_miim: gmac1m0-miim {
+ rockchip,pins =
+ /* gmac1_mdcm0 */
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ /* gmac1_mdiom0 */
+ <3 RK_PC5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_clkinout: gmac1m0-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinoutm0 */
+ <3 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rx_er: gmac1m0-rx-er {
+ rockchip,pins =
+ /* gmac1_rxerm0 */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0m0 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* gmac1_rxd1m0 */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* gmac1_rxdvcrsm0 */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0m0 */
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd1m0 */
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txenm0 */
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclkm0 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_txclkm0 */
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2m0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m0 */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* gmac1_txd2m0 */
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd3m0 */
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_miim: gmac1m1-miim {
+ rockchip,pins =
+ /* gmac1_mdcm1 */
+ <4 RK_PB6 3 &pcfg_pull_none>,
+ /* gmac1_mdiom1 */
+ <4 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_clkinout: gmac1m1-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinoutm1 */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rx_er: gmac1m1-rx-er {
+ rockchip,pins =
+ /* gmac1_rxerm1 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0m1 */
+ <4 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_rxd1m1 */
+ <4 RK_PB0 3 &pcfg_pull_none>,
+ /* gmac1_rxdvcrsm1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0m1 */
+ <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd1m1 */
+ <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txenm1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclkm1 */
+ <4 RK_PA3 3 &pcfg_pull_none>,
+ /* gmac1_txclkm1 */
+ <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2m1 */
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m1 */
+ <4 RK_PA2 3 &pcfg_pull_none>,
+ /* gmac1_txd2m1 */
+ <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd3m1 */
+ <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC0 2 &pcfg_pull_none>,
+ /* gpu_pwren */
+ <0 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ hdmitx {
+ /omit-if-no-ref/
+ hdmitxm0_cec: hdmitxm0-cec {
+ rockchip,pins =
+ /* hdmitxm0_cec */
+ <4 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitxm1_cec: hdmitxm1-cec {
+ rockchip,pins =
+ /* hdmitxm1_cec */
+ <0 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitx_scl: hdmitx-scl {
+ rockchip,pins =
+ /* hdmitx_scl */
+ <4 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitx_sda: hdmitx-sda {
+ rockchip,pins =
+ /* hdmitx_sda */
+ <4 RK_PD0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB1 1 &pcfg_pull_none_smt>,
+ /* i2c0_sda */
+ <0 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c1_sda */
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_sclm0 */
+ <0 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sdam0 */
+ <0 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_sclm1 */
+ <4 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sdam1 */
+ <4 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_sclm0 */
+ <1 RK_PA1 1 &pcfg_pull_none_smt>,
+ /* i2c3_sdam0 */
+ <1 RK_PA0 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_sclm1 */
+ <3 RK_PB5 4 &pcfg_pull_none_smt>,
+ /* i2c3_sdam1 */
+ <3 RK_PB6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_sclm0 */
+ <4 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c4_sdam0 */
+ <4 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_sclm1 */
+ <2 RK_PB2 2 &pcfg_pull_none_smt>,
+ /* i2c4_sdam1 */
+ <2 RK_PB1 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_sclm0 */
+ <3 RK_PB3 4 &pcfg_pull_none_smt>,
+ /* i2c5_sdam0 */
+ <3 RK_PB4 4 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_sclm1 */
+ <4 RK_PC7 2 &pcfg_pull_none_smt>,
+ /* i2c5_sdam1 */
+ <4 RK_PD0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1m0_lrckrx: i2s1m0-lrckrx {
+ rockchip,pins =
+ /* i2s1m0_lrckrx */
+ <1 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_lrcktx: i2s1m0-lrcktx {
+ rockchip,pins =
+ /* i2s1m0_lrcktx */
+ <1 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1m0_mclk */
+ <1 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclkrx: i2s1m0-sclkrx {
+ rockchip,pins =
+ /* i2s1m0_sclkrx */
+ <1 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclktx: i2s1m0-sclktx {
+ rockchip,pins =
+ /* i2s1m0_sclktx */
+ <1 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1m0_sdi0 */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1m0_sdi1 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1m0_sdi2 */
+ <1 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1m0_sdi3 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1m0_sdo0 */
+ <1 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1m0_sdo1 */
+ <1 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1m0_sdo2 */
+ <1 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1m0_sdo3 */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_lrckrx: i2s1m1-lrckrx {
+ rockchip,pins =
+ /* i2s1m1_lrckrx */
+ <4 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_lrcktx: i2s1m1-lrcktx {
+ rockchip,pins =
+ /* i2s1m1_lrcktx */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1m1_mclk */
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclkrx: i2s1m1-sclkrx {
+ rockchip,pins =
+ /* i2s1m1_sclkrx */
+ <4 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclktx: i2s1m1-sclktx {
+ rockchip,pins =
+ /* i2s1m1_sclktx */
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1m1_sdi0 */
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1m1_sdi1 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1m1_sdi2 */
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1m1_sdi3 */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1m1_sdo0 */
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1m1_sdo1 */
+ <4 RK_PB0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1m1_sdo2 */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1m1_sdo3 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_lrckrx: i2s1m2-lrckrx {
+ rockchip,pins =
+ /* i2s1m2_lrckrx */
+ <3 RK_PC5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_lrcktx: i2s1m2-lrcktx {
+ rockchip,pins =
+ /* i2s1m2_lrcktx */
+ <2 RK_PD2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_mclk: i2s1m2-mclk {
+ rockchip,pins =
+ /* i2s1m2_mclk */
+ <2 RK_PD0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sclkrx: i2s1m2-sclkrx {
+ rockchip,pins =
+ /* i2s1m2_sclkrx */
+ <3 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sclktx: i2s1m2-sclktx {
+ rockchip,pins =
+ /* i2s1m2_sclktx */
+ <2 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi0: i2s1m2-sdi0 {
+ rockchip,pins =
+ /* i2s1m2_sdi0 */
+ <2 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi1: i2s1m2-sdi1 {
+ rockchip,pins =
+ /* i2s1m2_sdi1 */
+ <2 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi2: i2s1m2-sdi2 {
+ rockchip,pins =
+ /* i2s1m2_sdi2 */
+ <2 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi3: i2s1m2-sdi3 {
+ rockchip,pins =
+ /* i2s1m2_sdi3 */
+ <2 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo0: i2s1m2-sdo0 {
+ rockchip,pins =
+ /* i2s1m2_sdo0 */
+ <2 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo1: i2s1m2-sdo1 {
+ rockchip,pins =
+ /* i2s1m2_sdo1 */
+ <3 RK_PA0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo2: i2s1m2-sdo2 {
+ rockchip,pins =
+ /* i2s1m2_sdo2 */
+ <3 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo3: i2s1m2-sdo3 {
+ rockchip,pins =
+ /* i2s1m2_sdo3 */
+ <3 RK_PC2 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m0_lrckrx: i2s2m0-lrckrx {
+ rockchip,pins =
+ /* i2s2m0_lrckrx */
+ <2 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_lrcktx: i2s2m0-lrcktx {
+ rockchip,pins =
+ /* i2s2m0_lrcktx */
+ <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2m0_mclk */
+ <2 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclkrx: i2s2m0-sclkrx {
+ rockchip,pins =
+ /* i2s2m0_sclkrx */
+ <2 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclktx: i2s2m0-sclktx {
+ rockchip,pins =
+ /* i2s2m0_sclktx */
+ <2 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2m0_sdi */
+ <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2m0_sdo */
+ <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_lrckrx: i2s2m1-lrckrx {
+ rockchip,pins =
+ /* i2s2m1_lrckrx */
+ <4 RK_PA5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_lrcktx: i2s2m1-lrcktx {
+ rockchip,pins =
+ /* i2s2m1_lrcktx */
+ <4 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2m1_mclk */
+ <4 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclkrx: i2s2m1-sclkrx {
+ rockchip,pins =
+ /* i2s2m1_sclkrx */
+ <4 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclktx: i2s2m1-sclktx {
+ rockchip,pins =
+ /* i2s2m1_sclktx */
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2m1_sdi */
+ <4 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2m1_sdo */
+ <4 RK_PB3 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s3 {
+ /omit-if-no-ref/
+ i2s3m0_lrck: i2s3m0-lrck {
+ rockchip,pins =
+ /* i2s3m0_lrck */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_mclk: i2s3m0-mclk {
+ rockchip,pins =
+ /* i2s3m0_mclk */
+ <3 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sclk: i2s3m0-sclk {
+ rockchip,pins =
+ /* i2s3m0_sclk */
+ <3 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sdi: i2s3m0-sdi {
+ rockchip,pins =
+ /* i2s3m0_sdi */
+ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sdo: i2s3m0-sdo {
+ rockchip,pins =
+ /* i2s3m0_sdo */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_lrck: i2s3m1-lrck {
+ rockchip,pins =
+ /* i2s3m1_lrck */
+ <4 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_mclk: i2s3m1-mclk {
+ rockchip,pins =
+ /* i2s3m1_mclk */
+ <4 RK_PC2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sclk: i2s3m1-sclk {
+ rockchip,pins =
+ /* i2s3m1_sclk */
+ <4 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sdi: i2s3m1-sdi {
+ rockchip,pins =
+ /* i2s3m1_sdi */
+ <4 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sdo: i2s3m1-sdo {
+ rockchip,pins =
+ /* i2s3m1_sdo */
+ <4 RK_PC5 5 &pcfg_pull_none>;
+ };
+ };
+
+ isp {
+ /omit-if-no-ref/
+ isp_pins: isp-pins {
+ rockchip,pins =
+ /* isp_flashtrigin */
+ <4 RK_PB4 4 &pcfg_pull_none>,
+ /* isp_flashtrigout */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* isp_prelighttrig */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtag_pins: jtag-pins {
+ rockchip,pins =
+ /* jtag_tck */
+ <1 RK_PD7 2 &pcfg_pull_none>,
+ /* jtag_tms */
+ <2 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+
+ lcdc {
+ /omit-if-no-ref/
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins =
+ /* lcdc_clk */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* lcdc_d0 */
+ <2 RK_PD0 1 &pcfg_pull_none>,
+ /* lcdc_d1 */
+ <2 RK_PD1 1 &pcfg_pull_none>,
+ /* lcdc_d2 */
+ <2 RK_PD2 1 &pcfg_pull_none>,
+ /* lcdc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_none>,
+ /* lcdc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_none>,
+ /* lcdc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_none>,
+ /* lcdc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_none>,
+ /* lcdc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_none>,
+ /* lcdc_d8 */
+ <3 RK_PA1 1 &pcfg_pull_none>,
+ /* lcdc_d9 */
+ <3 RK_PA2 1 &pcfg_pull_none>,
+ /* lcdc_d10 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* lcdc_d11 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* lcdc_d12 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* lcdc_d13 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* lcdc_d14 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* lcdc_d15 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* lcdc_d16 */
+ <3 RK_PB1 1 &pcfg_pull_none>,
+ /* lcdc_d17 */
+ <3 RK_PB2 1 &pcfg_pull_none>,
+ /* lcdc_d18 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* lcdc_d19 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* lcdc_d20 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* lcdc_d21 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* lcdc_d22 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* lcdc_d23 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* lcdc_den */
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ /* lcdc_hsync */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* lcdc_vsync */
+ <3 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ mcu {
+ /omit-if-no-ref/
+ mcu_pins: mcu-pins {
+ rockchip,pins =
+ /* mcu_jtagtck */
+ <0 RK_PB4 4 &pcfg_pull_none>,
+ /* mcu_jtagtdi */
+ <0 RK_PC1 4 &pcfg_pull_none>,
+ /* mcu_jtagtdo */
+ <0 RK_PB3 4 &pcfg_pull_none>,
+ /* mcu_jtagtms */
+ <0 RK_PC2 4 &pcfg_pull_none>,
+ /* mcu_jtagtrstn */
+ <0 RK_PC3 4 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20 {
+ /omit-if-no-ref/
+ pcie20m0_pins: pcie20m0-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm0 */
+ <0 RK_PA5 3 &pcfg_pull_none>,
+ /* pcie20_perstnm0 */
+ <0 RK_PB6 3 &pcfg_pull_none>,
+ /* pcie20_wakenm0 */
+ <0 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20m1_pins: pcie20m1-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm1 */
+ <2 RK_PD0 4 &pcfg_pull_none>,
+ /* pcie20_perstnm1 */
+ <3 RK_PC1 4 &pcfg_pull_none>,
+ /* pcie20_wakenm1 */
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20m2_pins: pcie20m2-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm2 */
+ <1 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie20_perstnm2 */
+ <1 RK_PB2 4 &pcfg_pull_none>,
+ /* pcie20_wakenm2 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20_buttonrstn: pcie20-buttonrstn {
+ rockchip,pins =
+ /* pcie20_buttonrstn */
+ <0 RK_PB4 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x1 {
+ /omit-if-no-ref/
+ pcie30x1m0_pins: pcie30x1m0-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm0 */
+ <0 RK_PA4 3 &pcfg_pull_none>,
+ /* pcie30x1_perstnm0 */
+ <0 RK_PC3 3 &pcfg_pull_none>,
+ /* pcie30x1_wakenm0 */
+ <0 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_pins: pcie30x1m1-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm1 */
+ <2 RK_PD2 4 &pcfg_pull_none>,
+ /* pcie30x1_perstnm1 */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* pcie30x1_wakenm1 */
+ <2 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_pins: pcie30x1m2-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm2 */
+ <1 RK_PA5 4 &pcfg_pull_none>,
+ /* pcie30x1_perstnm2 */
+ <1 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie30x1_wakenm2 */
+ <1 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_buttonrstn: pcie30x1-buttonrstn {
+ rockchip,pins =
+ /* pcie30x1_buttonrstn */
+ <0 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x2 {
+ /omit-if-no-ref/
+ pcie30x2m0_pins: pcie30x2m0-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm0 */
+ <0 RK_PA6 2 &pcfg_pull_none>,
+ /* pcie30x2_perstnm0 */
+ <0 RK_PC6 3 &pcfg_pull_none>,
+ /* pcie30x2_wakenm0 */
+ <0 RK_PC5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm1 */
+ <2 RK_PD4 4 &pcfg_pull_none>,
+ /* pcie30x2_perstnm1 */
+ <2 RK_PD6 4 &pcfg_pull_none>,
+ /* pcie30x2_wakenm1 */
+ <2 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_pins: pcie30x2m2-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm2 */
+ <4 RK_PC2 4 &pcfg_pull_none>,
+ /* pcie30x2_perstnm2 */
+ <4 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30x2_wakenm2 */
+ <4 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2_buttonrstn: pcie30x2-buttonrstn {
+ rockchip,pins =
+ /* pcie30x2_buttonrstn */
+ <0 RK_PB0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins =
+ /* pdm_clk0m0 */
+ <1 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_clk1: pdmm0-clk1 {
+ rockchip,pins =
+ /* pdmm0_clk1 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins =
+ /* pdmm0_sdi0 */
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins =
+ /* pdmm0_sdi1 */
+ <1 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins =
+ /* pdmm0_sdi2 */
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins =
+ /* pdmm0_sdi3 */
+ <1 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk: pdmm1-clk {
+ rockchip,pins =
+ /* pdm_clk0m1 */
+ <3 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk1: pdmm1-clk1 {
+ rockchip,pins =
+ /* pdmm1_clk1 */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi0: pdmm1-sdi0 {
+ rockchip,pins =
+ /* pdmm1_sdi0 */
+ <3 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi1: pdmm1-sdi1 {
+ rockchip,pins =
+ /* pdmm1_sdi1 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi2: pdmm1-sdi2 {
+ rockchip,pins =
+ /* pdmm1_sdi2 */
+ <4 RK_PA2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi3: pdmm1-sdi3 {
+ rockchip,pins =
+ /* pdmm1_sdi3 */
+ <4 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk1: pdmm2-clk1 {
+ rockchip,pins =
+ /* pdmm2_clk1 */
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi0: pdmm2-sdi0 {
+ rockchip,pins =
+ /* pdmm2_sdi0 */
+ <3 RK_PB3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi1: pdmm2-sdi1 {
+ rockchip,pins =
+ /* pdmm2_sdi1 */
+ <3 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi2: pdmm2-sdi2 {
+ rockchip,pins =
+ /* pdmm2_sdi2 */
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi3: pdmm2-sdi3 {
+ rockchip,pins =
+ /* pdmm2_sdi3 */
+ <3 RK_PC0 5 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ /* pmic_sleep */
+ <0 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug0 */
+ <0 RK_PA5 4 &pcfg_pull_none>,
+ /* pmu_debug1 */
+ <0 RK_PA6 3 &pcfg_pull_none>,
+ /* pmu_debug2 */
+ <0 RK_PC4 4 &pcfg_pull_none>,
+ /* pmu_debug3 */
+ <0 RK_PC5 4 &pcfg_pull_none>,
+ /* pmu_debug4 */
+ <0 RK_PC6 4 &pcfg_pull_none>,
+ /* pmu_debug5 */
+ <0 RK_PC7 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <0 RK_PC7 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <0 RK_PB5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <0 RK_PB6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3_pins: pwm3-pins {
+ rockchip,pins =
+ /* pwm3_ir */
+ <0 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4_pins: pwm4-pins {
+ rockchip,pins =
+ /* pwm4 */
+ <0 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5_pins: pwm5-pins {
+ rockchip,pins =
+ /* pwm5 */
+ <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6_pins: pwm6-pins {
+ rockchip,pins =
+ /* pwm6 */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7_pins: pwm7-pins {
+ rockchip,pins =
+ /* pwm7_ir */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm8 {
+ /omit-if-no-ref/
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <1 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm9 {
+ /omit-if-no-ref/
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <1 RK_PD6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm10 {
+ /omit-if-no-ref/
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <3 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <2 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm11 {
+ /omit-if-no-ref/
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_irm0 */
+ <3 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_irm1 */
+ <4 RK_PC0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm12 {
+ /omit-if-no-ref/
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <3 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm13 {
+ /omit-if-no-ref/
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <4 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm14 {
+ /omit-if-no-ref/
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm15 {
+ /omit-if-no-ref/
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_irm0 */
+ <3 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_irm1 */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ refclk {
+ /omit-if-no-ref/
+ refclk_pins: refclk-pins {
+ rockchip,pins =
+ /* refclk_ou */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ sata {
+ /omit-if-no-ref/
+ sata_pins: sata-pins {
+ rockchip,pins =
+ /* sata_cpdet */
+ <0 RK_PA4 2 &pcfg_pull_none>,
+ /* sata_cppod */
+ <0 RK_PA6 1 &pcfg_pull_none>,
+ /* sata_mpswitch */
+ <0 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ sata0 {
+ /omit-if-no-ref/
+ sata0_pins: sata0-pins {
+ rockchip,pins =
+ /* sata0_actled */
+ <4 RK_PC6 3 &pcfg_pull_none>;
+ };
+ };
+
+ sata1 {
+ /omit-if-no-ref/
+ sata1_pins: sata1-pins {
+ rockchip,pins =
+ /* sata1_actled */
+ <4 RK_PC5 3 &pcfg_pull_none>;
+ };
+ };
+
+ sata2 {
+ /omit-if-no-ref/
+ sata2_pins: sata2-pins {
+ rockchip,pins =
+ /* sata2_actled */
+ <4 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ scr {
+ /omit-if-no-ref/
+ scr_pins: scr-pins {
+ rockchip,pins =
+ /* scr_clk */
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ /* scr_det */
+ <1 RK_PA7 3 &pcfg_pull_up>,
+ /* scr_io */
+ <1 RK_PA3 3 &pcfg_pull_up>,
+ /* scr_rst */
+ <1 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_det */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_pwren: sdmmc0-pwren {
+ rockchip,pins =
+ /* sdmmc0_pwren */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ /* sdmmc1_det */
+ <2 RK_PB2 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins =
+ /* sdmmc1_pwren */
+ <2 RK_PB1 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc2 {
+ /omit-if-no-ref/
+ sdmmc2m0_bus4: sdmmc2m0-bus4 {
+ rockchip,pins =
+ /* sdmmc2_d0m0 */
+ <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d1m0 */
+ <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d2m0 */
+ <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d3m0 */
+ <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_clk: sdmmc2m0-clk {
+ rockchip,pins =
+ /* sdmmc2_clkm0 */
+ <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_cmd: sdmmc2m0-cmd {
+ rockchip,pins =
+ /* sdmmc2_cmdm0 */
+ <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_det: sdmmc2m0-det {
+ rockchip,pins =
+ /* sdmmc2_detm0 */
+ <3 RK_PD4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_pwren: sdmmc2m0-pwren {
+ rockchip,pins =
+ /* sdmmc2m0_pwren */
+ <3 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_bus4: sdmmc2m1-bus4 {
+ rockchip,pins =
+ /* sdmmc2_d0m1 */
+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d1m1 */
+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d2m1 */
+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d3m1 */
+ <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_clk: sdmmc2m1-clk {
+ rockchip,pins =
+ /* sdmmc2_clkm1 */
+ <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_cmd: sdmmc2m1-cmd {
+ rockchip,pins =
+ /* sdmmc2_cmdm1 */
+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_det: sdmmc2m1-det {
+ rockchip,pins =
+ /* sdmmc2_detm1 */
+ <3 RK_PA7 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_pwren: sdmmc2m1-pwren {
+ rockchip,pins =
+ /* sdmmc2m1_pwren */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_tx: spdifm0-tx {
+ rockchip,pins =
+ /* spdifm0_tx */
+ <1 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx: spdifm1-tx {
+ rockchip,pins =
+ /* spdifm1_tx */
+ <3 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx: spdifm2-tx {
+ rockchip,pins =
+ /* spdifm2_tx */
+ <4 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clkm0 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* spi0_misom0 */
+ <0 RK_PC5 2 &pcfg_pull_none>,
+ /* spi0_mosim0 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m0 */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1m0 */
+ <0 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clkm1 */
+ <2 RK_PD3 3 &pcfg_pull_none>,
+ /* spi0_misom1 */
+ <2 RK_PD0 3 &pcfg_pull_none>,
+ /* spi0_mosim1 */
+ <2 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m1 */
+ <2 RK_PD2 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clkm0 */
+ <2 RK_PB5 3 &pcfg_pull_none>,
+ /* spi1_misom0 */
+ <2 RK_PB6 3 &pcfg_pull_none>,
+ /* spi1_mosim0 */
+ <2 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m0 */
+ <2 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1m0 */
+ <2 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clkm1 */
+ <3 RK_PC3 3 &pcfg_pull_none>,
+ /* spi1_misom1 */
+ <3 RK_PC2 3 &pcfg_pull_none>,
+ /* spi1_mosim1 */
+ <3 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m1 */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clkm0 */
+ <2 RK_PC1 4 &pcfg_pull_none>,
+ /* spi2_misom0 */
+ <2 RK_PC2 4 &pcfg_pull_none>,
+ /* spi2_mosim0 */
+ <2 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m0 */
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m0 */
+ <2 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clkm1 */
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ /* spi2_misom1 */
+ <2 RK_PD7 3 &pcfg_pull_none>,
+ /* spi2_mosim1 */
+ <2 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m1 */
+ <2 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m1 */
+ <2 RK_PD4 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clkm0 */
+ <4 RK_PB3 4 &pcfg_pull_none>,
+ /* spi3_misom0 */
+ <4 RK_PB0 4 &pcfg_pull_none>,
+ /* spi3_mosim0 */
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m0 */
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m0 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clkm1 */
+ <4 RK_PC2 2 &pcfg_pull_none>,
+ /* spi3_misom1 */
+ <4 RK_PC5 2 &pcfg_pull_none>,
+ /* spi3_mosim1 */
+ <4 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m1 */
+ <4 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m1 */
+ <4 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm0_shut: tsadcm0-shut {
+ rockchip,pins =
+ /* tsadcm0_shut */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadcm1_shut: tsadcm1-shut {
+ rockchip,pins =
+ /* tsadcm1_shut */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shutorg: tsadc-shutorg {
+ rockchip,pins =
+ /* tsadc_shutorg */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <0 RK_PC0 3 &pcfg_pull_up>,
+ /* uart0_tx */
+ <0 RK_PC1 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ /* uart0_ctsn */
+ <0 RK_PC7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ /* uart0_rtsn */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rxm0 */
+ <2 RK_PB3 2 &pcfg_pull_up>,
+ /* uart1_txm0 */
+ <2 RK_PB4 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <2 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rxm1 */
+ <3 RK_PD7 4 &pcfg_pull_up>,
+ /* uart1_txm1 */
+ <3 RK_PD6 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <4 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <4 RK_PB6 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rxm0 */
+ <0 RK_PD0 1 &pcfg_pull_up>,
+ /* uart2_txm0 */
+ <0 RK_PD1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rxm1 */
+ <1 RK_PD6 2 &pcfg_pull_up>,
+ /* uart2_txm1 */
+ <1 RK_PD5 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rxm0 */
+ <1 RK_PA0 2 &pcfg_pull_up>,
+ /* uart3_txm0 */
+ <1 RK_PA1 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_ctsn: uart3m0-ctsn {
+ rockchip,pins =
+ /* uart3m0_ctsn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_rtsn: uart3m0-rtsn {
+ rockchip,pins =
+ /* uart3m0_rtsn */
+ <1 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rxm1 */
+ <3 RK_PC0 4 &pcfg_pull_up>,
+ /* uart3_txm1 */
+ <3 RK_PB7 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rxm0 */
+ <1 RK_PA4 2 &pcfg_pull_up>,
+ /* uart4_txm0 */
+ <1 RK_PA6 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_ctsn: uart4m0-ctsn {
+ rockchip,pins =
+ /* uart4m0_ctsn */
+ <1 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_rtsn: uart4m0-rtsn {
+ rockchip,pins =
+ /* uart4m0_rtsn */
+ <1 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rxm1 */
+ <3 RK_PB1 4 &pcfg_pull_up>,
+ /* uart4_txm1 */
+ <3 RK_PB2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rxm0 */
+ <2 RK_PA1 3 &pcfg_pull_up>,
+ /* uart5_txm0 */
+ <2 RK_PA2 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PD7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rxm1 */
+ <3 RK_PC3 4 &pcfg_pull_up>,
+ /* uart5_txm1 */
+ <3 RK_PC2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rxm0 */
+ <2 RK_PA3 3 &pcfg_pull_up>,
+ /* uart6_txm0 */
+ <2 RK_PA4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <2 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <2 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rxm1 */
+ <1 RK_PD6 3 &pcfg_pull_up>,
+ /* uart6_txm1 */
+ <1 RK_PD5 3 &pcfg_pull_up>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rxm0 */
+ <2 RK_PA5 3 &pcfg_pull_up>,
+ /* uart7_txm0 */
+ <2 RK_PA6 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <2 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <2 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rxm1 */
+ <3 RK_PC5 4 &pcfg_pull_up>,
+ /* uart7_txm1 */
+ <3 RK_PC4 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer: uart7m2-xfer {
+ rockchip,pins =
+ /* uart7_rxm2 */
+ <4 RK_PA3 4 &pcfg_pull_up>,
+ /* uart7_txm2 */
+ <4 RK_PA2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rxm0 */
+ <2 RK_PC6 2 &pcfg_pull_up>,
+ /* uart8_txm0 */
+ <2 RK_PC5 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <2 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rxm1 */
+ <3 RK_PA0 4 &pcfg_pull_up>,
+ /* uart8_txm1 */
+ <2 RK_PD7 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rxm0 */
+ <2 RK_PA7 3 &pcfg_pull_up>,
+ /* uart9_txm0 */
+ <2 RK_PB0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <2 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <2 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rxm1 */
+ <4 RK_PC6 4 &pcfg_pull_up>,
+ /* uart9_txm1 */
+ <4 RK_PC5 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer: uart9m2-xfer {
+ rockchip,pins =
+ /* uart9_rxm2 */
+ <4 RK_PA5 4 &pcfg_pull_up>,
+ /* uart9_txm2 */
+ <4 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+
+ vop {
+ /omit-if-no-ref/
+ vopm0_pins: vopm0-pins {
+ rockchip,pins =
+ /* vop_pwmm0 */
+ <0 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ vopm1_pins: vopm1-pins {
+ rockchip,pins =
+ /* vop_pwmm1 */
+ <3 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ spi0-hs {
+ /omit-if-no-ref/
+ spi0m0_pins_hs: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clkm0 */
+ <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi0_misom0 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosim0 */
+ <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0_hs: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m0 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1_hs: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1m0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins_hs: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clkm1 */
+ <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>,
+ /* spi0_misom1 */
+ <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosim1 */
+ <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0_hs: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m1 */
+ <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi1-hs {
+ /omit-if-no-ref/
+ spi1m0_pins_hs: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clkm0 */
+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_misom0 */
+ <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosim0 */
+ <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0_hs: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m0 */
+ <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1_hs: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1m0 */
+ <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins_hs: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clkm1 */
+ <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_misom1 */
+ <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosim1 */
+ <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0_hs: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m1 */
+ <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi2-hs {
+ /omit-if-no-ref/
+ spi2m0_pins_hs: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clkm0 */
+ <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>,
+ /* spi2_misom0 */
+ <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosim0 */
+ <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0_hs: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m0 */
+ <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1_hs: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m0 */
+ <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins_hs: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clkm1 */
+ <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>,
+ /* spi2_misom1 */
+ <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosim1 */
+ <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0_hs: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m1 */
+ <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1_hs: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m1 */
+ <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3-hs {
+ /omit-if-no-ref/
+ spi3m0_pins_hs: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clkm0 */
+ <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>,
+ /* spi3_misom0 */
+ <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosim0 */
+ <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0_hs: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m0 */
+ <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1_hs: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m0 */
+ <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins_hs: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clkm1 */
+ <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>,
+ /* spi3_misom1 */
+ <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosim1 */
+ <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0_hs: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m1 */
+ <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1_hs: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m1 */
+ <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ gmac-txd-level3 {
+ /omit-if-no-ref/
+ gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txd1 */
+ <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txen */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txd3 */
+ <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac1_txd0m0 */
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd1m0 */
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txenm0 */
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac1_rxd2m0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m0 */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* gmac1_txd2m0 */
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd3m0 */
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac1_txd0m1 */
+ <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd1m1 */
+ <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txenm1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac1_rxd2m1 */
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m1 */
+ <4 RK_PA2 3 &pcfg_pull_none>,
+ /* gmac1_txd2m1 */
+ <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd3m1 */
+ <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+
+ gmac-txc-level2 {
+ /omit-if-no-ref/
+ gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PA5 2 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac1_rxclkm0 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_txclkm0 */
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac1_rxclkm1 */
+ <4 RK_PA3 3 &pcfg_pull_none>,
+ /* gmac1_txclkm1 */
+ <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
new file mode 100644
index 0000000..d225e6a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3568";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ clocks = <&scmi_clk 0>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ opp-suspend;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <975000 975000 1150000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1050000 1050000 1150000>;
+ };
+
+ opp-1992000000 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1150000 1150000 1150000>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,no-tick-in-suspend;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ pinctrl-0 = <&clk32k_out0>;
+ pinctrl-names = "default";
+ #clock-cells = <0>;
+ };
+
+ sram@10f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x0010f000 0x100>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ gic: interrupt-controller@fd400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+ <0x0 0xfd460000 0 0x80000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ mbi-alias = <0x0 0xfd100000>;
+ mbi-ranges = <296 24>;
+ msi-controller;
+ };
+
+ pmugrf: syscon@fdc20000 {
+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc20000 0x0 0x10000>;
+ };
+
+ grf: syscon@fdc60000 {
+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc60000 0x0 0x10000>;
+ };
+
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c0: i2c@fdd40000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfdd40000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@fdd50000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfdd50000 0x0 0x100>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 0>, <&dmac0 1>;
+ pinctrl-0 = <&uart0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sdmmc2: mmc@fe000000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC2>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@fe2b0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@fe2c0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC1>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdhci: mmc@fe310000 {
+ compatible = "rockchip,rk3568-dwcmshc";
+ reg = <0x0 0xfe310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
+ dmac0: dmac@fe530000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe530000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ dmac1: dmac@fe550000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe550000 0x0 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@fe5a0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe5b0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe5c0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe5d0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fe5e0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart1: serial@fe650000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe650000 0x0 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ pinctrl-0 = <&uart1m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@fe660000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe660000 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 4>, <&dmac0 5>;
+ pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@fe670000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe670000 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ pinctrl-0 = <&uart3m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@fe680000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe680000 0x0 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ pinctrl-0 = <&uart4m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@fe690000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe690000 0x0 0x100>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ pinctrl-0 = <&uart5m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@fe6a0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@fe6b0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ pinctrl-0 = <&uart7m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart8: serial@fe6c0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ pinctrl-0 = <&uart8m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart9: serial@fe6d0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 18>, <&dmac0 19>;
+ pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3568-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@fdd60000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfdd60000 0x0 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@fe740000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe740000 0x0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@fe750000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe750000 0x0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@fe760000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe760000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@fe770000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe770000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3568-pinctrl.dtsi"
diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
new file mode 100644
index 0000000..5c64543
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+ bias-disable;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+ bias-disable;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+ bias-disable;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+ bias-disable;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+ bias-disable;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+ bias-disable;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+ bias-disable;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+ bias-pull-up;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
+ bias-pull-up;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
+ bias-pull-up;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
+ bias-pull-up;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
+ bias-pull-up;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
+ bias-pull-up;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
+ bias-pull-up;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+ bias-pull-down;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
+ bias-pull-down;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
+ bias-pull-down;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
+ bias-pull-down;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
+ bias-pull-down;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
+ bias-pull-down;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
+ bias-pull-down;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
+ bias-pull-down;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
+ bias-pull-down;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
+ bias-pull-down;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
+ bias-pull-down;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index ca59d1f..02c3fdf9 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
@@ -13,8 +24,30 @@
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x200000>;
- atf-sram@0 {
- reg = <0x0 0x1a000>;
+ tfa-sram@1c0000 {
+ reg = <0x1c0000 0x20000>;
+ };
+
+ dmsc-sram@1e0000 {
+ reg = <0x1e0000 0x1c000>;
+ };
+
+ sproxy-sram@1fc000 {
+ reg = <0x1fc000 0x4000>;
+ };
+ };
+
+ main_conf: syscon@43000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x0 0x43000000 0x0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x43000000 0x20000>;
+
+ serdes_ln_ctrl: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
};
@@ -189,8 +222,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -202,8 +233,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -215,8 +244,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -228,8 +255,6 @@
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -241,8 +266,6 @@
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -254,8 +277,6 @@
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -267,8 +288,6 @@
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -489,7 +508,8 @@
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&main_conf 0x200>;
};
cpsw_port2: port@2 {
@@ -497,7 +517,7 @@
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
- mac-address = [00 01 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
};
};
@@ -673,4 +693,170 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
+
+ main_r5fss0: r5fss@78000000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78000000 0x00 0x78000000 0x10000>,
+ <0x78100000 0x00 0x78100000 0x10000>,
+ <0x78200000 0x00 0x78200000 0x08000>,
+ <0x78300000 0x00 0x78300000 0x08000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@78000000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78000000 0x00010000>,
+ <0x78100000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <121>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 121 1>;
+ firmware-name = "am64-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@78200000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78200000 0x00008000>,
+ <0x78300000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <122>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 122 1>;
+ firmware-name = "am64-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@78400000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78400000 0x00 0x78400000 0x10000>,
+ <0x78500000 0x00 0x78500000 0x10000>,
+ <0x78600000 0x00 0x78600000 0x08000>,
+ <0x78700000 0x00 0x78700000 0x08000>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@78400000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78400000 0x00010000>,
+ <0x78500000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <123>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 123 1>;
+ firmware-name = "am64-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@78600000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78600000 0x00008000>,
+ <0x78700000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <124>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 124 1>;
+ firmware-name = "am64-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ serdes_wiz0: wiz@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+
+ assigned-clocks = <&k3_clks 162 1>;
+ assigned-clock-parents = <&k3_clks 162 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 162 1>,
+ <&k3_clks 162 1>,
+ <&k3_clks 162 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+ };
+
+ pcie0_ep: pcie-ep@f102000 {
+ compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
index deb19ae5..59cc58f 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
@@ -9,8 +9,6 @@
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -22,8 +20,6 @@
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -87,7 +83,7 @@
};
mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "keystone-gpio";
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dad0efa..0307122 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@@ -36,6 +38,60 @@
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
evm_12v0: fixedregulator-evm12v0 {
@@ -334,7 +390,7 @@
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
@@ -466,3 +522,55 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 8424cd0..d3aa290 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
@@ -35,6 +37,60 @@
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
vusb_main: fixed-regulator-vusb-main5v0 {
@@ -85,6 +141,12 @@
>;
};
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@@ -235,6 +297,33 @@
disable-wp;
};
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
@@ -332,3 +421,35 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index de763ca..1008e91 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -555,6 +555,7 @@
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ no-1-8-v;
};
&usb0 {
@@ -575,7 +576,7 @@
#address-cells = <1>;
#size-cells= <0>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&tscadc0 {
@@ -653,3 +654,63 @@
&pcie1_ep {
status = "disabled";
};
+
+&mailbox0_cluster0 {
+ status = "disabled";
+};
+
+&mailbox0_cluster1 {
+ status = "disabled";
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 6cd3131..ba4e5d3 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -84,8 +84,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -95,8 +93,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
@@ -105,8 +101,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
@@ -301,7 +295,6 @@
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
- no-1-8-v;
};
scm_conf: scm-conf@100000 {
@@ -1053,6 +1046,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru0_1-fw";
};
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg1: icssg@b100000 {
@@ -1184,6 +1187,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru1_1-fw";
};
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 63 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg2: icssg@b200000 {
@@ -1315,5 +1328,15 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru2_1-fw";
};
+
+ icssg2_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 64 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index f5b8ef2..c93ff15 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -23,8 +23,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index 7cb864b..9d21cdf 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -50,8 +50,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
index 4f7e3f2..94bb5dd 100644
--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
@@ -59,3 +59,8 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index eddb2ff..cfbcebf 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -85,6 +85,38 @@
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc3v3_io: fixedregulator-vcc3v3io {
+ /* Output of TPS54334 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&evm_12v0>;
+ };
+
+ vdd_mmc1_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
+ };
};
&wkup_pmx0 {
@@ -136,7 +168,7 @@
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+ AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
>;
};
@@ -299,7 +331,7 @@
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
flash@0{
compatible = "jedec,spi-nor";
@@ -327,6 +359,7 @@
* disable sdhci1
*/
&sdhci1 {
+ vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
@@ -506,3 +539,15 @@
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index bedd01b..d14f3c1 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -90,7 +90,7 @@
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 19fea8a..e8a41d0 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -301,8 +301,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -314,8 +312,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -327,8 +323,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -340,8 +334,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -353,8 +345,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -366,8 +356,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -379,8 +367,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -392,8 +378,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -405,8 +389,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -418,8 +400,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -683,6 +663,7 @@
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
+ cdns,phyrst-a-enable;
};
};
@@ -696,7 +677,6 @@
<149>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
@@ -714,7 +694,6 @@
<158>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
@@ -732,7 +711,6 @@
<167>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
@@ -750,7 +728,6 @@
<176>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 5663fe3..1044ec6 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
@@ -117,7 +113,6 @@
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
@@ -134,7 +129,6 @@
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 60764366..8bd02d9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
/ {
chosen {
@@ -237,7 +238,7 @@
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
@@ -358,7 +359,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -635,8 +636,45 @@
status = "disabled";
};
+&cmn_refclk1 {
+ clock-frequency = <100000000>;
+};
+
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
&serdes0 {
- serdes0_pcie_link: link@0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -646,7 +684,10 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -656,7 +697,10 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz2_pll1_refclk>;
+
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -718,3 +762,11 @@
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 3bcafe4..cf34823 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -8,6 +8,20 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
+/ {
+ cmn_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cmn_refclk1: clock-cmnrefclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -338,24 +352,12 @@
pinctrl-single,function-mask = <0xffffffff>;
};
- dummy_cmn_refclk: dummy-cmn-refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
- dummy_cmn_refclk1: dummy-cmn-refclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
@@ -364,21 +366,21 @@
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
@@ -400,10 +402,13 @@
reg = <0x5000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
+ <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -412,7 +417,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
@@ -421,21 +426,21 @@
ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>;
};
wiz1_refclk_dig: refclk-dig {
- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>;
@@ -457,10 +462,13 @@
reg = <0x5010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
+ <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -469,7 +477,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
@@ -478,21 +486,21 @@
ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>;
};
wiz2_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>;
};
wiz2_refclk_dig: refclk-dig {
- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>;
@@ -514,10 +522,13 @@
reg = <0x5020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
+ <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -526,7 +537,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
@@ -535,21 +546,21 @@
ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>;
};
wiz3_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>;
};
wiz3_refclk_dig: refclk-dig {
- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>;
@@ -571,10 +582,13 @@
reg = <0x5030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz3 0>;
reset-names = "sierra_reset";
- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
+ <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -775,8 +789,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -788,8 +800,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -801,8 +811,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -814,8 +822,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -827,8 +833,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -840,8 +844,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -853,8 +855,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -866,8 +866,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -879,8 +877,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -892,8 +888,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -1794,6 +1788,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru0_1-fw";
};
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 119 1>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg1: icssg@b100000 {
@@ -1925,5 +1929,15 @@
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru1_1-fw";
};
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 120 4>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 5e825e4..d2dceda 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
index bf0620a..29a4d9f 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
@@ -68,3 +68,11 @@
&gpio {
status = "okay";
};
+
+&pwm_mux {
+ groups = "pwm0_gpio16_grp", "pwm1_gpio17_grp", "pwm2_gpio18_grp", "pwm3_gpio19_grp";
+};
+
+&pwm {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 17934fd..4b4231f 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -432,6 +432,15 @@
reg = <0 0x28330000 0 0x1000>;
status = "disabled";
};
+
+ pwm: pwm@241c0000 {
+ compatible = "toshiba,visconti-pwm";
+ reg = <0 0x241c0000 0 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_mux>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
index 34de000..a480c6b 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
@@ -90,4 +90,9 @@
groups = "i2c8_grp";
bias-pull-up;
};
+
+ pwm_mux: pwm_mux {
+ function = "pwm";
+ };
+
};
diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h
index 4c23eef..eb91a6c 100644
--- a/include/dt-bindings/mailbox/qcom-ipcc.h
+++ b/include/dt-bindings/mailbox/qcom-ipcc.h
@@ -29,5 +29,6 @@
#define IPCC_CLIENT_PCIE1 14
#define IPCC_CLIENT_PCIE2 15
#define IPCC_CLIENT_SPSS 16
+#define IPCC_CLIENT_WPSS 24
#endif
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
index 0359bfd..93064c7 100644
--- a/include/dt-bindings/pinctrl/hisi.h
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -1,7 +1,7 @@
/*
* This header provides constants for hisilicon pinctrl bindings.
*
- * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 HiSilicon Limited.
* Copyright (c) 2015 Linaro Limited.
*
* This program is free software; you can redistribute it and/or modify